KR100773691B1 - Delay Synchronous Loop Circuit of Semiconductor Memory Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delayed synchronous loop circuit of a semiconductor memory device, and includes a fine delay adjusting unit that can vary a delay time in accordance with a cutting state of a test signal and a fuse. Disclosed is a delayed synchronous loop circuit of a semiconductor memory device whose sex time specification can be adjusted even at the wafer level.

DLL, Fuse, Fine Delay, Wafer Level

Description

Delay locked loop circuit in semiconductor memory device

1 is a block diagram of a delay lock loop circuit of a general semiconductor memory device.

2 is a timing diagram illustrating a relationship between an external clock, a data strobe signal, and output data of a semiconductor memory device.

3 is a block diagram of a delay lock loop circuit of a semiconductor memory device according to an embodiment of the present invention.

4 is a detailed circuit diagram of the delay compensator of FIG. 3.

5 is a detailed circuit diagram of the fuse of FIG. 3.

6 is a timing diagram illustrating a relationship between an external clock, a data strobe signal, and output data of a semiconductor memory device according to an exemplary embodiment of the present invention.

Description of the main parts of the drawing

100, 200: delay synchronization loop circuit 110, 210: clock buffer section

120, 220: delay line section 130, 230: delay control signal generator

140, 240: replica delay unit 250: fine delay adjustment unit

150, 260: phase comparator 251: delay compensation unit

252: fuse

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a delay locked loop circuit of a semiconductor memory device.

In general, in the input / output method of transmitting data in synchronization with a clock signal such as a transfer between a memory device and a memory controller, it is very important to achieve time synchronization between the clock signal and data as the bus load increases and the transmission frequency increases.

In other words, the time required for the data to be loaded on the bus in response to the clock signal must be compensated for and the data must be accurately positioned at the edge of the clock signal. Circuits that can be used for this purpose include a Phase Locked Loop (PLL) and a Delay Looked Loop (DLL), and generally a DLL is used for a memory device. However, the time between the data from the clock signal is called tAC (DQ output access time from CK / CKB), and this time is specified in the specification.

1 is a block diagram illustrating a delay lock loop circuit of a general semiconductor memory device.

Referring to FIG. 1, a delay lock loop circuit 100 of a semiconductor memory device may include a clock buffer unit 110, a delay line unit 120, a delay control signal generator 130, a replica delay unit 140, and a phase. Comparator 150, and DLL driver 160.

The clock buffer unit 110 receives the external clock CLK and the external inverted clock CLKB and synchronizes with the falling edge and the rising edge of the external clock CLK to synchronize the first internal clock FCLK and the second internal clock RCLK. )

The delay line unit 120 receives the first internal clock FCLK and the second internal clock RCLK and delays the delay time controlled by the delay control signal generator 130 set by the first output clock iFCLK. And a second output clock iRCLK. The delay line unit 120 outputs the second output clock iRCLK passing through only one unit delay element to the replica delay unit 140 during an initial operation.

The delay control signal generator 130 adjusts the delay time of the delay line unit 120 in response to the control signal CTRL.

The replica delay unit 140 includes a dummy clock buffer, a dummy output buffer, and a dummy load in order to have a delay time equal to the delay time occurring in the path of the actual clock, and the second output clock passing only one unit delay element. The iRCLK is applied to output a feedback clock FBCLK that compensates for the actual delay time.

The phase comparator 150 receives the feedback clock FBCLK and the second internal clock RCLK to compare the phases of the rising edge of the feedback clock FBCLK and the rising edge of the second internal clock RCLK to control the signal CTRL. )

The DLL driver 160 receives the first output clock iFCLK and the second output clock iRCLK to generate a first DLL clock FCLKDLL and a second DLL clock RCLKDLL. The outputted first DLL clock FCLKDLL and second DLL clock RCLKDLL are clocks ahead of the external clock signal CLK by a predetermined amount of time.

2 is a timing diagram illustrating a relationship between an external clock, a data strobe signal, and output data of a semiconductor memory device.

Referring to FIG. 2, a clock skew phenomenon occurs due to a time delay caused by an internal circuit, and thus the data strobe signal DQS is earlier or later than the timing of the external clocks CLK and CLKB. As a result, the timings of the input external clocks CLK and CLKB and the output data DQ differ by tAC. To compensate for this, the DLL circuit referenced in FIG. 1 is used.

tAC is mainly determined by the replica characteristics of the DLL 10. Accordingly, the replica delay unit 140 is configured to integrate the logic gate on the actual path as it is so as to have the same change in temperature, process, and voltage change. However, due to variations in temperature, process, layout wiring, etc., it is very difficult to control the correct tAC. In addition, semiconductor memory devices use clock signals with shorter periods, so the tAC spec is decreasing (eg, ± 750 ps for DDR266, ± 450 ps for DDR667), requiring precise circuit configuration. .

The technical problem to be achieved by the present invention includes a fine delay adjustment unit that can vary the delay time according to the cutting state of the test signal and fuse, thereby changing the specification of the data extrusion time that changes with temperature, process conditions, etc., wafer level The present invention also provides an adjustable delay loop circuit of a semiconductor memory device.

A delay lock loop circuit of a semiconductor memory device according to an exemplary embodiment of the present invention includes a clock buffer unit, a delay line unit, a replica delay unit, a fine delay adjuster, a phase comparator, and a delay control signal generator. The clock buffer unit generates a first internal clock and a second internal clock in synchronization with the falling edge and the rising edge of the external clock in response to the external clock and the external inversion clock. The delay line unit receives the first internal clock and the second internal clock to delay the set delay time to generate a first output clock and a second output clock. The replica delay unit receives the second output clock to generate a first feedback clock by reflecting a delay condition of an actual clock path. The fine delay adjuster generates a second feedback clock by adjusting a delay amount of the first feedback clock in response to the plurality of test signals. The phase comparator generates a control signal by comparing a phase of the rising edge of the second feedback clock and the rising edge of the second internal clock. The delay control signal generator adjusts the delay time of the delay line unit in response to the control signal.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 is a block diagram of a delay lock loop circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the delay lock loop circuit 200 may include a clock buffer 210, a delay line 220, a delay control signal generator 230, a replica delay 240, and a fine delay adjuster 250. ), A phase comparator 260, and a DLL driver 270.

The clock buffer unit 210 includes a first clock buffer 211 and a second clock buffer 212. The first clock buffer 211 receives the external clock CLK and the external inverted clock CLKB as inputs to generate the first internal clock FCLK synchronized with the falling edge of the external clock CLK. The second clock buffer 212 receives the external clock CLK and the external inverted clock CLKB as inputs to generate a second internal clock RCLK synchronized with the rising edge of the external clock CLK.

The delay line unit 220 includes a first delay line 221 and a second delay line 22. The first delay line 221 receives the first internal clock FCLK and generates a first delay clock iFCLK. The second delay line 222 receives the second internal clock RCLK to generate a second delay clock iRCLK.

The delay control signal generator 230 includes a shift register 231 and a shift controller 232. The shift controller 232 generates control signals SR and SL for controlling the shift register 231 in response to the control signal CTRL of the phase comparator 260. The shift register 231 controls the delay times of the first delay line 221 and the second delay line 222 in response to the control signals SR and SL of the shift register 231.

The replica delay unit 240 passes the same delay condition as the actual clock path in response to the second delay clock iRCLK to generate the first feedback clock FBCLK1.

The fine delay adjuster 250 includes a delay compensator 251 and a fuse 252. The fuse unit 251 outputs a plurality of fuse signals FUSE <0: 3> in response to the plurality of test signals TM <0: 3>. The delay compensator 251 generates the second pitback clock FBCLK2 by fine-adjusting the actual delay time of the feedback clock FBCLK in response to the plurality of fuse signals FUSE <0: 3>.

The phase comparator 260 receives the second feedback clock FBCLK2 and the second internal clock RCLK to compare the phase of the rising edge of the feedback clock FBCLK and the rising edge of the second internal clock RCLK to control signals. Output (CTRL)

The DLL driver 270 includes a first DLL driver 271 and a second DLL driver 272. The first DLL driver 271 receives the first delayed clock iFCLK and outputs the first DLL clock FCLKDLL ahead of the external clock CLK by a predetermined amount of time. The second DLL driver 272 receives the second delay clock iRCLK and outputs the second DLL clock RCLKDLL ahead of the external clock CLK by a predetermined amount of time.

4 is a detailed circuit diagram of the delay compensator 251 of FIG. 3.

Referring to FIG. 4, the delay compensator 251 includes a resistance adjuster 251A, a first delay adjuster 251B, a fuse signal input terminal 251C, a second delay adjuster 251D, and an inverter I1 and I10).

The inverter I1 inverts the first feedback clock FBCLK1 and outputs the inverted clock CK1 to the node NA.

The resistance adjuster 251A includes a plurality of switches SW1 to SW5 and resistors R1 and R2. The switch SW1, the resistor R1, and the switch SW2 are connected in series between the node NA and the node NB, and according to the open or closed states of the switches SW1 and SW2, the node NA and the node ( The resistor R1 is connected or disconnected between NB). The switch SW3, the resistor R2, and the switch SW4 are connected in series between the node NA and the node NB, and according to the open or closed states of the switches SW3 and SW4, the node NA and the node ( The resistor R2 is connected or disconnected between NB). The switch SW5 is connected between the node NA and the node NB, and is connected or disconnected between the node NA and the node NB according to the open or closed state of the switch SW5. Accordingly, the inverted clock CK1 has a delay time by the resistor R1 or the resistor R2 or is output as the clock signal CK2 without a delay time depending on the open or closed states of the switches SW1 to SW5.

The first delay adjuster 251B includes a plurality of switches SW6 to SW9 and capacitors C1 and C2. The switch SW7, the gate capacitor C1, and the switch SW6 are connected in series between the power supply voltage VDD and the node D1. The capacitor C1 is connected to or disconnected from the node D1 according to the open and closed states of the switch SW6, and the power supply voltage VDD is connected to the junction of the capacitor C1 according to the open and closed states of the switch SW7. Connect or disconnect Therefore, the open and close states of the switches SW6 and SW7 are adjusted to delay the clock signal CK2 applied to the node D1 by a delay time corresponding to the capacity of the capacitor C1.

The switch SW9, the gate capacitor C2, and the switch SW8 are connected in series between the ground voltage VSS and the node D1. The capacitor C2 is connected to or disconnected from the node D1 according to the open and closed states of the switch SW8, and the ground voltage VSS is connected to the junction of the capacitor C2 according to the open and closed states of the switch SW9. Connect or disconnect Accordingly, the open and close states of the switches SW8 and SW9 are adjusted to delay the clock signal CK2 applied to the node D1 by a delay time corresponding to the capacity of the capacitor C2.

The fuse signal input terminal 251C includes a plurality of inverters I2 to I9. The inverter I2 inverts the fuse signal FUSE <0> and outputs the first input signal FS1. The inverter I3 inverts the first input signal FS1 to output the second input signal FS2. The inverter I4 inverts the fuse signal FUSE <1> and outputs the first input signal FS3. The inverter I5 inverts the first input signal FS3 and outputs the second input signal FS4. The inverter I6 inverts the fuse signal FUSE <2> and outputs the first input signal FS5. The inverter I7 inverts the first input signal FS5 and outputs the second input signal FS6. The inverter I8 inverts the fuse signal FUSE <3> and outputs the first input signal FS7. The inverter I9 inverts the first input signal FS7 and outputs the second input signal FS8.

The second delay adjuster 251D includes a plurality of junction capacitors C3 to C10 and a plurality of switches SW11 to SW25. One capacitor (e.g. C3) is connected to a node (e.g. D2) and a switch (e.g. SW10) for applying or blocking a first input signal (e.g. Or disconnecting switches (eg SW11) are connected. In more detail, the switch SW10, the junction capacitor C3, and the switch SW11 are connected in series to the node D2, and the junction capacitor C3 is connected to the node according to the open or closed state of the switch SW11. Connected to or disconnected from (D2). In addition, according to the open or closed state of the switch SW10, the second input signal FS2 is applied or blocked to the gate of the junction capacitor C3. The switch SW12, the junction capacitor C4, and the switch SW13 are connected in series to the node D2, and the junction capacitor C4 is connected to or disconnected from the node D2 according to the open or closed state of the switch SW13. do. In addition, the first input signal FS1 is applied to or blocked from the gate of the junction capacitor C4 according to the open or closed state of the switch SW12. Similar to the above structure, the plurality of switches SW14 to SW25 and the plurality of capacitors C5 to C10 are connected to the nodes D3, D4, and D5. Accordingly, the delay time of the clock signal CK2 passing through the nodes D2, D3, D4, and D5 may be adjusted by adjusting the open or closed states of the switches SW10 to SW25. In addition, various delay times may be set by different capacitance capacitances of the plurality of junction capacitors C3 to C10 in the design.

The inverter I10 is connected to the node D5 and inverts the clock signal CK2 to output the second feedback signal FBCLK2.

5 is a detailed circuit diagram of the fuse unit 252 of FIG. 3.

Referring to FIG. 5, the fuse unit 252 includes a plurality of fuse signal generators 252A to 252D. Since a plurality of fuse signal generators 252A to 252D are similar in configuration and operation, one fuse signal generator 252A will be described as an example.

The fuse signal generator 252A includes a fuse FU, a PMOS transistor PM, and a resistor R3. The fuse FU and the PMOS transistor PM are connected in series between the power supply voltage VDD and the node QA, and the PMOS transistor PM is turned on or turned off in response to the test signal TM <0>. . The resistor R3 is connected between the node QA and the ground voltage VSS. Therefore, when the low level test signal TM <0> is applied, the potential of the node QA changes according to the cutting state of the fuse FU to output the fuse signal FUSE <0>. For example, when the fuse FU is in a no-cutting state, the PMOS transistor PM is turned on in response to the low level test signal TM <0>, so that the node QA is at a high level. Therefore, the high level fuse signal FUSE <0> is output. On the other hand, when the fuse FU is cut, the node QA is discharged to the low level even when the PMOS transistor PM is turned on in response to the low level test signal TM <0>. Therefore, the low level fuse signal FUSE <0> is output.

6 is a timing diagram illustrating a relationship between an external clock, a data strobe signal, and output data of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to Figures 3 to 6 the operation of the DLL circuit according to an embodiment of the present invention will be described.

According to an exemplary embodiment of the present invention, it is assumed that the capacitance of the junction capacitors C9 and C10, the junction capacitors C7 and C8, the junction capacitors C5 and C6, and the junction capacitors C3 and C4 are large. In addition, it is assumed that the sum of capacitances of the junction capacitors C7 and C8, the junction capacitors C5 and C6, and the junction capacitors C3 and C4 is smaller than the sum of the junction capacitors C3 and C4.

First, the external clock CLK and the external inverted clock CLKB are input to the first clock buffer 211 and the second clock buffer 212. The first clock buffer 211 generates the first internal clock FCLK synchronized with the falling edge of the external clock CLK by inputting the external clock CLK and the external inverted clock CLKB. The second clock buffer 212 receives the external clock CLK and the external inverted clock CLKB as inputs to generate a second internal clock RCLK synchronized with the rising edge of the external clock CLK.

In the initial operation, the second internal clock RCLK is applied to the second delay line 222 to generate the second output clock iRCLK passing through only one unit delay element of the second delay line 222.

The second output clock iRCLK is input to the replica delay unit 240 and outputs the same. The replica delay unit 240 outputs the second output clock iRCLK to the first feedback clock FBCLK1 by passing through the same delay condition as the actual clock path.

The fuse unit 252 outputs a plurality of fuse signals FUSE <0: 3> in response to the test signals TM <0: 3>. The delay compensator 251 outputs the second feedback clock FBCLK2 by finely delaying the first feedback clock FBCLK1 in response to the plurality of fuse signals FUSE <0: 3>. In order to measure the tAC basic amount of the replica delay unit 240 and the fine delay adjustment unit 250 during the initial test operation, the test signal TM <3> is applied at a low level and the remaining test signals TM <0: 2> are applied. In other words, the tAC basic amount is defined as the sum of the delay amount of the replica delay unit 240 and the delay amount by the junction capacitors C9 and C10 of the fine delay adjustment unit 250.

 The phase comparator 260 receives the second feedback signal FBCLK2 and the second internal clock RCLK having finely adjusted delay time, so that the rising edges of the second feedback clock FBCLK and the second internal clock RCLK are adjusted. The phase of the rising edge is compared to output a control signal CTRL.

The shift controller 232 generates control signals SR and SL for controlling the shift register 231 in response to the control signal CTRL of the phase comparator 260. The shift register 231 controls the delay times of the first delay line 221 and the second delay line 222 in response to the control signals SR and SL of the shift register 231.

The first delay line 221 and the second delay line 222 adjust the delay times of the first internal clock FCLK and the second internal clock RCLK so that the first delay clock iFCLK and the second delay clock ( iRCLK).

The first DLL driver 271 and the second DLL driver 272 receive the first delayed clock iFCLK and the second delayed clock iRCLK and receive a first DLL clock FCLKDLL ahead of the external clock CLK by tAC. And a second DLL clock RCLKDLL, respectively.

When the timing of the data strobe signal and the data DQS and DQ is faster than the timing of the external clock and the external inverted clocks CLK and CLKB as shown in FIG. Is as follows.

The tAC variation according to the cutting state of the fuses FU of the plurality of fuse signal generators 252A to 252D is shown in the following table.

Fuse Status (O: no-cut, X: cut) tAC delay 252D 252C 252B 252A O X X X Base quantity O X X O Basic amount + α1 O X O X Basic amount + α2 O X O O Basic amount + α3 O O X X Basic amount + α4 O O X O Basic amount + α5 O O O X Basic amount + α6 O O O O Basic amount + α7

The delay amount of the second delay adjuster 251D of the delay compensator 251 is adjusted according to the cutting state of the fuse while the test signal TM <0: 3> is applied to the fuse 252 at a low level. do. More specifically, the test signal TM <0: 3> is adjusted to set an optimum delay amount, and the fuses 252 are programmed by cutting the corresponding fuses. The programmed fuse unit 252 outputs a fuse signal FUSE <0: 3> to a low level test signal TM <0: 3>. The second delay controller 251D outputs a second feedback clock FBCLK2 having a delay time adjusted in response to the fuse signals FUSE <0: 3>.

When the timing of the data strobe signal and the data DQS and DQ is slower than the timing of the external clock and the external inverted clocks CLK and CLKB as shown in FIG. 6B, the delay compensation unit 251 and the fuse unit 252 may be adjusted. Is as follows.

The tAC variation according to the cutting state of the fuses FU of the plurality of fuse signal generators 252A to 252D is shown in the following table.

Fuse Status (O: no-cut, X: cut) tAC delay 252D 252C 252B 252A X X X X Basic quantity -a1 X X X O Base quantity-a2 X X O X Base quantity-a3 X X O O Base quantity-a4 X O X X Basic quantity -a5 X O X O Basic quantity -a6 X O O X Basic quantity -a7 X O O O Basic quantity -a8

Operation methods of the delay compensator 251 and the fuse unit 252 for reducing the delay time are similar to those for increasing the delay time, and thus detailed description thereof will be omitted.

The delay time of the delay compensator 251 may be additionally adjusted using the resistance adjuster 251A and the first delay adjuster 251B.

For example, the resistance adjusting unit 251A adjusts an open close state of the switches SW1 to SW5 to selectively change a path connecting the node NA and the node NB to change the resistance value due to the path. . That is, when the delay amount is increased, the clock signal CK2 is generated by delaying the inverted clock CK1 by forming a path to which the resistor R1 or R2 is connected.

The first delay controller 251B may change the delay amount by adjusting the open state of the switches SW6 to SW9 to adjust the connection state of the capacitors C1 and C2 and the node D1.

The switch of the delay compensator 251 and the fuse of the fuse 252 may be adjusted by cutting with a laser at the wafer stage of the semiconductor memory device. Therefore, the DLL circuit of the present invention is adjustable at the wafer level when the data access time between the external clock and the data is over the specification after the circuit design test.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to one embodiment of the present invention, by including a fine delay adjustment unit that can vary the delay time in accordance with the cutting state of the test signal and fuse, thereby testing the data access time between the external clock and the data and the data access time is allowed If over, the micro-delay adjuster can be adjusted to allowance at the wafer level without revision of the metal mask.

Claims (9)

A clock buffer configured to generate a first internal clock and a second internal clock in synchronization with the falling edge and the rising edge of the external clock in response to an external clock and an external inversion clock; A delay line unit configured to receive the first internal clock and the second internal clock and delay a set delay time to generate a first output clock and a second output clock; A replica delay unit receiving the second output clock to generate a first feedback clock by reflecting a delay condition of an actual clock path; A fine delay adjuster for generating a second feedback clock by adjusting a delay amount of the first feedback clock in response to a plurality of test signals; A phase comparator configured to generate a control signal by comparing a phase of a rising edge of the second feedback clock and a rising edge of the second internal clock; And And a delay control signal generator configured to adjust a delay time of the delay line unit in response to the control signal. The method of claim 1, The fine delay adjustment unit may include a fuse unit configured to output a plurality of fuse signals in response to the plurality of test signals; And And a delay compensator configured to delay the first feedback clock to generate the second feedback clock in response to the plurality of fuse signals. The method of claim 2, The fuse unit includes a plurality of fuse signal generation units, wherein the plurality of fuse signal generation units respectively generate the plurality of fuse signals in response to the plurality of test signals. The method of claim 3, wherein Each of the plurality of fuse signal generators A fuse for applying or blocking a power supply voltage according to a cutting state; A transistor coupled between the fuse and an output node and controlling a potential of the output node in response to one of the test signals; And And a resistor coupled between the output node and a ground voltage, the resistor discharging the potential of the output node. The method of claim 2, wherein the delay compensation unit A resistance adjuster configured to adjust a delay time using a resistor connected to the first feedback clock; A first delay adjuster adjusting a delay time by adjusting a connection state of the switch; A fuse signal input stage configured to receive the plurality of fuse signals and output first inverted signals and second input signals inverted the first input signals; And And a second delay adjuster configured to adjust a delay time in response to the first input signals and the second input signals. The method of claim 5, wherein the resistance control unit A plurality of resistors connected in parallel between a first node and a second node, wherein both ends of each of the plurality of resistors are connected through an auxiliary switch between the first node and the second node, and an open close of the auxiliary switch. The delay lock loop of a semiconductor memory device, wherein a resistance value is different between the first node and the second node according to a state. The method of claim 6, wherein the first delay control unit And a plurality of capacitors, wherein the plurality of capacitors are connected to or separated from the second node according to the connection state of the switch. The method of claim 5, wherein the fuse signal input terminal First inverters connected to each of the plurality of fuse signals to invert the plurality of fuse signals to output the first input signals; And And second inverters connected to the first inverters, respectively, and inverting the first input signals to output the second input signals, respectively. The method of claim 6, wherein the second delay control unit A plurality of capacitors, wherein the plurality of capacitors control a delay of the first feedback clock transmitted through the second node in response to the first input signal or the second input signal. Synchronous loop circuit.

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