KR100742214B1 - Handler for semiconductor device test - Google Patents

Abstract

The present invention relates to a handler for testing semiconductor devices, the handler of the present invention comprising: a main body; A window formed on one surface of the main body to have a predetermined size; A test head having a size smaller than that of the window and mounted to the window; At least one cover plate coupled to at least one edge of the test head to convert the size of the test head to a size corresponding to the size of the window, the at least one cover plate being mounted to the window with the test head to close a portion of the window; Characterized in that configured to include.

According to the present invention, since the cover plate is integrated with the test head to convert the size of the test head to the size corresponding to the size of the window, it is possible to simply change the size of the test part and simply change the size of the other Test heads with sockets can be applied to perform tests.

Description

Handler for Testing Semiconductors

1 is a side view schematically showing the configuration of an embodiment of a handler for testing semiconductor devices according to the present invention

FIG. 2 is a rear view of the handler of FIG. 1;

3 is a front view of one embodiment of a reference testhead applied to the handler of FIG.

4 is a front view showing one embodiment of another test head and cover plate applied to the handler in FIG.

5 is a front view showing an embodiment of a test tray applied to the handler of FIG.

Explanation of symbols on the main parts of the drawings

1 main body 2 loading stacker

3: unloading stacker 4: exchanger part

5 Picker 6 Chamber

7: test head 8: mount board

10: test head 11: socket

61: preheat chamber 62: test chamber

63: heat removal chamber 64: contact push unit

65: Windows T: test tray

C: Carrier

The present invention relates to a handler for testing a semiconductor device, and more particularly, to a handler for testing a semiconductor device that can easily test a desired number of semiconductor devices by applying test heads of various sizes to a test unit. .

 In general, memory ICs or non-memory semiconductor devices and module ICs having them properly configured on a single substrate are shipped after various tests after production, and handlers are referred to as semiconductor devices and It refers to a device that is used to automatically test the module IC by electrically connecting it to an external test device.

Typically, many of these handlers not only perform general performance tests at room temperature, but also create extreme conditions of high temperature and low temperature through electrothermal heaters and liquefied nitrogen injection systems in sealed chambers, thereby providing semiconductor devices and module ICs. It is also possible to conduct high temperature and low temperature tests to test whether they can function under these extreme temperature conditions.

Korean Patent Application Publication No. 10-0384622 filed and filed by the applicant (May 22, 2003) has a large number of test sites in a short time without increasing the overall size and structural complexity of the handler. Disclosed is a handler for testing semiconductor devices that enables efficient testing of semiconductor devices.

The chamber portion of the handler is pre-heated and pre-cooled the semiconductor element to a predetermined temperature, a test chamber for performing the test, and a defrosting chamber for returning the semiconductor element to room temperature are arranged horizontally, two test chamber Since the test head is composed of two layers, the test head is configured to test more than twice as many semiconductor devices at a time as the conventional memory handler.

That is, in the conventional memory handler, one test head having a plurality of test sockets is mounted in the test chamber to perform a test, and one test tray is correspondingly connected to the test head.

On the other hand, the conventional handler developed by the present applicant can be equipped with two test heads in the test chamber, so that two test trays can be connected to each test head at a time, thus twice as many times as before. Will be able to test the semiconductor device.

However, the conventional handler as described above has the following problems.

The test head of the handler is an interface device that is electrically connected to a tester for testing the electrical performance of the semiconductor device and transmits and receives electrical signals. The test head of the handler is mounted on the test unit of the handler during the test, and is disconnected when the test is completed. The test head is called a Hi-Fix Board, and a plurality of sockets are arranged in a matrix (m × n) horizontally and vertically.

Typically, semiconductor device manufacturers want to carry out tests by mounting test heads with various number of test sockets in one handler.

For example, a semiconductor device manufacturer may decide that 128 test sockets (8 × 16 matrices) are formed in one test head (referred to as “128para test head”) in order to improve processing speed of testers in the future. Expect to install two handlers but expect to install one or more testheads (called '64para testheads') with 64 test sockets (4 x 16 matrices). do. Therefore, one handler is required to be compatible with both the 64para test head and the 128para test head.

In addition, the pitch between the test sockets varies according to the type of semiconductor device to be tested. Accordingly, the pitch between carriers of the test tray should also be correspondingly different, so that various carrier pitches can be applied in one handler.

However, the conventional handler has a fixed size of the test unit, and thus does not have compatibility with the 64para test head and the 128para test head, and there is a problem that only a single carrier pitch can be tested.

The present invention is to solve the above problems, an object of the present invention is to improve the compatibility of the handler by selectively mounting a test board having a test socket of various number and pitch in one handler to test To provide a device test handler.

The present invention for achieving the above object, the main body; A window formed on one surface of the main body to have a predetermined size; A test head having a size smaller than that of the window and mounted to the window; At least one cover plate coupled to at least one edge of the test head to convert the size of the test head to a size corresponding to the size of the window, the at least one cover plate being mounted to the window with the test head to close a portion of the window; It provides a handler for a semiconductor device test configured to include.

According to the present invention, since the cover plate is integrated with the test head to convert the size of the test head to the size corresponding to the size of the window, it is possible to simply change the size of the test part and simply change the size of the other Test heads with sockets can be applied to perform tests.

Hereinafter, a preferred embodiment of a handler for testing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the handler according to the present invention includes a loading stacker 2 and an unloading stacker 3 installed in front of the main body 1, and a semiconductor conveyed from the loading stacker 2. An exchanger unit 4 on which the test tray T on which the element is mounted is placed in a horizontal state and waiting, and the semiconductor elements are loaded into the loading stacker 2, the unloading stacker 3, and the exchanger unit 4. The picker 5 to be conveyed, the chamber part 6 to be tested while the test tray T conveyed from the exchanger part 4 moves upright, and the rear part of the chamber part 6. Removably mounted, the semiconductor elements are electrically connected, and consist of a test head 10 to be tested.

In the test head 10, a plurality of sockets 11 to which semiconductor elements are electrically connected are arranged in a predetermined matrix. The test head 10 is electrically connected to the tester 7 for analyzing and determining the electrical performance of the semiconductor device and the like, and transmits and receives electrical signals and performs a test.

The loading stacker 2 includes a plurality of customer trays (CTs) in which semiconductor devices to be tested are stored. In the unloading stacker 3, the empty customer trays CT are stacked up and down to classify and store the tested semiconductor devices conveyed from the test tray T according to the test results.

The picker 5 is configured to be movable in the X-Y-Z direction on the upper side of the main body 1, and performs a function of absorbing the semiconductor element by vacuum pressure and transporting it to a desired position.

The test tray T is made of a heat resistant metal material, and has a plurality of carriers C, which are capable of releasably fixing semiconductor elements. Here, the carrier (C) is formed in a pitch and the number corresponding to the socket 11 arranged in the test head (10).

As shown in FIG. 2, the chamber part 6 includes a preheating chamber 61 for heating or cooling a semiconductor device to a predetermined temperature state, and a test chamber in which the test head 10 is coupled to perform a test. And a heat removal chamber 63 for applying the thermal stress opposite to the preheating chamber 61 after the test is completed to return the semiconductor element to the normal temperature state again.

The preheating chamber 61, the test chamber 62, and the heat removing chamber 63 are arranged side by side on one side, and each of the upper and lower layers is configured to handle and test two test trays T at a time. .

Two windows 65 having predetermined sizes are formed on the rear surface of the test chamber 62 so as to be opened to the outside of the chamber, respectively. Each of the windows 65 is coupled to test heads 10 outside the test chamber 62. The contact push unit 64 connects the semiconductor element to the socket 11 of the test head 10 by a predetermined force by pressing the carrier C of the test tray T to the inside of each window 65. Are installed to be movable in the front-rear direction.

Each of the windows 65 is a reference test head 10 of a predetermined size (hereinafter referred to as a 'reference test head') in which sockets 11 are arranged in an (m × n) matrix, where m and n are integers greater than zero. It is formed so as to have a size almost identical to ().

For example, the windows 65 correspond to this test head 10 with reference to the test head 10 in which the sockets 11 are arranged in an 8 × 16 matrix 128para, as shown in FIG. 3. It can be formed to a size.

Thus, when the reference test head 10 is coupled to the window 65, the entire area of the window 65 is completely closed by the reference test head 10.

However, when the test is to be performed using a test head having a smaller number of sockets 11 than the sockets 11 provided in the reference test head 10, that is, the socket to which the semiconductor devices are connected is [( ma) × n] or [m × (nb)] matrix or [(ma) × (nb)] matrix, where a and b are any integer greater than 0 If desired, the size of the test head will be smaller than the reference test head 10.

Therefore, when the test head is mounted on the window 65, an area is left in which the window 65 is not completely closed. As such, when an open area is present in the window 65, air flows through the open area, so that an accurate temperature test cannot be performed in the test chamber 62, and a high temperature or low temperature fluid flows to the outside. Spills can also cause problems on stability.

Therefore, when the handler of the present invention intends to perform a test by applying a test head having a smaller size than the reference test head 10, as shown in FIG. 4, predetermined handlers are provided on at least one side of the test head 10. By joining the size of the cover plate 20 has a structure that completely closes the open area.

The cover plate 20 coupled to the edge of the test head 10 has an area capable of completely closing the window 65 together with the test head 10. That is, when the cover plate 20 is coupled to the test head 10, the horizontal and vertical sizes formed by the test head 10 and the cover plate 20 are almost the same as the horizontal and vertical sizes of the window 65. Do.

For example, when using the test head 10 having a socket arrangement of the [(m-a) × n] matrix, the test head 10 has a smaller length of the vertical side because the number of columns is smaller than that of the reference test head. Therefore, in this case, the cover plate 20 is coupled to the upper end and / or lower end of the test head 10 to secure a reduced area.

In addition, when the test head 10 having the socket array of the [m × (nb)] matrix is used, since the number of columns is smaller than that of the reference test head 10, the test head 10 has a smaller horizontal length. . Therefore, in this case, the cover plate 20 is coupled to one side or both sides of the test head 10 to secure a reduced area.

In addition, when the socket arrangement is reduced in both the horizontal row and the vertical row, the cover plate 20 may be selectively secured to the side portions and the upper and lower ends of the test head 10 to secure the reduced area.

The cover plate 20 may be made of various materials, but it is preferable that the cover plate 20 is made of a heat insulating material so that heat transfer does not occur between the inside and the outside of the test chamber 62.

In FIG. 3 and FIG. 4, reference numeral 8 denotes a mount board on which the test head 10 and / or the cover plate 20 are fixed and supported, and the mount board 8 is provided on the rear surface of the chamber part 6. While being fixed by a separate fixing means (not shown) provided, the test head 10 and the cover plate 20 to function to secure the chamber portion (6).

Meanwhile, the test tray T may have a constant size regardless of the size of the test head 10 coupled to the window 65. Because, behind the chamber 6, guide rails 67 for guiding the movement of the test tray T while supporting the upper end and the lower end of the test tray T are installed, and the size of the test tray T is If variable, the position of these guide rails 67 should also be variable. As such, when the position of the guide rail 67 is changed according to the size of the test tray T, the configuration of the chamber part 6 becomes very complicated.

Therefore, the size of the test tray T is preferably constant regardless of the size of the test head 10 mounted on the window 65. However, the carrier C mounted on the test tray T may be arranged to correspond to the arrangement of the socket 11 mounted on the window 65.

For example, as shown in FIG. 5, when the socket of the test head 10 has fewer rows than the socket of the reference test head 10, the upper or lower side of the test tray T is the reduced area. As long as the flat surface Te or the open surface without carrier C, and the other side, that is, the lower side or the upper side, the carriers C are arranged in an arrangement corresponding to the arrangement of the sockets 11 of the test head 10. .

Meanwhile, the test head 10 may vary in size depending on the arrangement of the sockets 11 (matrix), but the arrangement (the number of matrixes) of the sockets 11 mounted on the test head 10 is the same. Even when the pitch between the sockets is variable, the size may vary. Therefore, in this case as well, the size of the test head 10 can be changed to match the size of the window 65 by attaching the cover plate 20 to the edge of the test head 10.

As described above, according to the present invention, even if the size of the test head is varied according to the arrangement (number of rows) or the pitch of the sockets mounted on the test head, the cover plate is selectively attached to the edge of the test head to the size of the window. You can change the size of the testhead to suit your needs.

Therefore, since a test head having various socket arrangements and pitches having various socket arrangements can be mounted as a single handler without any structural change in the test part of the handler, the compatibility of the handler is improved.

Claims (7)

A main body; A window formed on one surface of the main body to have a predetermined size; A test head having a size smaller than that of the window and mounted to the window; At least one cover plate coupled to at least one edge of the test head to convert the size of the test head to a size corresponding to the size of the window, the at least one cover plate being mounted to the window with the test head to close a portion of the window; Handler for semiconductor device testing, including. The method of claim 1, wherein the window has a size corresponding to the size of a reference testhead in which the sockets are arranged in a (m × n) matrix, where m and n are integers greater than zero; And the test head has fewer sockets than the sockets arranged in the reference test head. The handler for testing a semiconductor device according to claim 1 or 2, wherein the cover plate is coupled to both side edges of the test head. The handler of claim 1, wherein the cover plate is coupled to at least one of an upper end and a lower end of the test head. The handler for testing a semiconductor device according to claim 1 or 2, wherein the cover plate is made of a heat insulating material. The handler for testing a semiconductor device according to claim 1 or 2, further comprising a test tray having a plurality of carriers releasably mounted to the semiconductor device to be tested and positioned in the window. The test tray of claim 6, wherein the test tray has a size corresponding to that of the window, and the carrier of the test tray is arranged to correspond one-to-one with a socket arranged in the test head, and the cover plate of the area of the test tray. A handler for testing semiconductor devices, wherein the corresponding area consists of a flat or open surface without carriers.

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