KR100731449B1 - Pulse generator circuit and electronic device using this circuit, mobile phone, personal computer, and information transmission method using this circuit - Google Patents

Abstract

It is an object of the present invention to provide a pulse generating circuit which can be easily generated in a high frequency band with low power consumption in a simple circuit, and can be realized without using an expensive semiconductor process.

Inverter circuits 101 to 109, which are connected in a predetermined number of stages, and one inverter circuit input / output side in these inverter circuits 101 to 109 are connected at intervals of one step, and the inverters of the connected stages are connected. A plurality of NAND circuits 110 to 113 for generating pulses of a time width corresponding to the delay amounts of the circuits 102, 104, 106, and 108, and a NOR circuit that takes a logical sum of the outputs of these NAND circuits 110 to 113 ( 114).

Description

Pulse generating circuits and electronic devices, mobile phones, personal computers using the circuits, and information transmission methods using the circuits USING THIS CIRCUIT}

1 is a view and an operation time chart of a pulse generating circuit according to a first embodiment of the present invention;

2 is a diagram of a pulse generating circuit according to a second embodiment of the present invention;

3 is a diagram of a pulse generating circuit according to a third embodiment of the present invention;

4 is a diagram of a pulse generating circuit according to a fourth embodiment of the present invention;

5 is a diagram of an pulse generation circuit and an operation time chart according to the fifth embodiment of the present invention;

6 is a waveform diagram of pulses to be generated in the pulse generating circuit according to the present invention;

7 is a circuit diagram of a pulse generating circuit according to a sixth embodiment of the present invention;

8 is a time chart for explaining the operation of the pulse generating circuit according to the sixth and second embodiments of the present invention;

9 is a circuit diagram of a pulse generating circuit according to a seventh embodiment of the present invention;

10 is a time chart and a circuit diagram for explaining the operation of the pulse generating circuit according to the eighth embodiment of the present invention;

FIG. 11 is a diagram illustrating the invention in which the pulse generating circuit described with reference to FIGS. 1 to 10 is applied to each other so that an electronic circuit is mounted on each of them to carry out a signal transmission between two housing bodies coupled by a mechanism unit by wireless communication. A block diagram showing an example of the configuration of an electronic device as an embodiment;

FIG. 12 is a diagram illustrating an example in which the wireless communication described with reference to FIG. 11 is applied to a clamshell type mobile telephone. FIG.

FIG. 13 is a diagram illustrating an example in which the wireless communication described with reference to FIG. 11 is applied to a rotary mobile phone.

14 is a diagram showing an example in which the wireless communication described with reference to FIG. 11 is applied to a notebook personal computer;

FIG. 15 is a diagram showing the configuration of a liquid crystal projector which is one embodiment of an electronic device according to the present invention; FIG.

16 is an explanatory diagram for explaining a pulse used in UWB communication;

17 is an explanatory diagram for explaining another pulse used for UWB communication;

18 is a view and an operation time chart of a conventional pulse generating circuit.

<Explanation of symbols for main parts of drawing>

101, 102, 103, 104, 105, 106, 107, 108, 109, 202, 203, 501, 502: inverter circuit constituting a delay circuit

110, 111, 112, 113, 315, 504, 505, 506: Negative AND Circuit

114, 503, 507: Negative-OR circuit 209: Ring oscillation circuit

206: phase comparison circuit 207: charge pump

208: low pass filter 205: phase locked loop

311, 312, 313, and 314: buffer circuits forming a delay circuit

307: delay comparison circuit 403: switch

701, 702, 703, 704, 705, 706, 707, 708, 709, 901, 902, 903, 904, 905, 906, 907, 908, 909: inverter circuit constituting the delay circuit

710, 711, 712, 713, 714, 715, 716, 717, 718, 719, 720, 721, 722, 723, 724, 725, 910, 911, 914, 915, 918, 919, 922, 923: switch Composing transistor

912, 916, 920, 924: NAND circuit 913, 917, 921, 925: NOR circuit

729, 929: node giving the first potential level

726, 926: Nodes to give the seventh potential level

The present invention relates to a circuit for generating a pulse suitable for ultra wide band (UWB) communication, an electronic device using the circuit, and a method for transmitting information using the circuit.

UWB communication is a communication method that performs high-speed, large-capacity data communication using a very wide frequency band. The communication method using a wideband signal includes a conventional spread spectrum method or orthogonal frequency division multiplexing (OFDM). However, UWB is a more broadband communication method using a very short pulse, and an impulse radio (IR) communication method. It is called. In the IR system, modulation and demodulation can be performed only by time-base operation that does not depend on conventional modulation, and it is expected to simplify circuits and reduce power consumption (see Patent Documents 1, 2, and 3).

Here, the pulse waveform used for the IR method will be briefly described. As shown in Fig. 16A, the pulse width P _D and the pulse string of the period T _P are well known, and the frequency spectrum of the pulse string is shown in Fig. 16B. As is the sinc function with the first zero at the frequency where the envelope is BW = 1 / P _D.

Such a pulse is difficult to use because the spectrum extends from direct current to BW, and a pulse at a point where the center frequency f of the spectrum is high as shown in Fig. 17B is preferred.

In other words, the pulse waveform shown in Fig. 17A is multiplied by the rectangular wave of frequency f ₀ = 1 / 2P _W to shift the frequency spectrum upward. However, this waveform includes a direct current (DC) component as shown by dashed line 1701 in FIG. 17A and does not have a spectrum exactly as shown in FIG. There are many other pulse waveforms that are ideal for UWB communication, and they are often used because they are different from the waveforms shown here, but they are simple to generate.

FIG. 18A is a conventional circuit example for generating a pulse as shown in FIG. 17A (Non-Patent Document 1).

As shown, the two inverters 1801 and 1802 and the NOR circuit 1803 have three stages when the other input C of the NOR 1803 is false (L: low level). Configure a ring oscillator. That is, as shown in the time chart shown in Fig. 18B, C oscillates by L, and the outputs NR1, N1, N2 of the NOR 1803 and the inverters 1701, 1802 are delayed by time t, respectively. Change is propagating. For simplicity, it is assumed that the rise times and fall times of the NOR 1803 and the inverters 1701 and 1802 are all the same. Therefore, the pulse width (P _{W in} Fig. 17 (a)) generated in this circuit is 3t. That is, three times the delay time of the elements constituting the circuit is the shortest pulse width that can be generated.

(Patent Document 1) US Pat. 6421389

(Patent Document 2) Pub. No. US2003 / 0108133A1

(Patent Document 3) Pub. No. US2001 / 0033576

(Non-Patent Document 1) A CMOS IMPULSE RADIO ULTRA-WIDE BAND TRANCEIVER FOR 1 Mb / s DATA COMMUNICATION AND ± 2.5 cm RANGE FINDINGS T. Teradaet. al, 2005, Symposiumon on VLSI Circuits Digest of Technical Papers, pp. 30-33

However, with the above-described conventional pulse generating circuit, if one wants to obtain a pulse of a high frequency band required, one must use an element having a sufficient speed, but in reality, it is very difficult or impossible to obtain such an element.

In general, since power consumption increases when the device is operated at high speed, an increase in power consumption is inevitable when a very short pulse is obtained in such a conventional circuit. Further, the reduction in power consumption is intended to wirelessly transmit and receive signals at extremely short distances, such as between a plurality of housing bodies divided in such a manner as to allow relative displacement with respect to posture or position, or within the same housing body. It is strongly expected even if you do.

Accordingly, an object of the present invention is to provide a pulse generating circuit which can easily generate a pulse in a high frequency band and has a simple configuration and low power consumption, an electronic device using the circuit, and information transmission using the circuit. To provide a way.

In order to solve the above problems, the present application proposes the following technique.

According to the pulse generation circuit of one embodiment of the present invention, a plurality of delay elements are cascaded so as to form a predetermined loop, and a predetermined input pulse is supplied to the start end of the cascade connection. In this case, a frequency effective by a logic circuit to a signal appearing in a plurality of predetermined portions of each of the nodal portions between the plurality of delay elements and the termination portions of the slave connection. A multiplication process is performed so as to obtain an output pulse having a frequency higher than that of the input pulse.

In this pulse generating circuit, a pulse output of a predetermined frequency can be obtained by a plurality of delay elements cascaded so as to constitute a predetermined loop, and the pulse output is used for each of the nodal portion between the plurality of delay elements and the termination portion of the slave connection. An effective frequency multiplication process is performed by a logic circuit to a signal appearing in a plurality of predetermined portions of the portion, whereby a desired high frequency output pulse can be obtained.

Moreover, according to the pulse generation circuit which concerns on one form of this invention, the time equivalent to the delay amount per stage of the said delay circuit connected to the delay circuit connected by the predetermined stage and the output of the said delay circuit. A plurality of first logic circuits for generating a pulse of width and a second logic circuit for taking a logical sum of the outputs of the first logic circuits are provided.

As a result, since a plurality of delay amounts of the delay circuit can be extracted and synthesized by the logic circuit, it is possible to narrow the pulse width of the generated pulses up to the delay amount of the delay circuit. In the prior art, a significant improvement is possible with the narrowest width which can obtain three times the delay amount of the delay circuit. The delay circuit can be constituted by a buffer circuit or the like of a semiconductor element, and when the element having a fast response speed is used, the pulse width can be shortened up to the delay time during the fastest operation of the element.

In addition, according to the pulse generating circuit of one embodiment of the present invention, a delay circuit formed by cascade-dependent connection of a buffer circuit in which a delay amount is electrically controlled, and an output of the delay circuit, A plurality of first logic circuits generating pulses of a time width corresponding to the delay amount, a second logic circuit taking a logical sum of the outputs of the first logic circuits, and a delay amount of the delay circuit and a reference delay amount are compared. And a circuit for controlling the delay amount of the buffer circuit by the output of the comparison circuit.

As a result, the delay circuit can be realized by a simple connection of a buffer circuit, so the implementation is easy. In addition, since the delay amount is controlled in comparison with the reference delay amount, high precision pulses can be generated. In particular, manufacturing problems such as deviation due to semiconductor processes can be easily solved.

In addition, according to the pulse generating circuit of one embodiment of the present invention, a delay circuit formed by cascade-dependent connection of a first buffer circuit in which a delay amount is electrically controlled, and an output of the delay circuit, are connected to one of the delay circuits. A plurality of first logic circuits for generating pulses of a time width corresponding to a delay amount per unit, a second logic circuit for taking a logical sum of the outputs of the plurality of first logic circuits, and electricity similar to the first buffer circuits; An oscillation circuit having a second buffer circuit having characteristics, and comparing the output and reference frequency of the oscillation circuit including the oscillation circuit so that the oscillation frequency of the oscillation circuit is phase-locked to the reference frequency. A phase locked loop for feedback-controlling a delay amount, wherein the delay amount of the first buffer circuit controls the feedback of the phase locked loop It characterized in that the same control.

As a result, the delay circuit can be realized by a simple connection of a buffer circuit, so the implementation is easy. In addition, since the delay amount is controlled according to the result of comparing the oscillation frequency of the oscillation circuit using the element equivalent to the element which constitutes the delay circuit with the reference frequency, it can easily generate a high precision pulse. In particular, manufacturing problems such as deviation due to semiconductor processes can be easily solved.

In addition, according to the pulse generating circuit of one embodiment of the present invention, a delay circuit formed by cascade-dependent connection of a buffer circuit in which a delay amount is electrically controlled, and an output of the delay circuit, A plurality of first logic circuits generating pulses of a time width corresponding to a delay amount, a second logic circuit which takes a logical sum of the outputs of the first logic circuits, an output of a buffer circuit at a predetermined stage of the delay circuit, and a corresponding A switch means for connecting to an input of a delay circuit to form a ring oscillation circuit, a phase locked loop including the ring oscillating circuit, and a signal when the phase locked loop is locked to a reference frequency of the buffer circuit. Means for maintaining the delay amount as a control signal, wherein the phase locked loop is released, and the timing of operation of the first and second logic circuits is released. The amount of delay of the buffer circuit is characterized in that in a controlled time so as to be equal to the delay amount at the time of locking of the phase locked loop.

As a result, since the delay amount of the buffer circuit constituting the pulse generator circuit is configured to switch the buffer circuit to form a phase locked loop, the control voltage at the time of lock is maintained and used for pulse generation, thereby enabling accurate pulse generation. .

Moreover, according to the pulse generation circuit which concerns on one form of this invention, the oscillation circuit formed by connecting the delay circuit of one stage and one gate circuit in a loop shape, and the delay of each said stage from the output of each stage of the said oscillation circuit. A plurality of first logic circuits for generating pulses of a time width corresponding to the amount and a second logic circuit for taking a logical sum of the outputs of these first logic circuits are provided.

As a result, the oscillation of the ring oscillation circuit is controlled by the gate circuit, and while the oscillation circuit is oscillating, the pulse string corresponding to the delay amount of each stage is extracted by the first and second logic circuits and is a thin pulse. Can produce heat. In addition, since the pulse generator can continuously generate pulses while the oscillation circuit continues to oscillate, a pulse train having a large number of fingers can be generated without increasing the number of circuit elements.

Moreover, according to the pulse generation circuit of one embodiment of the present invention, the delay circuit can be controlled so that the delay amount can be controlled to be a predetermined value.

As a result, the delay amount of the delay circuit can be controlled, so that a pulse having a desired pulse width can be easily obtained.

In addition, according to the pulse generating circuit of one embodiment of the present invention, an oscillation circuit formed by connecting a plurality of buffer circuits and gate circuits in which the delay amount is electrically controllable in a loop shape, and a corresponding angle from an output of each stage of the oscillation circuit. A plurality of first logic circuits generating pulses having a time width corresponding to the delay amounts of the stages, a second logic circuit which takes a logical sum of the outputs of the first logic circuits, the delay amounts of the stages and a reference delay amount And a circuit for controlling the delay amount of the buffer circuit by the output of the comparison circuit.

As a result, the oscillation circuit can be implemented by a simple connection of a buffer circuit, so that the implementation is easy. Also, since the delay amount is controlled in comparison with the reference delay time, high precision pulses can be generated. In particular, manufacturing problems such as deviations caused by semiconductor processes can be easily solved. In addition, while the oscillation circuit continues to oscillate, pulses can be generated continuously so that a pulse train having a large number of fingers can be generated without increasing the number of elements in the circuit.

In addition, according to the pulse generating circuit of one embodiment of the present invention, an oscillation circuit formed by connecting a plurality of first buffer circuits and gate circuits in which a delay amount can be electrically controlled in a loop shape, and from the output of each stage of the oscillation circuit A plurality of first logic circuits generating pulses of a time width corresponding to the delay amounts of the respective stages, a second logic circuit taking a logical sum of the outputs of the first logic circuits, and electricity similar to the first buffer circuits; An oscillation circuit having a second buffer circuit having characteristics, and comparing the output and reference frequency of the oscillation circuit including the oscillation circuit so that the oscillation frequency of the oscillation circuit is phase-locked to the reference frequency. A phase locked loop for feedback-controlling a delay amount, wherein the delay amount of the first buffer circuit is a feedback agent of the phase locked loop. It is characterized in that the same control.

As a result, since the oscillation circuit can be realized by a simple connection of a buffer circuit, the implementation is easy. In addition, since the delay amount is controlled in comparison with the reference delay time, high-precision pulses can be generated. In particular, manufacturing problems such as deviation due to semiconductor processes can be easily solved. In addition, since the pulses can be continuously generated while the oscillation circuit continues to oscillate, a pulse train having a large number of fingers can be generated without increasing the number of circuit elements.

Moreover, according to the pulse generation circuit which concerns on one form of this invention, the said controllable buffer circuit consists of a CMOS inverter and a means which controls the electric current which flows into the said CMOS inverter. It is characterized by the above-mentioned.

As a result, since the control of the delay time can be realized by a simple MOS circuit, the implementation is easy.

 In addition, according to the pulse generating circuit of one embodiment of the present invention, the controllable buffer circuit is a buffer circuit having a CMOS current mode logic circuit, and the delay amount is controlled by controlling the inflow current of the buffer circuit. It features.

Accordingly, since the delay circuit is composed of a CMOS current mode logic circuit, the delay circuit can be operated at the maximum speed of the CMOS circuit without a significant increase in operating power.

Moreover, according to the pulse generation circuit of one embodiment of the present invention, the first and second logic circuits comprise a CMOS current mode logic circuit.

Accordingly, since the logic circuit is composed of a CMOS current mode logic circuit, the logic circuit can be operated at the maximum speed of the CMOS circuit without a significant increase in operating power. In addition, it is easy to generate a signal of low amplitude enough to be used for normal UWB communication.

Moreover, the pulse generation circuit which concerns on one form of this invention is the delay circuit of the cascaded N + 1 stage (N is a positive integer), and the i (i is 2 <= i≤N even) th stage of the said delay circuit. output D _i D _i and i-1 of the output of the first logical product circuit which takes the logical product of the logical negation XD _{i -1} of the output of the second stage, i-th stage of the delay circuit and the negative logic of said delay circuit XD _i A second AND circuit that takes the logical product of D _{i +1} of the output of the i + 1 th stage of the delay circuit, and a first potential level when the first AND circuit output is true, and when the second AND circuit output is true And a switch means for connecting to the second potential level and otherwise to the third potential level.

According to the above configuration of the present invention, the delay circuit is formed by the logical product of the output of the i-th stage (2 ≦ i ≦ N) of the delay circuit of the cascaded N + 1 stage (N is an integer) and the previous output thereof. A pulse having a width corresponding to the delay amount per stage is generated and alternately connected to the first potential level and the second potential level for each pulse width period, and the third potential level when the output of the AND circuit is not true. Since it is connected to, it is possible to generate a pulse having no DC component. In addition, since the circuit does not involve an analog circuit that handles a small signal, it can be realized by a logic circuit by a simple CMOS semiconductor integrated circuit, which makes it easy to reduce power consumption and cost.

The pulse generating circuit of one embodiment of the present invention is characterized in that the delay circuit is controlled such that the delay amount can be controlled and the delay amount is a predetermined value.

According to the above-described configuration of the present invention, the delay circuit can control the delay amount of each stage, whereby a pulse train of a predetermined pulse width can be obtained.

Moreover, according to the pulse generation circuit which concerns on one form of this invention, the said delay circuit is comprised by the MOS inverter of the N + 1 stage | stage, and the means for controlling the power supply current which flows into the said inverter, The said delay is controlled by control of a power supply current. The delay amount of the circuit is controlled to be a predetermined value.

According to the above configuration of the present invention, the delay circuit can be configured by a simple MOS inverter, and the delay amount can be easily adjusted by controlling the power current flowing into the inverter, so that the delay circuit is simple and easy to configure. The delay amount can be set to a predetermined value.

The pulse generating circuit of one embodiment of the present invention is characterized in that the first or second logical product circuit has a means for controlling so that the transition time of the output signal does not overlap.

According to the above configuration of the present invention, since the switch means is controlled so that the transition time of the output signal of the logical AND circuit does not overlap, the switch means does not short-circuit between the first and second potential levels. Therefore, it is possible to reduce the inrush current, the so-called short current, into the circuit, which has a great effect on reducing the power consumption of the circuit.

The pulse generating circuit of one embodiment of the present invention obtains the logical product of the output D ₂ of the second stage of the delay circuit and the negative logic XD ₁ of the output of the first stage of the delay circuit among the first AND circuits. a logical product circuit, and the first logical product circuit which takes the product logic of D _{N + 1} in N + 1 of the second-stage output of N of the second-stage output D _N negative logic XD _N and the delay circuit of the delay circuit of the second logical product circuit that And a means for setting the time for which the output becomes true to be shorter than that of the other.

According to the said structure of this invention, the time connected to the 1st or 2nd electric potential level can be set short in the leading edge and the trailing edge of an output pulse. This makes it possible to output a good signal waveform even when the load of the signal output circuit, particularly the capacitive load, is heavy.

The pulse generation circuit of one embodiment of the present invention takes the logical product of the output D ₂ of the second stage of the delay circuit and the negative logic XD ₁ of the output of the first stage of the delay circuit among the first AND circuits. by a logical product circuit, a logical aND circuit which takes the second logical product circuit multiplication of the logic of the D _{N + 1} in N + 1 of the second-stage output of N of the second-stage output D _N negative logic XD _N and the delay circuit of the delay circuit The switch means to be controlled is characterized in that its conduction impedance is set larger than that of other switch means.

According to the above-described configuration of the present invention, since the conduction impedance of the switch means is set larger than that of the other when the switch means conducts, the rate at which the output load capacity is charged and discharged can be controlled. As a result, a good pulse waveform can be obtained by adjusting the deformation of the output pulse.

The pulse generating circuit of one embodiment of the present invention omits the first stage of the delay circuit and connects an input signal to the delay circuit instead of the first stage output signal.

According to the above configuration of the present invention, since the first stage of the delay circuit can be omitted, the number of circuit elements can be reduced, and there is a slight but cost advantage and an effect of reducing power consumption. In addition, since the present invention can be configured as a logic circuit by a CMOS integrated circuit, it can be configured to operate at the highest speed of the CMOS circuit simply and without increasing the operating power, so that high-frequency broadband pulses that can be used for UWB communication can be configured. It can be easily generated.

On the other hand, the electronic device of one embodiment of the present invention wirelessly performs transmission and reception of signals between a plurality of housing bodies in which electronic circuits are mounted to each other by a coupling mechanism unit so as to allow relative displacement with respect to posture and position. The radio unit for each is provided in the said housing body, and the said radio part is comprised by applying the pulse generation circuit in any one of the said various forms, It is characterized by the above-mentioned.

In such an electronic device, since the required information can be transmitted and received between the two housing bodies by radio, the coupling mechanism portion can be simplified, and the radio section employs any one of the above-described pulse generation circuits. Because of this configuration, it is possible to reduce the size and to reduce the power consumption.

Moreover, the mobile telephone which concerns on one form of this invention is the 1st housing body and the 2nd housing body which are couple | bonded by the coupling mechanism part so that relative displacement is permissible with respect to a posture or a position, and the electronic circuit was mounted, respectively, and the said 1st In order to carry out a signal transmission between a housing body and a 2nd housing body wirelessly, each radio part provided in each of the said 1st housing body and a 2nd housing body is provided, Moreover, the said radio part is the said various form. It is characterized by being comprised by applying any one of the pulse generating circuits.

Such a mobile phone is a so-called cramshell type or a rotary type. However, since the required information can be wirelessly transmitted between the two housing bodies, the coupling mechanism can be simplified. Since the pulse generating circuit of any one of the above forms is applied, it can be miniaturized and the effect of reducing power consumption is also great.

In addition, the personal computer of one embodiment of the present invention includes a first housing body and a second housing body coupled to each other by a coupling mechanism so as to allow relative displacement with respect to posture and position, and each having an electronic circuit mounted thereon; In order to carry out a signal transmission between a housing body and a 2nd housing body wirelessly, each radio part provided in each of the said 1st housing body and a 2nd housing body is provided, Moreover, the said radio part is the said various form. It is characterized by being comprised by applying any one of the pulse generating circuits.

In such a personal computer, since the required information is transferred between the two housing bodies by radio, the coupling mechanism portion can be simplified, and the radio section can be applied to any one of the above-described forms of pulse generator circuits. Since it is comprised, it can be miniaturized and the effect of reducing power consumption is also large.

Moreover, the electronic device which concerns on one form of this invention is equipped with the at least one pair of radio | wireless parts for performing the number of signals by radio | wire | wire mutually among the several circuit blocks or circuit boards mounted in the same housing body. Moreover, the said wireless part is comprised by applying the pulse generating circuit in any one of the said various forms, It is characterized by the above-mentioned.

In such an electronic device, transmission and reception of signals between a plurality of circuit blocks or circuit boards can be made wireless by electromagnetic waves, and since signals are propagated through the space, there is no need for wiring using a flexible board or a connector. As a result, concerns over an increase in cost and a decrease in reliability due to these problems are disregarded.

In addition, the information transmission method of one embodiment of the present invention is coupled by a coupling mechanism so as to allow relative displacement with respect to posture or position, and wirelessly transmits and receives signals between a plurality of housing bodies in which electronic circuits are mounted. An information transmission method to be carried out, characterized in that the reception of the signal by the radio is performed by applying any one of the above-described pulse generating circuits.

In this information transmission method, since the required information is transferred between the two housing bodies by radio, the coupling mechanism unit can be simplified, and the transmission and reception of signals by the radio unit can be carried out by any one of the various forms described above. Since the pulse generating circuit is applied, the effect of reducing power consumption is also great.

(Embodiment of the Invention)

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described, referring drawings.

(1st embodiment)

Fig.1 (a) is a circuit diagram which showed the principal part of the pulse generating circuit which concerns on 1st Embodiment of this invention, (b)-(d) is a time chart for demonstrating the operation. However, as an example, the case where four pulses are included in the time P _{D in} the pulse waveform shown in FIG. 6 (a) (P _D = 8P _W ), that is, the pulse having four fingers will be described.

Reference numerals 101 to 109 shown in Fig. 1A are cascaded inverter circuits. Each input / output terminal is assigned a terminal name such as D0 to D9.

When the input terminal D0 changes from the high level H to the low level L as shown in the figure (b), each output propagates with a delay of t.

The NAND circuits 110 to 113 are each of the terminals ND1 to D1 as shown in Fig. 3C when D1 and D2, D3 and D4, D5 and D6, D7 and D8 are both H. L is output from ND4). NOR circuit (negative logic OR circuit) 114 outputs H as shown in the drawing (d) when any of ND1 to ND4 is L. FIG. As described above, the target pulse waveform is obtained.

In the drawing (d), the output level does not sufficiently deviate. However, the signal strength used for UWB communication is regulated by law, and the strength is too strong at a sufficiently elevated level of ordinary logic circuits. In such a case, the attenuation circuit must be inserted separately to weaken the signal level of the pulse. For this reason, the side of the signal that is not raised enough is rather convenient to use.

In addition, although the output of the last stage inverter circuit 109 is not used, the fan-out (load) connected to the inverter circuits 101-108 to the front end is adjusted, and each stage is adjusted. It is input to make the delay amount constant. Similarly, it is better to use the inverter having the same characteristics as that of the inverter circuit 101 at the foremost stage so that the signal input to the negative AND circuit 110 is driven by the inverter having the same characteristics.

The pulse train of the period Tp as shown in Fig. 6A can be obtained by inputting the signal as falling once at the time Tp shown in Fig. 6A to the terminal D0.

Here, the pulse width of the pulses output by the negative AND circuits 110 to 113 is only the delay time td from the rising of the input of the inverter circuits 102, 104, 106 and 108 to the falling of the output. It is three times more effective than 3td of.

That is, according to the pulse generation circuit of the first embodiment, it is possible to generate short pulses having a high frequency component that cannot be achieved in the conventional circuit. In addition, since the pulse generating circuit has a simple circuit configuration in which respective circuits of an inverter, NAND, and NOR are combined, a UWB communication system can be realized by a semiconductor integrated circuit by a simple CMOS process.

(2nd embodiment)

FIG. 2 is a circuit diagram showing an essential part of a pulse generating circuit according to a second embodiment of the present invention.

202 and 203 are inverter circuits whose delay amount can be controlled and correspond to the inverter circuits 101 and 102 constituting the delay circuit of the first embodiment. Equivalent circuits should be arranged in necessary stages. In Fig. 2, the numbers after the third stage are not numbered. This inverter circuit 202 is comprised by the combination of PMOS transistor M3 and NMOS transistor M1.

PMOS and NMOS transistors M4 and M2 are connected to a source of each of the transistors M3 and M1. By controlling the amount of inflow current into the inverter circuit by M3 and M1, the M4 and M2 are controlled. It is possible to control the delay amount.

The gate of the transistor M2 is connected to the control voltage terminal 211, and the gate of the transistor M4 is connected to the control voltage terminal 211 via the current mirror circuit 204, and the control voltage terminal ( The voltage applied to 211) is connected to the voltage inverted from VDD.

In addition, this inverter structure is the same also in the circuit shown by each of the other reference numbers M5-M8, M9-M12, and M13-M16.

The inverter circuit constructed as described above is connected to the required stage to form a delay circuit. D0 to Dn (n is the necessary number of stages) in FIG. 2 correspond to D0 to D9 in FIG. 1 and the like, and are connected to logical AND circuits as in the first embodiment (omitted in the drawing), and generate a target pulse. The terminal 201 is a trigger terminal, which corresponds to D0 in FIG. 1, and a target pulse is generated based on the pulse input to the terminal 201.

In order to control the delay amount of the delay circuit, the voltage applied to the control voltage terminal 211 can be precisely determined as described below, so that a pulse having a high accuracy pulse width can be generated.

209 is a ring oscillation circuit composed of an inverter circuit having the same electrical characteristics as the inverter circuits 202 and 203. This ring oscillation circuit 209 can also control the delay amount by controlling the current flowing into the inverter constituting the ring oscillation circuit, thereby converting the oscillation frequency. That is, the oscillation frequency is changed by the voltage applied to the terminal 212.

The output 213 of the ring oscillation circuit 209 is phase compared with the reference frequency applied to the reference frequency terminal 210 by the phase comparison circuit 206, and this phase difference is output. The charge pump 207 outputs electric charges to the low pass filter 208 in accordance with the phase difference signal output from the phase comparison circuit 206. The output of the direct current component of the low pass filter 208 is applied to the control voltage terminal 212 of the ring oscillation circuit 209. Therefore, the ring oscillation circuit 209, the phase comparison circuit 206, the charge pump 207, and the low pass filter 208 form the phase locked loop 205.

The voltage of the control voltage terminal 211 is controlled so that the oscillation frequency of the output 213 of the ring oscillation circuit 209 always matches the reference frequency applied to the reference frequency terminal 210. This voltage can also be used for delay amount control of the inverter circuits 202 and 203 constituting the delay circuit, so that the delay amount is the same as the delay amount of the inverter circuit of the ring oscillation circuit 209. Since the inverter circuits 202 and 203 serving as the delay circuit and the inverter circuit of the ring oscillation circuit 209 are made to have the same electrical characteristics, their delay amounts coincide.

In addition, although the ring oscillation circuit 209 shows the case comprised by the 3-stage delay circuit shown with the reference numbers M19-M32 in 2nd Embodiment, if necessary, it is oscillated by configuring more oscillation circuit of a stage. The frequency can also be lowered to facilitate configuration. In addition, it is common to insert a divider circuit between the phase comparison circuit 206 and the output of the ring oscillation circuit 209 so as to suit the value of the reference frequency (not shown).

According to the pulse generation circuit of this second embodiment, it is possible to accurately generate the target pulse. This can not only set the pulse width of the pulse to be output freely, but also eliminate various error factors due to the process variation of the semiconductor integrated circuit constituting the circuit, thereby increasing the product yield of manufacturing. In addition, it becomes easy to manufacture and can lower manufacturing cost.

In the pulse generating circuit of this second embodiment, the inverter circuit of the ring oscillation circuit 209 and the inverter circuits 202 and 203 of the delay circuit have been described on the premise that the electrical characteristics are the same, but the characteristics are similar to each other even if they are not the same. Accordingly, it is possible to eliminate error factors such as manufacturing deviation. In addition, by changing the configuration of the phase locked loop 205, for example, by inserting a frequency divider circuit between the output of the ring oscillation circuit 209 and the phase comparison circuit 206, the change of the reference frequency or The degree of freedom in designing the phase locked loop 205 can be increased, and the load can be reduced by reducing the scale of the voltage generating circuit for controlling the delay amount of the delay circuit.

Therefore, the pulse generation circuit of the second embodiment can easily generate a high precision pulse having a wide and high frequency component in a simple circuit. In addition, various error factors such as manufacturing variation of semiconductor integrated circuits can be eliminated, and manufacturing is easy.

(Third embodiment)

3 is a circuit diagram showing a main part of a pulse generating circuit according to a third embodiment of the present invention.

311 to 314 are buffer circuits configured as current mode logic circuits. The buffer circuit 311 is described here as an example, and the differential amplifier circuit is constituted by the NMOS transistor differential pairs M1 and M2. The NMOS transistor M3 controls the delay amount by limiting the circuit current in accordance with the control voltage 310 applied to the gate thereof. The PMOS transistors M4 and M5 become loads on the output side and control the output amplitude by the gate applied voltage. The buffer circuit 311 is driven by the differential signal which is characteristic of the current mode logic circuit.

The terminal 301 is a trigger terminal, which corresponds to the terminal D0 of the first embodiment, and a target pulse is generated based on the pulse input thereto. In the present embodiment, the trigger signal is not a differential but an example of a normal logic signal, and the differential signal D0 is generated by the inverter circuit U1 to connect to the current mode logic circuit.

Each of the buffer circuits 311 to 314 generates differential delay signals D1 to Dn. In these circuits 311 to 314, D1 is made directly from D0, and the conditions are different from, for example, that D2 is made from D1. That is, D1 of the buffer circuit 311 is driven by the trigger signal applied to the trigger terminal 301 and the inverter circuit U1, while D2 is made by driving the D1. If this difference is anxious, insert the circuit of the same characteristic of another stage in front of D1.

D1 to Dn are sent to the logic circuit to produce the desired pulse. 315 is a logic circuit that takes a logical product of D1 and D2, and outputs a logical product ND1. ND1 is sent to the OR circuit together with the outputs of other AND circuits as in the first embodiment to produce a desired pulse (these circuits are not shown).

The output Dn of the buffer circuit 314 at the final stage of the delay circuit is compared by the comparison circuit 307 with a reference pulse in which the delay amount of the delay circuit is input to the terminal 305. That is, the time from the trigger signal input to the terminal 301 to the output of Dn and the pulse width of the reference pulse input to the terminal 305 are compared by the comparison circuit 307, and the result is generated by the control voltage. Transfer to circuit 308. The control voltage generation circuit 308 outputs the control voltage 310 to adjust the delay amount of the delay circuit based on the comparison result of the comparison circuit 307, and each buffer circuit 311 to 314 constituting the delay circuit. Is applied to the gate of the current limiting transistor (NMOS transistor).

At the same time, when the inflow current of each of the buffer circuits 311 to 314 changes, the output amplitude also changes with it, so that the gate voltage 309 of the load transistor (PMOS transistor) on the output side is changed in accordance with the change of the control voltage 310. It is also changed to control the output amplitude to be constant. In the pulse width control of the third embodiment, the first generated pulse is subject to an error, but after the second time, the control voltage can be corrected based on the previous result, so that an accurate pulse can be generated. In applications such as UWB communication, the inaccuracy of these first pulses is not a problem. It is very effective to be able to generate a high-precision pulse with a simple configuration as in the present embodiment.

In addition, since current mode logic capable of high speed operation is used, not only the high frequency but also the low power consumption can be achieved up to the limit of device performance of the circuit.

According to the pulse generation circuit of the third embodiment described above, a pulse can be generated with a high frequency accuracy with a simple circuit. Not only can the pulse width of the pulse to be output be freely set, but also various error factors caused by the process variation of the semiconductor integrated circuit constituting the circuit can be eliminated, thereby facilitating manufacture and lowering the manufacturing cost.

(4th embodiment)

4 is a circuit diagram showing a main part of a pulse generating circuit according to a fourth embodiment of the present invention.

In the second embodiment described above, the delay circuits 202, 203, ..., and the ring oscillation circuit 209 are separately provided, but in the present embodiment, an example of sharing them by switching them is described. Blocks given the same numerals as those in FIG. 2 are the same as those in the second embodiment, and description thereof will be omitted.

The pulse generator circuit is switched between the calibration mode and the pulse generation mode by the signal applied to the terminal 401. Given a signal specifying the configuration mode at terminal 401, switch 403 switches the input of delay circuit 202 to the output of a predetermined stage of the delay circuit to configure a predetermined number of ring oscillating circuits. At the same time, the division circuit 402 (not shown in the second embodiment), the phase comparison circuit 206, the charge pump 207, and the low pass filter 208 are activated to switch to form a phase locked loop.

Calibration is complete when the phase locked loop locks to a reference frequency applied to the reference frequency terminal 210. It goes without saying that in the calibration mode, the logic circuit for generating pulses is made inactive by a signal applied to the terminal 401.

When the command signal of the pulse generation mode is input to the terminal 401, the switch 403 switches to switch the input of the delay circuit 202 to the trigger terminal 201 side and waits for the signal of pulse generation. At the same time, the logic circuit for pulse generation is activated, and the phase locked loop is released. The output of the low pass filter 208 maintains the value when the phase locked loop was locked. The delay circuits 202, 203, ... correct the phase locked loop and are driven by the control voltage (voltage at the control terminal 211) when the phase locked loop is locked, so that the delay amount is the phase locked loop. Is equal to the fixed amount when is locked. This makes it possible to generate pulses of the correct pulse width.

(5th embodiment)

Fig. 5A is a circuit diagram showing the main part of the pulse generating circuit according to the fifth embodiment of the present invention, and Fig. 5B is a time chart showing the operation thereof.

In the above-described pulse generating circuits of the first to fourth embodiments, when a trigger signal is applied to the trigger terminal, the pulse generator stops by generating a pulse of a predetermined number of fingers determined by the number of stages of the delay circuit and the AND circuit. The larger the number of fingers, the larger the circuitry required. This embodiment is an example in which the circuit scale does not increase even when a pulse having a large number of fingers is generated.

In Fig. 5 (a), 503 is an NOR circuit, which starts the same operation as the inverter when the signal Ci applied to the trigger terminal 508 becomes false (L). If Ci is now L, as shown in Fig. 5B, the output NR1 is delayed by the delay time td of the NOR 503 to be H. The inverters 501 and 502 emit a signal delayed by the delay time of each inverter according to the change of the output NR1 of the output NOR 503, and constitute a ring oscillation circuit together with the NOR 503 to start oscillation. .

N1 and N2 in Fig. 5B show the outputs of the inverters 501 and 502, respectively. For simplicity, hereinafter, the delay times of the inverters 501 and 502 and the NOR 503 will be described as equal, and the oscillation period of the ring oscillation circuit is 6td, as can be seen from N1, N2 and NR1 in the figure.

NAND circuits 504, 505, and 506 output L when both NR1 and N1, N1 and N2, and N2 and NR1 are H, respectively. In Fig. 5B, ND1, ND2, and ND3 represent output signals of the NAND circuits 504, 505, and 506, respectively.

507 is a negative logic logic (NOR) circuit, and if any of the NAND circuits 504, 505, and 506 has L, H is output from the output terminal 509. In FIG. 5B, NR2 represents the output of the NOR circuit 507.

As can be seen from the figure, the output NR2 continuously generates pulses of period 2td while Ci is L. As shown in FIG. It can be seen that the width of the generated pulse is a conventional thin pulse.

The duration of pulse generation (number of fingers of the pulse) can be controlled by Ci, which is a thin pulse that cannot be generated in a conventional circuit without increasing the number of elements in the circuit. Generation is possible.

In the fifth embodiment, an example using a three-stage ring oscillation circuit has been described, but the number of stages of the ring oscillation circuit can take a stage other than three. In that case, it is necessary to increase the number of NAND circuits by the number of stages and to make the number of inputs of the NOR circuits equal to the number of NAND circuits. In this case, the number of elements in the circuit increases, but since the oscillation frequency of the ring oscillation circuit decreases with the number of stages, the current consumption of the circuit hardly changes.

In the pulse generating circuit of the fifth embodiment, as in the second to fourth embodiments, the ring oscillation circuit is compared with the phase locked loop including the oscillation circuit having the same characteristics, so that the accuracy of the oscillation period is increased. In addition, current mode logic circuits can be used to generate a shorter period of pulse trains.

Next, the pulse shape which generate | occur | produces and uses in this invention is demonstrated before demonstrating embodiment of this invention after 6th Embodiment.

6 shows the pulse shape to be generated by the present invention. The figure (a) is a waveform obtained by multiplying the pulse waveform shown to Fig.16 (a) by the sine wave carrier wave of period 2Pw (= 1 / f).

Similarly, (b) is a waveform obtained by multiplying the pulse waveform shown in FIG. 16 (a) by the square wave carrier wave of the period 2Pw (= 1 / f). Although the waveform side of the figure (b) is easy to implement | achieve by a binary digital circuit, it is convenient because the waveform side of the figure (a) has unnecessary side waves. However, although the waveform in (b) can be easily generated in a digital circuit, since the frequency is high, it is difficult to generate an angular waveform as shown in the drawing, and naturally, the waveform close to the waveform shown in the drawing (a) appears. Obtained.

In this specification, the case where the waveform of the following specification is generated as an example is demonstrated, but this invention is not limited only to this case.

Pulse interval: Tp = 5nsec

Carrier frequency: f = 8 GHz

Carrier pulse width: Pw = 62.6psec

Pulse Width: P _D = 50 Opsec

Number of pulses included in time P: 4 (P _D = 8 Pw)

EMBODIMENT OF THE INVENTION Hereinafter, the pulse generation circuit which concerns on embodiment of this invention is demonstrated, referring drawings.

(6th Embodiment)

Fig. 7 (a) is a circuit diagram showing the main part of the pulse generating circuit according to the first embodiment of the present invention, (b) is a diagram detailing the inside of an example of a delay circuit as a component thereof; 3 is a time chart for explaining the operation.

In Fig.7 (a), 701-709 are the delay circuits comprised by cascading nine inverters. The configuration inside each stage of the inverter is shown in FIG. 7 (b) but will be described later. The pulse D ₀ input to the terminal 731 is delayed by time td for each stage as shown in Figs. 8A to 8J, and the logic is reversed to propagate in the delay circuit and exit from each stage. It is In other words, if the signal applied to the input terminal 731 is positive logic, then k is an integer in the i-th stage.

XD _{2k -i} when i = 2k-1

D _2k when i = _2k

Is output. X represents the negation logic of the signal and transposes it to the signal name.

The N-channel MOS transistors 713 and 712 are turned on when the output XD _{1 of the} first stage and the output D ₂ of the second stage of the delay circuit are high, respectively, to bring the pulse output terminal 730 to the first potential level ( V1). Next, the P-channel MOS transistors 210 and 211 respectively have low output D ₂ and third output XD ₃ of the delay circuit (ie, negative logic of D ₂ and D ₃₎ . When both are high (the logical product is true), the conduction is conducted to connect the pulse output terminal 230 to the second potential level V2.

Similarly, the N-channel MOS transistors 716, 717, 720, 721, 724, and 725 are respectively high when the output of the 2k-1st stage (XD _{2k -1} ) and the output of the 2kth stage (D _2k ) of the delay circuit are high. i.e. the conductive when true logical product of XD _2k-1 and D _2k to connect the pulse output terminal 230 to a first potential level (V1).

Next, the P-channel MOS transistors 714, 715, 718, 719, 722, and 723 are respectively low when the output (D _2k ) and the output of the 2k + 1st stage (XD _{2k +1} ) of the delay circuit are low, respectively. when D _2k logical product of the negative XD XD _2k and _{2k +1} of the negative logic of D _{2k +1} true of conduction to connect the pulse output terminal 730 to a second potential level (V2).

By the above operation, a pulse waveform as shown in Fig. 8 (k) can be generated.

Here, the first and second potential levels can be used at the -side and + side power supply potentials VSS and VDD of the integrated circuit constituting the circuit, respectively, but may be set to any other potential.

The P-channel MOS transistor 727 and the N-channel MOS transistor 728 are MOS resistors. The first and second potentials V1 and V2 are divided to switch circuits of the MOS transistors 710 to 725. The potential of the output terminal 730 is set when none of the potentials V1 and V2 of 2 is connected. Usually, the symmetry of the constants of the N and P channel transistors is maintained, so that the potential is designed to be the intermediate value between V1 and V2.

FIG. 7B is a diagram showing the interior of the inverters 701 to 709 constituting the delay circuit. The P-channel MOS transistor 741 and the N-channel MOS transistor 742 constitute an inverter circuit, and the signal input to the terminal 744 is inverted and output from the terminal 745 with a delay time td.

The P-channel MOS transistor 240 and the N-channel MOS transistor 243 are respectively inserted in series with the source of the transistor constituting the inverter, respectively, + side power supply (VDD) terminal 746 and-side power supply (VSS) terminal. 749 is connected. By controlling the gate potential of these transistors, it is possible to control the power supply current flowing into the inverter.

This control makes it possible to control the operating speed of the inverter and control td. In order to generate a pulse having a desired frequency spectrum, the voltages at the terminals 747 and 748 may be controlled such that Pw = td. When the voltages applied to these terminals are measured from the VSS side, and each of Vpc and Vnc is set such that VDD-Vpc = Vnc, an output signal having good symmetry can be obtained.

In addition, any one of the transistors 740 and 743 can be omitted. Since the delay characteristic of the delay circuit illustrated here is influenced by the load, the output to the switch circuit can be connected via an appropriate buffer circuit.

By taking such a configuration as described above, most of the circuit can be designed as a digital binary circuit, and the configuration is simple. In addition, the circuit operates in a complementary manner, and either of the P or N-channel transistors is always in a non-conductive state when the circuit is stopped, resulting in extremely low power consumption.

In addition, since the output circuit is directly driven by the MOS transistors 710 to 725, not only the deformation is small but also a large amplitude large power signal can be taken out.

In addition, the axiom of boolean algebra may change the logical and logical sums depending on how the logical values are defined (whether the low potential is true or false), but these principles are the same. The concept would not need explanation.

(Seventh embodiment)

Fig. 9A shows a seventh embodiment of the present invention.

In Fig. 9A, 901 to 909 are delay circuits formed by cascading nine inverters. The configuration inside each stage of the inverter is the same as that shown in Fig. 7B, and the output of each stage is also the same as in the first embodiment.

That is, the pulse D ₀ input to the terminal 931 is delayed by time td for each stage as shown in Fig. 8 (a) (j), and the logic is reversed to propagate in the delay circuit and output from each stage. do. In other words, if the signal applied to the input terminal 431 is positive logic, k is an integer in the i-th stage.

i = _2k-1 XD 2k _-1 when

D _2k when i = _2k

Is output. X represents negative logic and transposes into a signal name.

The N-channel MOS transistor 911 conducts when the output XD _{1 of the} first stage and the output D ₂ of the second stage of the delay circuit are low by the NOR circuit 913 to close the pulse output terminal 930. 1 is connected to the potential level V1. Next, the P-channel MOS transistor 910 is energized when the output D _{2 of the} second stage and the output XD ₃ of the third stage of the delay circuit are high due to the action of the NAND circuit 912. 930 is connected to the second potential level V2.

Similarly, the N-channel MOS transistors 915, 919, and 923 have low outputs (XD _{2k- 1} ) and 2k -th outputs (D _2k ) of the delay circuit, respectively, that is, XD _{2k -1} and When the negative logical product of D _2k is true, it conducts and connects the pulse output terminal 930 to the first potential level V1.

Next, the output of the P-channel MOS transistor (914, 918, and 922) is a 2k-th stage of the respective delay circuits (D _2k) and 2k + output of the first stage (XD _{2k +1)} when high, that is, D _2k and XD _{2k +1} Conducts when the logical product of is true, and connects the pulse output terminal 430 to the second potential level V2.

By the operation described above, a pulse waveform as shown in Fig. 8 (l) can be generated.

In the sixth embodiment, the pulse is outputted by the falling of the signal applied to the terminal D _{0. In} the seventh embodiment, the pulse is outputted by the rising. These are the differences between whether D _{0 to} D ₉ are regarded as negative logic or positive logic.

According to the above configuration, compared with the first embodiment, the transistors 910, 911, 914, 915, 918, 919, 922, and 923 constituting the switch circuit directly output the first and second potential levels and pulse outputs. The terminal 930 is connected. In contrast, in the sixth embodiment, for example, the transistor 711 is connected to the second potential level via the transistor 710, which is a problem when the output impedance is to be lowered. In this embodiment, since the transistor is directly connected to V1 and V2, the design becomes easier when the output impedance of the signal is to be lowered.

In the sixth embodiment, for example, the transistors 711 and 712 or 710 and 717 are connected to the same signal D ₂ or XD ₃ . When the signal D ₂ changes from a high level to a low level, since the D ₂ potential is in the middle of the power supply and the transistors 710 and 713 are already conducting, they short-circuit V1 and V2, and the excessive current so-called short current is spiked. Flows into.

Similarly, when the signal XD ₃ changes, that is, from low level to high level, the XD ₃ potential is in the middle of the power supply and the transistors 211 and 216 are already conducting, which short-circuits V1 and V2 resulting in excessive current. This increases the current consumption of the circuit flowing in the spike shape.

In the seventh embodiment, since the gates of the P and N channel transistors are not driven with the same signal, it is possible to control them so that they do not become conductive at the same time, and it is possible to reduce the influence of the short current. To this end, the output of the NAND circuits 912, 916, 920, and 924 may be slowed down, the rise may be faster, and the output of the NOR circuits 913, 917, 921, 925 may be slowed, and the speed may be lowered.

In the NAND circuit, as shown in Fig. 9B, the P-channel transistors 941 and 942 are connected in parallel to the power supply VDD on the + side, and the N-channel transistors 943 and 944 are connected to the VSS on the negative side. It is connected in series and comprised. In addition, as shown in Fig. 9C, the NOR circuit is configured such that the N-channel transistors 948 and 947 are connected to the power supply VSS in parallel, and the P-channel transistors 945 and 946 are connected in series to the power supply VDD. do.

When the transistors are connected in series, the impedance is high, so the NAND circuit tends to have a slow fall and a rapid rise, while in a NOR circuit, a rapid fall and a rise tends to be slow. Therefore, the short current can be reduced by the connection similar to this embodiment. If the transistors in parallel in the NAND circuit or the NOR circuit are made larger and the transistors in series are designed smaller, the above characteristics are further emphasized and the effect is also increased.

(8th Embodiment)

Fig. 10 (a) schematically shows a pulse waveform obtained in the first and second embodiments. In the no-load state, a waveform like 1001 is output, but the waveform is deformed by the output load and becomes 1003 when the load is very heavy, such as 1002 at light load. In particular, when a pulse train of about 8 GHz is to be output in a 0.18 µ CMOS process, waveforms of 1001 and 1002 are not obtained and become 1003.

In the case of 1003, the output waveform 1001 is integrated at no load by the load capacity. Since the area on the + side of the waveform 1001 and the area on the − side are the same, the integrated waveform becomes a waveform inclined toward the − side as shown in the figure. This waveform is not a desired waveform, but a desired one as shown in FIG. 6.

In the eighth embodiment, a circuit capable of outputting a desired waveform without deformation even when driving such a heavy load is shown. For this purpose, as shown in the drawing (b), the pulses of the leading edge and the trailing edge of the output waveform may be set thin so that the integrated waveform is equalized to both sides of + −.

This operation principle will be described in more detail below with reference to FIG. 10 (b). In the same figure (b), the waveform shown in the same figure (a) is also drawn for comparison, and the same reference numerals designate the same waveforms. The description of these is duplicated, and thus will be omitted. 1006 is a waveform whose width is reduced in the front and rear edges of the above-described output waveform. When such a waveform drives a heavy capacitive load, it is integrated and a waveform equal to both + and-is obtained as in 1008. This becomes the target output pulse waveform.

A waveform obtained by reducing the front and rear edges such as the waveform 1006 can be realized by setting the delay amounts of the second stage and the final stage of the delay circuits of the first and second embodiments small.

Fortunately, there is only one transistor, or gate, connected to the final stage 709 or 909 of the delay circuit and is lighter in fanout load than the other output. Therefore, it is easy to reduce the delay amount of the final stage.

 Similarly, the load of the first stage inverter 701 or 901 is lightly loaded with a fanout of 1, but the delay amount of the inverter 702 or 902 must be reduced in order to narrow the pulse width. In this case, the inverters 701 and 901 are simple buffers, and the delay amount of this stage is not related to the output waveform. In order to reduce the delay amount, the transistors of the transistors 740 and 743 of the inverter cell of the delay circuit shown in Fig. 10C are made larger by comparison with other stages.

As shown in Fig. 10 (b), another method of thinly setting the pulse waveform at the leading edge of the output waveform is to insert a signal delay element in series with the nodes 732 and 932 in Fig. 7 or 9. It can also be realized. In FIG. 8, the signal of XD ₁ in (b) is accompanied by a delay in the first AND circuit due to the action of the delay element, that is, the signal in (b) is slightly shifted to the right in the same time chart. Because it is sent to.

In addition, another method of preventing the output pulse waveform from inclining to any one of + − as described above by the capacitive load will be described with reference to FIG. 10 (d). That is, in the same figure, the speed at which the output pulse 1001 charges and discharges the load capacitance at the front and rear edges of the output pulse may be slower than the other. In other words, the inclination of the discharge may be smaller in the leading edge 1004 than in the waveform 1003 when no countermeasure is taken. In the trailing edge 1005, the inclination of the charging may be reduced in comparison with the waveform 1003. To this end, the switching transistors conducting at these front and rear edges, 712, 713, 722, 723 of FIG. 7 (a) or 911, 922 of FIG. 9 (a), are set to be larger than the conduction impedance of other switching transistors, that is, these The size (channel width) of the transistor may be reduced.

In addition, as described above, the first stage inverters 701 and 901 of the delay circuits of the first and second embodiments perform only a function of the buffer. Therefore, this part can be omitted. In this case, the input signal D ₀ of the delay circuit is connected to the first AND circuit instead of the output XD _{1 at the} first stage of the delay circuit.

In the pulse generating circuit according to the above description, the generated pulse is only 3.5 cycles, which is slightly different from the pulse of the purpose shown in FIG. It is easy to add the remaining half cycle. That is, it is possible to realize by adding a delay circuit and a switch transistor connected to the first potential level. In FIG. 7, another delay circuit is provided behind the delay circuit 709 to produce a delay output D ₁₀ . Two N-channel switch transistors are inserted in series between the terminals 730 and 729 and the gates of the respective transistors are connected to XD ₉ and D ₁₀ . Alternatively, another delay circuit is placed behind the delay circuit 909 in FIG. 9 to form a delay output D ₁₀ . An N-channel switch transistor is inserted in series between the terminals 930 and 929 to drive the gate of the transistor at the NOR of XD ₉ and D ₁₀ .

In this way, the remaining half cycle is added as shown in FIG. 10 (e) 1010 or 1012. As described above, the waveform 1010 is made smaller in pulse width than the other to adjust the discharge time from the load capacitance to obtain a pulse waveform of the same purpose as in 1011. The waveform 1012 is the same as described above, that is, the conduction resistance of the switch transistor is increased to adjust the discharge time from the load capacitance to obtain a pulse waveform of the purpose as shown in 1013. The waveform thus obtained does not have a DC component. In addition, the DC component due to a slight unbalance of the output pulse due to the ON resistance of the switching transistor or the variation of the delay amount of the delay circuit is automatically adjusted from the request that the total amount of charges charged and discharged to the load capacity should be O in the steady state. Canceled.

As described above, according to the present invention, even a large capacitive load can be easily generated with a short pulse with less deformation by a simple circuit.

(Ninth embodiment)

The pulse generator circuit described above is very small in size, low in power consumption, and can obtain an ideal pulse signal for use in UWB communication, so that it does not cause unnecessary influence on the surroundings and is not easily disturbed from others. It is also very promising for application to short-range micropower communication.

For example, it includes a mechanism (coupling mechanism) for wirelessly transmitting and receiving signals between two or more housing bodies coupled to allow relative displacement with respect to posture or position, such as a material coupling or hinge. It is also suitable for application to a device.

FIG. 11 is a diagram illustrating the invention in which the pulse generating circuit described with reference to FIGS. 1 to 10 is applied to each other so that an electronic circuit is mounted on each of them to carry out a signal transmission between two housing bodies coupled by a mechanism unit by wireless communication. It is a block diagram which shows the structural example of the electronic device as embodiment.

In FIG. 11, the two housing bodies are configured as a transmitter block 1112, which is one side thereof, and a receiver block 1113, which is the same and the other side, and transmits data from the transmitter block 1112 to the receiver block 1113. do. In the transmitter block 1112, electromagnetic waves are radiated from the transmission antenna 1110 through the transmission circuit 1102 from the circuit element 1101 that generates or holds transmission information.

In this embodiment, a circuit section for supplying a transmission power modulated in correspondence with transmission information to the transmission antenna 1110 by applying the pulse generating circuit described with reference to FIGS. 1 to 10 is provided in the transmission circuit 1102. have.

Electromagnetic waves radiated from the transmitting antenna 1110 propagate through the air radio path 1108 in the air.

The receiving unit block 1113 is provided with a circuit element 1104 for receiving transmission information propagating through the radio wave path 1108 through the receiving antenna 1111 and the receiving unit 1106. In addition, between the transmitter block 1112 and the receiver block 1113, the interface circuit 1103 is provided in the transmitter block 1112, and the interface circuit 1105 is provided in the receiver block 1113, and both interface circuits 1103 are provided. And 1105, the transmission and reception of some signals or power are configured through a wired path 1107 connecting them.

It is easy to transmit a low-speed signal by this wired line, and can transmit a synchronization signal of a wireless communication unit. This eliminates the need for cumbersome procedures and circuits such as synchronization capture and tracking in the wireless communication unit, thereby simplifying the circuit. In addition, wireless communication can be performed while sending an encryption key for enhanced safety and arbitrarily changing the key.

The electromagnetic field radiated from the transmitting antenna 1110 is set not to exceed the upper limit prescribed by law. The emission level allowed as a station without a license is much lower than the EMI regulations, but since the communication distance is very close, it is possible to secure a sufficient quality communication path by properly setting the link budget. have.

Since large amounts of information requiring high-speed transmission, such as data including images, are not transmitted through signal lines but propagate space by radio, there is no need to use signal lines, and the accompanying connector or hinge structure (coupling mechanism) Various problems in mechanical or electrical, and also in manufacturing can be eliminated.

In the conventional transmission using signal lines, the charge and discharge of the stray capacitance increases with the increase of the speed, the power consumption increases, and the unnecessary radiated power emitted from the signal lines increases, and the countermeasures against the peripheral equipment are increased. There was a drawback to being difficult. In addition, since the logic level is specified in the transmission by the signal line, power consumption can be essentially reduced, and there is only a countermeasure such as shield strengthening to reduce unnecessary radiation.

On the other hand, according to the structure similar to this embodiment, since sufficient communication quality can be ensured at a very short distance inside the same system, the radiated power from the transmission antenna 1110 can be reduced to this value, The increase is inherently improved, and EMI countermeasures are facilitated. In addition, the power consumption associated with the termination for impedance matching of the communication line can be freed from the constraints such as the increase in power consumption, the arrangement of components, and the arrangement of lines.

In addition, in the configuration example of FIG. 11, for convenience, the data has been described as being transmitted only from the transmitter block 1112 to the receiver block 1113, but it is necessary to say that it can be configured to perform bidirectional communication between both blocks. There is no.

(10th embodiment)

FIG. 12 is a diagram illustrating an example in which the wireless communication described with reference to FIG. 11 is applied to a clamshell type mobile telephone. Fig. 12A is a perspective view showing a state when the clamshell type mobile phone is opened, and Fig. 12B is a perspective view showing a state when the clamshell type mobile phone is closed.

12 (a) and 12 (b), the operation button 1204 is arranged on the surface of the first housing body portion 1201, and a microphone 1205 is disposed at the lower end of the first housing body portion 1201. An external wireless communication antenna 1206 is mounted on the upper end of the first housing body part 1201. In addition, the display body 1208 is provided on the surface (surface shown in an open state) of the second housing body portion 1202, and a speaker 1209 is provided at the upper end of the second housing body portion 1202.

Moreover, the display body 1211 and the imaging element 1212 are provided in the back surface (outer surface in a closed state) of the 2nd housing body part 1202. As the display bodies 1208 and 1211 described above, for example, a liquid crystal display panel, an organic EL panel, a plasma display panel, or the like is applied. As the imaging element 1212, a CCD, a CMOS sensor, or the like is applied.

In the first housing body portion 1201 and the second housing body portion 1202, internal wireless communication antennas 1207 and 1210 that perform internal wireless communication between the first housing body portion 1201 and the second housing body portion 1202 are provided. Each is installed. As shown, the first housing body portion 1201 and the second housing body portion 1202 are connected via a hinge 1203 as a coupling mechanism portion, and the second housing body portion 1202 is rotated with the hinge 1203 as a point. In this way, the second housing body portion 1202 can be stacked on the first housing body portion 1201.

As described above, by closing the second housing body portion 1202 on the first housing body portion 1201, the operation button 1204 can be protected by the second housing body portion 1202, and the user can walk with the mobile phone. It is possible to prevent the operation button 1204 from being misoperated at the time. In addition, by opening the second housing body portion 1202 from the first housing body portion 1201, while operating the operation button 1204 while viewing the display body 1208, or while using the speaker 1209 and the microphone 1205. The imaging can be performed while making a call or operating the operation button 1204.

Moreover, by using the clamshell structure, the display body 1208 can be arrange | positioned on almost the whole surface of the 2nd housing body part 1202, and the size of the display body 1208 is not lost, as a portable telephone is not lost. By making it possible to enlarge, the visibility can be improved.

In the above-described configuration, in this mobile phone, the internal wireless communication antenna 1207 is provided in the first housing body part 1201 and the internal wireless communication antenna 1210 is provided in the second housing body part 1202, respectively. A data transmission between the first housing body portion 1201 and the second housing body portion 1202 is performed by internal wireless communication using these internal wireless communication antennas 1207 and 1210.

That is, in the mobile telephone of FIG. 12, the internal wireless communication antenna 1207 corresponds to the transmission antenna 1110 in the electronic device of FIG. 11, and the internal wireless communication antenna 1210 is used in the electronic device of FIG. 11. Corresponds to the receiving antenna 1111.

In the mobile telephone of FIG. 12, a transmitter block including a circuit portion corresponding to the transmitter 1102 of the electronic device of FIG. 11 on the antenna 1207 side (first housing body portion 1201 side) of the internal wireless communication. A circuit portion corresponding to 1112 is provided.

Similarly, a receiver block including a circuit portion corresponding to the receiver 1106 of the electronic device of FIG. 11 on the internal wireless communication antenna 1210 side (second housing body 1202 side) of the mobile telephone of FIG. 12. A circuit portion corresponding to 1113 is provided.

In addition, as described with respect to the apparatus of FIG. 11, the assumption of the transmitting side and the receiving side is for convenience, and the fact that the apparatus can be configured to perform bidirectional communication is also applicable to FIG. 12. Of course.

With the above-described configuration, for example, the internal wireless communication using the image data and the audio data taken into the first housing body 1201 through the external wireless communication antenna 1206 using the internal wireless communication antennas 1207 and 1210. By this, it can be sent to the 2nd housing body part 1202, an image can be displayed on the display body 1208, or an audio | voice can be output from the speaker 1209. FIG.

Moreover, the imaging data picked up by the imaging element 1212 is sent from the second housing body portion 1202 to the first housing body portion 1201 by internal wireless communication using the antennas 1207 and 1210 for internal wireless communication. It can be transmitted to the outside through the wireless communication antenna 1206. As described above, data transmission between the first housing body portion 1201 and the second housing body portion 1202 does not need to be carried out by wire, so that the multi-pin flexible wiring board passes through the hinge 1203. You don't have to.

As a result, the structure of the hinge 1203 is not complicated, and thus, the complexity of the installation process can be avoided, the cost reduction can be reduced, and the mobile phone can be made thinner and more reliable. The mobile phone can be made larger and more versatile without losing its portability as a mobile phone.

As described above, the use of wireless communication for signal transmission also has great effect even inside the apparatus. However, when pulse communication using the pulse generating circuit according to the present invention is used for internal communication, the interference and the resistance are excellent. Wireless communication with excellent coherence is possible. In other words, even in an electronic device such as a cellular phone, which has a communication circuit which is the original purpose of the device, the influence or interference of the wireless communication intended for the original purpose or the wireless communication intended for the original purpose of the device It can be minimized.

(Eleventh embodiment)

FIG. 13 is a diagram illustrating an example in which the wireless communication described with reference to FIG. 11 is applied to a rotary cellular phone. In FIG. 13, an operation button 1324 is disposed on the surface of the first housing body part 1321, and a microphone 1325 is provided at a lower end of the first housing body part 1321, and the first housing body part 1321 is provided. At the upper end of the external wireless communication antenna 1326 is installed. The display body 1328 is provided on the surface of the second housing body part 1322, and a speaker 1329 is provided on the upper end of the second housing body part 1322.

An internal wireless communication antenna 1327 is provided in the first housing body part 1321, and an internal wireless communication antenna 1330 is provided in the second housing body part 1322, respectively, and the first housing body part 1321 and the first housing body part 1321 are respectively provided. It is comprised so that internal radio | wireless communication may be performed between the 2 housing body parts 1322.

The first housing body portion 1321 and the second housing body portion 1322 are connected via a hinge 1323 as a coupling mechanism portion, and the second housing body portion 1322 is rotated horizontally with the hinge 1323 as a point. The second housing body portion 1322 can be disposed on the first housing body portion 1321 or the second housing body portion 1322 can be shifted from the first housing body portion 1321.

As described above, by arranging the second housing body portion 1322 on the first housing body portion 1321, the operation button 1324 can be protected by the second housing body portion 1322, and thus has a mobile phone. It is possible to prevent the operation button 1324 from being misoperated when walking. In addition, by operating the second housing body part 1322 horizontally to shift the second housing body part 1322 from the first housing body part 1321, the operation button 1324 is operated while the display body 1328 is viewed. The call can be made while using the speaker 1333 and the microphone 1325.

In the cellular phone of FIG. 13, the internal wireless communication antenna 1327 is provided in the first housing body part 1321, and the internal wireless communication antenna 1330 is provided in the second housing body part 1322, respectively. A data transmission is performed between the first housing body portion 1321 and the second housing body portion 1322 by internal wireless communication using the antennas 1327 and 1330.

That is, in the mobile phone of FIG. 13, the internal wireless communication antenna 1327 corresponds to the transmission antenna 1110 in the electronic device of FIG. 11, and the internal wireless communication antenna 1330 is used in the electronic device of FIG. 11. Corresponds to the receiving antenna 1111.

In the cellular phone of FIG. 13, a transmitter block including a circuit portion corresponding to the transmitter 1102 of the electronic device of FIG. 11 on the internal radio communication antenna 1327 side (first housing unit 1321 side). A circuit portion corresponding to 1112 is provided.

Similarly, a receiver block including a circuit portion corresponding to the receiver 1106 of the electronic device of FIG. 11 on the internal wireless communication antenna 1330 side (second housing body portion 1322 side) of the mobile telephone of FIG. 13. A circuit portion corresponding to 1113 is provided.

In addition, as described with respect to the apparatus of FIG. 11, the assumption of the transmitting side and the receiving side is for convenience, and it is a matter of course that the apparatus can be configured to perform bidirectional communication.

By the above-described configuration, for example, the internal wireless communication using the image data and the audio data taken into the first housing body part 1321 via the external wireless communication antenna 1326 using the internal wireless communication antennas 1313 and 1330. Can be sent to the second housing body portion 1322 to display an image on the display body 1328 or to output sound from the speaker 1333.

As described above, data transmission between the first housing body portion 1321 and the second housing body portion 1322 is not necessary to be wired, so that the multi-pinned flexible wiring board does not need to pass through the hinge 1323. In addition, the complexity of the hinge 1323 structure can be suppressed, and the complexity of the installation process can be avoided, the cost reduction can be reduced, and the mobile phone can be made thinner and more reliable. The mobile phone can be made larger and more versatile without losing portability as the mobile phone.

The wireless communication technique described above can also be applied to a video camera, a personal digital assistant (PDA), a notebook personal computer, and the like.

(12th Embodiment)

14 is a diagram illustrating an example in which the wireless communication described with reference to FIG. 11 is applied to a notebook personal computer. In Fig. 14, the notebook personal computer of this example is divided into a main body portion 1405 and a display portion 1409, and are integrated through a hinge 1407 as a coupling mechanism portion. The main body 1405 includes a main body substrate 1403 which is responsible for overall function control, a keyboard 1404 as an input device, and a liquid crystal controller 1408 which generates display data by control of an electronic circuit on the main body substrate 1403. Is installed.

In addition, the display unit 1409 is provided with a liquid crystal display 1406 as a display device. In addition, the main body 1405 and the display unit 1409 are provided with a transmitting antenna 1412 and a receiving antenna 1410 for wirelessly communicating with each other. The main body 1405 and the display portion 1409 are connected to each other by a line 1411 for wired communication and power supply. It is easy to transmit a low-speed signal over this wired line, and can transmit a synchronization signal of a wireless communication unit. As a result, in the wireless communication unit, cumbersome procedures and circuits such as synchronization capturing and tracking are unnecessary, and the circuit can be simplified. In addition, wireless communication can be performed while sending an encryption key for enhanced safety and arbitrarily changing the key.

In this notebook personal computer, in particular, the display data generated by the liquid crystal controller 1408 is converted from the transmitter 1412 to an electromagnetic wave (radio wave) by the transmission antenna 1412 to propagate the space. The electromagnetic signal transmitted from the transmitting antenna 1412 is received by the receiving antenna 1410, sent to the liquid crystal driver 1401 through the receiving unit 1402, and displayed on the liquid crystal display 1406.

In the above-described configuration, the transmit antenna 1412 corresponds to the transmit antenna 1110 in the electronic device of FIG. 11, and the receive antenna 1410 corresponds to the receive antenna 1111 in the electronic device of FIG. 11. .

In the notebook personal computer of FIG. 14, a transmitting unit including a circuit unit corresponding to the transmitting unit 1102 in the electronic device of FIG. 11 on the transmitting antenna 1400 side (note-type personal computer main body unit 1405 side). A circuit portion corresponding to the block 1112 is provided.

Similarly, a receiving section block 1113 includes a circuit section corresponding to the receiving section 1106 of the electronic device of FIG. 11 on the receiving antenna 1410 side (display section 1409 side) of the notebook personal computer of FIG. 14. The circuit part equivalent to) is provided.

In addition, as described with respect to the apparatus of FIG. 11, the assumption of the transmitting side and the receiving side is for convenience, and it is a matter of course that the apparatus can be configured to perform bidirectional communication.

In the above-described notebook personal computer, the information to be displayed on the liquid crystal display 1406 as a display device as the display device is transmitted between the main body portion 1405 and the display portion 1409 through the hinge 1407. The number of signal lines to be reduced can be reduced, the complexity of the structure can be suppressed, the complexity of the mounting process can be avoided, and the reliability can be improved while suppressing the cost increase.

As mentioned above, although embodiment as a notebook type personal computer was described, of course, the same technical idea can be applied also to what is called a mobile type computer smaller than a notebook type | mold, a PDA, and other portable information terminal apparatus which were described.

(13th Embodiment)

In the embodiment described with reference to FIGS. 11 to 14, the signal generation between the two housing bodies, in which an electronic circuit is mounted and coupled by a mechanism unit, is applied to each of the pulse generating circuits described with reference to FIGS. 1 to 10. It was to take a configuration to perform the wireless communication.

However, the technical idea of this invention is not limited to the aspect which performs the communication of the signal between these divided | divided housing bodies by wireless communication.

That is, in the same housing body, a transmitting circuit portion corresponding to the transmitting portion block 1112 of FIG. 11 and a receiving circuit portion corresponding to the receiving portion block are provided, and are shown between FIGS. 1 to 10 between these transmitting and receiving circuit portions. It can take the form to perform communication by applying the pulse generating circuit described with reference to. Next, such an embodiment will be illustrated, and the technical idea of this invention is further demonstrated.

 FIG. 15 is a view showing the configuration of a liquid crystal projector which is one embodiment of an electronic device according to the present invention. FIG. 15 (a) is a view showing the main part of the liquid crystal projector, and FIG. 15 (b) is a view of FIG. 15 (a). Fig. 3 shows the details of one light valve in the liquid crystal projector.

In Fig. 15A, the projector occupies most of the housing body 1510 by the optical system. That is, the light (white light) emitted from the light source 1501 is decomposed into three primary colors by the optical system 1502 (inside the broken line). Here, the optical system 1502 is mainly composed of a half mirror HM, an optical filter, and a lens LZ. Each light is light modulated by the light valve 1505, the light valve 1506, and the light valve 1507 by the liquid crystal, and then synthesized by the optical system 1503 composed of a prism, and by the optical system 1504. The picture is enlarged.

Circuits for controlling the light valve 1505, the light valve 1506, and the light valve 1507 are mounted on the substrates 1508 and 1509. The modulator 1512 modulates the display data signal for light valve control and radiates from the transmitting antenna 1511 as electromagnetic waves.

In Fig. 15B, the liquid crystal driver 1522 (usually composed of a plurality of semiconductor integrated circuits) by a semiconductor integrated circuit driving the optical shutter 1521 by the transmissive liquid crystal is transmitted in Fig. 15A. The display data signal transmitted from the antenna 1511 is received by the receiving antenna 1523, and the optical shutter 1521 is driven by the demodulated signal.

On the other hand, in the projector of this example, the electric power for driving the optical shutter 1521 and the liquid crystal driver 1522 is configured to be received via the connector 1524.

The display data signal by the electromagnetic waves transmitted by being transmitted from the transmission antenna 1511 can be divided into these multiplexed signals so that they can be received by each of them. Specific regular signal circuit blocks (modules) are designated by a method of determining and addressing slots.

By taking this addressing method, the electromagnetic wave signal transmitted from the transmitting antenna 1511 is correctly transmitted to the designated light valve among the three light valves. Addressing may be performed for each light valve, and as shown in Fig. 15B, a plurality of liquid crystal drivers may be mounted in one light valve and addressed to each of them.

As described above, as easily understood from the embodiment as the liquid crystal projector described with reference to FIGS. 15A and 15B, the electronic device of the present embodiment includes an electromagnetic wave conversion unit for converting a transmission signal into an electromagnetic signal; Transmitting circuit section having a transmitting section for wirelessly transmitting electromagnetic signals (in the apparatus of FIG. 15, a modulator 1512 and a transmitting antenna (modulated display data signal for light valve control and supplied to the transmitting antenna 1511 as electromagnetic waves) Receiving circuit section (corresponding to the transmitting section block 1112 of FIG. 11), a receiving section for receiving the electromagnetic wave signal, and an electromagnetic wave restoring section for restoring the received electromagnetic wave signal to the transmission signal. Is a circuit unit for demodulating the signals received by the receiving antenna 1523 and the receiving antenna 1523 to obtain a signal for driving the optical shutter 1521. That corresponds to the block), it can be said that the configuration is accommodated in the same housing body.

The above-described technique further includes, at least, a pair of radio units for wirelessly transmitting and receiving signals among a plurality of circuit blocks or circuit boards mounted in the same housing body. It is clear that the radio unit is an electronic device configured by applying any one of the above-described pulse generation circuits.

In the above-described configuration, the transmitting circuit portion and the receiving circuit portion may be each modularized as a circuit board or a circuit block.

In the electronic device having the above-described configuration, since the transmission and reception of signals can be made wireless by electromagnetic waves, and the signals are propagated through the space, there is no need for wiring using a flexible board or a connector. Concerns about deterioration of reliability are eliminated.

In addition, the problem of an increase in power consumption due to the termination for impedance matching or the increase in the data transmission speed can be avoided. In addition, restrictions on the arrangement of the wiring and the arrangement of components can be eliminated, and the design and usability of the electronic device can be improved.

In addition, since the electromagnetic waves used for signal transmission are conducted at a very short distance from the same housing body, it is only necessary to secure communication within this distance, and the intensity of the radiated electromagnetic waves can be lowered to the limit, thereby improving the EMI characteristics inherently. Measures become easy.

In particular, in the case of the liquid crystal projector illustrated with reference to FIG. 15, in the conventional liquid crystal projector, the optical system occupies most of the volume of the housing body, and it is necessary to wire the optical path and to arrange components away from the optical path. Furthermore, since the heat generated from the light source enters the housing body, the heat countermeasure of the wiring was also required. By carrying out the present invention, since the signal transmission is spatially transmitted by electromagnetic waves, such a conventional problem is remarkably alleviated.

The present invention is particularly effective when used for UWB communication using short pulses.

As described above, according to the present invention, the pulse of the high frequency band can be easily generated, and the configuration is simple and the power consumption is low.

Claims (24)

When the plurality of delay elements are cascaded so as to form a predetermined loop, and a predetermined input pulse is supplied to the start end of the cascade connection, the nodule portion between the plurality of delay elements. ) And an effective frequency multiplication process by a logic circuit to a signal appearing in a plurality of predetermined portions of each of the termination portions of the slave connection by the logic circuit. A pulse generating circuit characterized by obtaining an output pulse having a high frequency. A plurality of first logic circuits connected to a predetermined stage dependent connection, a plurality of first logic circuits connected to an output of the delay circuit and generating pulses of a time width corresponding to a delay amount per stage of the delay circuit; And a second logic circuit for obtaining a logical sum of outputs of the plurality of first logic circuits. A delay circuit formed by cascade-dependent connection of a buffer circuit capable of electrically controlling a delay amount, and a plurality of agents connected to an output of the delay circuit and generating pulses of a time width corresponding to a delay amount per stage of the delay circuit. A first logic circuit, a second logic circuit for obtaining a logical sum of the outputs of the plurality of first logic circuits, a comparison circuit for comparing the delay amount of the delay circuit and the reference delay amount, and the output of the comparison circuit. And a circuit for controlling the delay amount of the buffer circuit. A plurality of delay circuits formed by cascade-connecting a first buffer circuit in which a delay amount is electrically controllable, and a pulse having a time width corresponding to a delay amount per stage of the delay circuit connected to an output of the delay circuit; An oscillation circuit comprising a first logic circuit of a second circuit, a second logic circuit for obtaining a logical sum of outputs of the plurality of first logic circuits, a second buffer circuit having electrical characteristics similar to those of the first buffer circuit, and And a phase lock loop for feedback-controlling the delay amount of the second buffer circuit such that the oscillation frequency of the oscillation circuit is phase-locked to the reference frequency by comparing the output of the oscillation circuit with a reference frequency. And a delay amount of the one buffer circuit is controlled in the same manner as the feedback control of the phase locked loop. A delay circuit formed by cascade-dependent connection of a buffer circuit capable of electrically controlling a delay amount, and a plurality of agents connected to an output of the delay circuit and generating pulses of a time width corresponding to a delay amount per stage of the delay circuit. A ring oscillation circuit is formed by connecting a first logic circuit, a second logic circuit for obtaining a logic sum of the outputs of the plurality of first logic circuits, an output of a buffer circuit at a predetermined stage of the delay circuit, and an input of the delay circuit. A switch means, a phase locked loop including the ring oscillation circuit, and means for holding a signal when the phase locked loop is locked to a reference frequency as a control signal of the delay amount of the buffer circuit, The timing lock loop is released when the timing of the operation of the first and second logic circuits is released, and the delay amount of the buffer circuit is lower than the phase lock loop. A pulse generating circuit, characterized in that in a controlled time so as to be equal to the delay amount at the time. An oscillation circuit formed by connecting a plurality of delay circuits and one gate circuit in a loop shape, and a plurality of first pulses that generate pulses of a time width corresponding to the delay amount of the respective stages from the output of each stage of the oscillation circuit; And a logic circuit and a second logic circuit for obtaining a logic sum of the outputs of the plurality of first logic circuits. The method according to claim 2 or 6, And the delay circuit is configured such that the delay amount can be controlled so that the delay amount can be controlled to be a predetermined value. An oscillation circuit formed by connecting a plurality of delay-controlled buffer circuits and gate circuits in a loop shape, and a plurality of pulses having a time width corresponding to the delay amount of each stage from the output of each stage of the oscillation circuit; A first logic circuit, a second logic circuit for obtaining a logical sum of the outputs of the plurality of first logic circuits, a comparison circuit for comparing the delay amounts of the respective stages and the reference delay amount, and the output of the comparison circuit. And a circuit for controlling the delay amount of the buffer circuit. An oscillation circuit formed by connecting a plurality of first buffer circuits and gate circuits which can be electrically controlled in a loop in a loop shape, and pulses having a time width corresponding to the delay amounts of the respective stages from the outputs of the respective stages of the oscillating circuit. An oscillation circuit comprising a plurality of first logic circuits, a second logic circuit for obtaining a logical sum of outputs of the plurality of first logic circuits, and a second buffer circuit having electrical characteristics similar to those of the first buffer circuit; And a phase lock loop for feedback-controlling the delay amount of the second buffer circuit such that the oscillation frequency of the oscillation circuit is phase-locked to the reference frequency by comparing the oscillation circuit output with a reference frequency. The delay amount of the first buffer circuit is controlled in the same manner as the feedback control of the phase locked loop. Generating circuit. The method according to any one of claims 3 to 5, or 8 to 9, The controllable buffer circuit includes a CMOS inverter and means for controlling a current flowing into the CMOS inverter. The method according to any one of claims 3 to 5, The controllable buffer circuit is a buffer circuit having a CMOS current mode logic circuit, and the delay amount is varied by controlling the inflow current of the buffer circuit. The method according to any one of claims 2 to 6, or 8 to 9, And the first and second logic circuits comprise CMOS current mode logic circuits. The delay circuit of the cascaded N + 1 stage (N is a positive integer), the output D _i of the _i stage of the delay circuit (i is an even number of 1≤i≤N) and the i-1th stage of the delay circuit. the output of the negative logic XD _{i -1} of the first logical product for obtaining the logical product circuit and a, i + 1, D _{i +1} of the output of the second stage of the delay i of the output D _i of the second stage negative logic of the circuit XD _i and the delay circuit A second AND circuit that obtains the AND, and a first potential level when the first AND circuit output is true, and a second potential level when the second AND circuit output is true; And a switching means connected to the level. The method according to claim 13, And the delay circuit is controlled so that the delay amount can be controlled so that the delay amount becomes a predetermined value. The method according to any one of claims 13 to 14, The delay circuit is constituted by a MOS inverter in the N + 1 stage and a means for controlling a power supply current flowing into the MOS inverter, and is controlled so that the corresponding delay amount of the delay circuit is a predetermined value by controlling the power supply current. Pulse generating circuit. The method according to any one of claims 13 to 14, And said first or second AND circuit has means for controlling the transition time of the output signal not to overlap. The method according to any one of claims 13 to 14, An AND circuit which obtains the logical product of the output D ₂ of the second stage of the delay circuit of the first AND circuit and the output of the negative logic XD ₁ of the output of the first stage of the delay circuit; and the delay of the second AND circuit N of the output of the second stage D _N negative logic XD _N and the logical product of a D _{N +1} of the N + 1-th stage output of the delay circuit for obtaining the logical product circuit is set to be short, compared to its output is true, the time is different that of the circuit And a means for generating the pulse generating circuit. The method according to any one of claims 13 to 14, An AND circuit which obtains the logical product of the output D ₂ of the second stage of the delay circuit of the first AND circuit and the output of the negative logic XD ₁ of the output of the first stage of the delay circuit; and the delay of the second AND circuit The switch means controlled by an AND circuit which obtains the logical product _{X N} of the output D _N of the N-th stage of the circuit and D _{N + 1} of the output of the N + 1-th stage of the delay circuit has its conduction impedance. The pulse generating circuit is set larger than other switch means. The method according to any one of claims 13 to 14, A pulse generating circuit, wherein the first stage of the delay circuit is omitted and an input signal to the delay circuit is connected instead of the first stage output signal. The housing body corresponding to a radio part for wirelessly transmitting and receiving a signal between a plurality of housing bodies in which electronic circuits are mounted to each other so as to allow relative displacement with respect to posture and position. The said wireless part is comprised by applying the pulse generating circuit in any one of Claims 1-6, 8-9, or 13-14, The electronic device characterized by the above-mentioned. Receiving a signal between the first housing body and the second housing body, each of which is coupled by a coupling mechanism to allow relative displacement with respect to posture or position, and in which an electronic circuit is mounted, and between the first housing body and the second housing body. Each wireless part provided in each of the said 1st housing body and the 2nd housing body in order to perform | move wirelessly is provided, Moreover, the said said wireless part is a claim 1-6, 8-9, or 13-Claims A mobile telephone, comprising the pulse generating circuit according to any one of 14. Receiving a signal between the first housing body and the second housing body, each of which is coupled by a coupling mechanism to allow relative displacement with respect to posture or position, and in which an electronic circuit is mounted, and between the first housing body and the second housing body. Each wireless part provided in each of the said 1st housing body and the 2nd housing body in order to perform | move wirelessly is provided, Moreover, the said said wireless part is a claim 1-6, 8-9, or 13-Claims A personal computer, comprising the pulse generating circuit according to any one of 14. Claims 1 to 6 further comprising at least one pair of radio units for transmitting and receiving signals by radio between a plurality of circuit blocks or circuit boards mounted in the same housing body. The pulse generating circuit of any one of Claims 8-9, or 13-14 is applied and comprised, The electronic device characterized by the above-mentioned. An information transmission method for wirelessly transmitting and receiving signals between a plurality of housing bodies in which electronic circuits are mounted to each other so as to allow relative displacements in relation to postures and positions. And the pulse generating circuit according to any one of claims 1 to 6, 8 to 9 or 13 to 14.

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