KR100685324B1 - Random access system and control device of NAND flash memory using dual port DRAM - Google Patents

Abstract

The present invention relates to a NAND flash memory random access system using dual-port DRAM, comprising: a NAND flash memory in which data is accessed in block units, a dual-port DRAM having first and second ports and a first port connected to a host; It is connected between the NAND flash memory and the dual port DRAM, and operates according to a control signal of the host to read a page unit data from the NAND flash memory to the dual port DRAM when the read control signal is received from the host and from the host And a controller configured to receive data written from the dual port DRAM and write data to the NAND flash memory in units of pages when a write control signal is received.

According to the present invention as described above, a controller for transferring data between the dual port DRAM and the NAND flash memory is interposed so that the NAND flash memory can be randomly accessed from the host point of view, thereby dramatically improving data read and write performance of the NAND flash memory. It can be effected.

Description

A System For Accessing NAND Flash Memory At Random Using Dual-Port DRAM And A Controller Thereof}

1 is a block diagram illustrating a connection relationship between a conventional CPU and a memory.

FIG. 2 is a block diagram illustrating a system for random access of a NAND flash memory using dual-port DRAM according to the present invention.

3 is a detailed block diagram illustrating an internal configuration of the controller of FIG. 2.

4 illustrates an example in which the controller and the NAND flash memory are implemented in one chip according to the present invention.

5 illustrates an example in which the dual port DRAM and the controller are implemented in one chip according to the present invention.

<Description of main drawing code>

10: CPU (MODEM) 20: Dual Port DRAM

30: controller 31: control logic

32: host interface 33: memory interface

34: NAND interface 35: Error Correction Code (ECC)

36: buffer 37: internal bus

40: NAND flash memory

The present invention relates to a control device for randomly accessing a NAND flash memory, which is a mass storage medium, and more particularly, interposed between a dual port DRAM and a NAND flash memory to control a random access of a NAND flash memory from a host's point of view. It relates to a system and a control device.

In general, flash memory is a nonvolatile and writable memory that stores once-recorded contents such as ROM (Read Only Memory (ROM)) even when power is not supplied, and cells are paralleled between bit lines and ground lines depending on the manufacturing method. It can be divided into a NAND flash memory having a structure arranged in series with the NOR flash memory having a structure arranged in.

NOR flash memory reads or writes random addresses regardless of the cell order (Random Access), which requires a bit line contact electrode for each cell or byte-accessible device. There is this.

In contrast, a NAND flash memory is a block device in which a block is accessed based on a basic unit by first selecting the block and then reading each cell connected in series.

In NAND flash memory, a block represents a unit that can be erased in one erase operation, and a page represents a data size that can be read or written in a read / write operation.

Since NAND flash memory has the advantages of faster writing speed, relatively cheaper price, and easier capacity storage than NOR flash memory, NAND flash memory is widely used for storing large data. There is a disadvantage that cannot be accessed randomly.

FIG. 1 is a block diagram showing a connection relationship between a conventional general host 10 (CPU or modem, hereinafter referred to as CPU) and a memory.

Referring to FIG. 1, the NAND flash memory 150 is connected to the CPU 10 through the NAND controller 130 for accessing block-by-block data, and the main memory DRAM 160 is connected through the memory controller 140. It is connected to the CPU 10 and data is randomly accessed.

The NAND controller 130 is provided with a buffer for storing a small amount of data therein, and temporarily stores data in a page unit read from the NAND flash memory 150, and then stores the data in the DRAM 160 through the memory controller 140. The CPU 10 may access the data stored in the DRAM 160.

Since the conventional data access method of the NAND flash memory 150 is not able to access randomly, it takes a considerable time to read and write data to the NAND flash memory 150, thereby degrading data reading and writing performance. have.

The present invention has been made to solve the above problems, an object of the present invention is to intervene a controller for transferring data between the dual port DRAM and the NAND flash memory to allow the NAND flash memory to randomly access from the host point of view NAND This is to significantly improve the data read and write performance of the flash memory.

According to an aspect of the present invention for achieving the above object, a NAND flash memory to which data is accessed in units of blocks, a dual port DRAM having a first and a second port and the first port is connected to a host and the NAND It is connected between a flash memory and a dual port DRAM, and operates according to a control signal of a host to read page data from the NAND flash memory to the dual port DRAM when the read control signal is received from the host, and transmits the data to the dual port DRAM and write control from the host. The NAND flash memory random access system using the dual port DRAM is provided, comprising a controller that receives data written from the dual port DRAM and writes the data to the NAND flash memory in units of pages when a signal is received.

The controller may include a host interface connected to a control port of the host to receive a control signal from the host, a memory interface connected to the dual port DRAM to interface data transmission and reception between the dual port DRAM and a controller, and the NAND flash memory. A NAND interface connected to an NAND interface for interfacing data transmission and reception between the flash memory and the controller, a buffer for temporarily storing data in units of pages received from the NAND flash memory, and connected through each interface and the buffer and an internal bus and received from the host. And a control logic unit for controlling the operation of each of the interfaces and the buffer based on the control signals.

In addition, the NAND flash memory and the controller or the dual port DRAM and the controller may be implemented on one semiconductor chip.

According to another aspect of the present invention for achieving the above object, it is interposed between dual-port DRAM (Dual-Port DRAM) and NAND flash memory (NAND Flash Memory) to control the host to randomly access the NAND flash memory A control device comprising: a host interface connected to a control port of a host to receive a control signal from the host, a memory interface connected to the dual port DRAM to interface data transmission and reception between the dual port DRAM and a controller, and the NAND flash memory A NAND interface connected to an NAND interface for interfacing data transmission and reception between the flash memory and the controller, a buffer for temporarily storing data in units of pages received from the NAND flash memory, and connected through each interface and the buffer and an internal bus and received from the host. To the control signal Provided is a NAND flash memory random access control apparatus using dual-port DRAM, the control logic unit for controlling the operation of each of the interfaces and the buffer based on the.

Here, the control device may be implemented on the same semiconductor chip as the NAND flash memory or the dual port DRAM.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 2 is a block diagram illustrating a system for random access of a NAND flash memory using dual-port DRAM according to the present invention.

As shown in FIG. 2, a system for random access of a NAND flash memory using dual-port DRAM according to the present invention is a dual main memory for the operation of the CPU 10. The dual port DRAM 20 having a port is used, and the controller 30 is connected between the dual port DRAM 20 and the NAND flash memory 40.

In detail, the dual port DRAM 20 has first and second ports, the first port is connected to the CPU 10 via the DRAM interface, and the second port is connected to the controller 30 via the DRAM interface. . The dual port DRAM 20 is a type of DRAM having the two input / output ports described above. One of the two input / output ports is accessible to, for example, a processor in its own board, and the other port. For example, it is a memory having a structure that allows access from another board through a bus.

As described above, the controller 30 is connected to the dual port DRAM 20 through the DRAM interface, the other end is connected to the NAND flash memory 40 through the NAND interface, and is also connected to the CPU 10 to NAND flash. The control signal for writing and reading the data of the memory 40 is received.

When the received control signal is a read control signal, the controller 30 reads data in units of pages from the NAND flash memory 40, transmits the data to the dual port DRAM 20, and receives the received control signal. If the received control signal is a write control signal, the CPU 10 receives the recorded data from the dual port DRAM 20 and writes the data to the NAND flash memory 40 in units of pages so that the CPU 10 of the NAND flash memory 40 can be used. It performs a function to make data randomly accessible from the dual port DRAM 20.

4 is a detailed block diagram illustrating an internal configuration of the controller of FIG. 3.

As shown in FIG. 4, the controller 30 according to the present invention includes a control logic unit 31, a host interface 32, a memory interface 33, a NAND interface 34, an ECC / EDC 35, and a buffer. 36, each of which is communicated via an internal bus 37.

The control logic unit 31 is connected to each of the following interfaces 32, 33, 34 and buffer 36 via the internal bus 37 and based on the control signals received from the CPU 10. , 33, 34, and controls the operation of the buffer 36. The control logic unit 31 stores an instruction set for performing an operation corresponding to an instruction included in a control signal received from the CPU 10.

The host interface 32 is connected to the control port of the CPU 10 to provide an interface for receiving control signals from the CPU 10.

The memory interface 33 is connected to the second port of the dual port DRAM 20 and implemented as a DRAM interface to interface data transmission and reception between the dual port DRAM 20 and the controller 33.

The NAND interface 34 is connected to the NAND flash memory 40 and implemented as a NAND interface to interface data transmission and reception between the NAND flash memory 40 and the controller 30.

An ECC / EDC (Error Correction Code / Error Detection Code: 35) performs a function for detecting and correcting an error in data transmitted and received between the dual port DRAM 20 and the NAND flash memory 40.

The buffer 36 is for temporarily storing page data received from the NAND flash memory.

The reading and writing operations of the NAND flash memory 40 under the control of the control logic unit 31 will be described below.

Reading  action

First, when a read control signal transmitted from the CPU 10 is received through the host interface 32, the control logic unit 31 interprets a command included in the control signal and uses the NAND flash memory (NAND flash memory) through the NAND interface 34. 40, data in units of pages is read and temporarily stored in the buffer 36, and then transferred to the dual port DRAM 20 through the memory interface 33.

Data transmitted to the dual port DRAM 20 is transmitted to the CPU 10 through the DRAM interface, so that the CPU 10 can randomly read the desired data from the dual port DRAM 20 with only one control command. Therefore, the data read time is significantly reduced.

Recording action

First, the CPU 10 stores data to be written to the NAND flash memory 40 in the dual port DRAM 20 and transmits a write control signal to the controller 30.

When the write control signal transmitted from the CPU 10 is received through the host interface 32, the control logic unit 31 interprets the command included in the control signal and determines that the write control signal is the data write control signal. The data to be written from the dual port DRAM 20 is temporarily stored in the buffer 36 and then written to the NAND flash memory 40 through the NAND interface 34 in units of pages.

4 illustrates an example in which the controller and the NAND flash memory are implemented in one chip, and FIG. 5 illustrates an example in which the dual port DRAM and the controller are implemented in one chip in the present invention.

As shown in FIGS. 4 and 5, the three components required for the present invention, the dual port DRAM 20, the controller 30, and the NAND flash memory 40 may be manufactured as separate units, respectively. As shown in FIG. 4, the controller 30 and the NAND flash memory 40 may be implemented on one semiconductor chip. As illustrated in FIG. 5, the dual port DRAM 20 and the controller 30 may be implemented on one semiconductor chip. It may be.

That is, in the present invention, the dual port DRAM 20, the controller 30, and the NAND flash memory 40 are coupled to each other so that the host can randomly access the NAND flash memory 40. One single chip, two chips, three individual chips, etc. are possible in various ways, and all possible chip implementation methods belong to the technical idea of the present invention.

According to the present invention as described above, a controller for transferring data between the dual port DRAM and the NAND flash memory is interposed so that the NAND flash memory can be randomly accessed from the host point of view, thereby dramatically improving data read and write performance of the NAND flash memory. It can be effected.

Although the present invention has been described in connection with the above-mentioned preferred embodiments, it is possible to make various modifications or variations without departing from the spirit and scope of the invention. Accordingly, the appended claims will cover such modifications and variations as fall within the spirit of the invention.

Claims (5)

In a random access system of NAND flash memory using dual-port DRAM, A NAND flash memory in which data is accessed in units of blocks; A dual port DRAM having first and second ports and wherein the first port is connected to a host; And It is connected between the NAND flash memory and the dual port DRAM, and operates according to a control signal of the host to read a page unit data from the NAND flash memory to the dual port DRAM when the read control signal is received from the host and from the host And a controller configured to receive data written from the dual port DRAM and write data to the NAND flash memory in units of pages when a write control signal is received. The method of claim 1, The controller A host interface connected to a control port of the host to receive a control signal from the host; A memory interface connected to the dual port DRAM to interface data transmission and reception between the dual port DRAM and a controller; A NAND interface connected to the NAND flash memory to interface data transmission and reception between the flash memory and a controller; A buffer for temporarily storing data in units of pages received from the NAND flash memory; And Any of the NAND flash memory using dual-port DRAM characterized in that it comprises a control logic unit connected to each of the interface and buffer via an internal bus and controls the operation of each interface and buffer based on a control signal received from the host. Access system. The method of claim 1, The NAND flash memory random access system using dual port DRAM, characterized in that the NAND flash memory and the controller or the dual port DRAM and the controller is implemented on a single semiconductor chip. A control device interposed between dual-port DRAM and NAND flash memory to control a host to randomly access the NAND flash memory. A host interface connected to a control port of a host to receive a control signal from the host; A memory interface connected to the dual port DRAM to interface data transmission and reception between the dual port DRAM and a controller; A NAND interface connected to the NAND flash memory to interface data transmission and reception between the flash memory and a controller; A buffer for temporarily storing data in units of pages received from the NAND flash memory; And Any of the NAND flash memory using dual-port DRAM characterized in that it comprises a control logic unit connected to each of the interface and buffer via an internal bus and controls the operation of each interface and buffer based on a control signal received from the host. Access control system. The method of claim 4, wherein And each of the above components is implemented on the same semiconductor chip as the NAND flash memory or the dual port DRAM.

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