KR100673129B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, 1) sequentially stacking a bit line barrier metal, a bit line and a hard mask on the semiconductor substrate; 2) forming a first photoresist pattern on the hard mask, and then forming a hard mask pattern using the first photoresist pattern as a mask; 3) forming a second photoresist layer pattern in which the buried portion and the opening are alternately present on the hard mask pattern; 4) etching the lower stacked structure using the second photoresist pattern as a mask; 5) removing the second photoresist pattern and filling the interlayer insulating layer between the hard mask patterns; 6) forming a bit line by etching the lower layer structure using the hard mask pattern as a mask; And 7) forming a planarized interlayer insulating film over the entire surface after forming the spacers on the sidewalls of the bit lines. The method of the present invention has the advantage that it is possible to solve the problem of collapse of the pattern due to the high aspect ratio in forming the bit line without large changes in the conventional process.

Description

Method of manufacturing a semiconductor device {Method of Fabricating Semiconductor Device}

1A to 1F are cross-sectional views illustrating a conventional semiconductor device manufacturing process.

2A to 2F are cross-sectional views illustrating a process of manufacturing a semiconductor device of the present invention.

<Description of the symbols for the main parts of the drawings>

11,110; Active area, 12,120; Field Oxide,

13,130; Interlayer insulating film, 14,140; Landing plug pulley,

15,150; Interlayer insulating film, 16,160; Bitline barrier metal,

17,170; Bitline, 18,180; Hard Mask,

19,190; A first photosensitive film pattern, 200; Hardmask Pattern,

210; Second photosensitive film pattern 22,220; Spacer

23,230; Interlayer insulation film

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of preventing the collapse of the bit line by the aspect ratio increases with the decrease of the bit line line width during the bit line mask process. It is about.

A conventional bit line process is illustrated in FIGS. 1A-1F.

Referring to FIG. 1A, after forming the field oxide film 12 in the active region 11 of the semiconductor substrate, a gate (not shown) is formed.

Referring to FIG. 1B, the space between the gates is filled with the interlayer insulating film 13, the landing plug poly 14 is deposited, and then planarized by a chemical mechanical polishing (CMP) process.

Referring to FIG. 1C, an interlayer insulating layer 15 is deposited to prevent short between the bit line and the storage electrode contact SNC.

Referring to FIG. 1D, the bit line barrier metal 16, the bit line 17, and the hard mask 18 are sequentially stacked on the entire surface.

Referring to FIG. 1E, after the photoresist pattern 19 is formed on the hard mask 18, the lower bit line stacked structure is etched using the photoresist pattern 19 as an etch stop layer.

Referring to FIG. 1F, the spacers 22 are formed on the sidewalls of the bit lines, and the spaces between the bit lines are filled with the interlayer insulating layer 23. At this time, as the semiconductor device fabrication process becomes more and more fine and the line width of the bit line 17 is reduced, the bit line pattern having a stacked structure of the bit line barrier metal 16, the bit line 17, and the hard mask 18 is formed. The aspect ratio becomes large and the pattern collapses.

Therefore, even if the process becomes smaller and the line width of the bit line continues to decrease, if the bit line mask process is carried out in a single process as in the present, the bit line pattern may not collapse. There is a need for a solution that can solve the bit line collapse problem without changing.

The present invention has been made to solve the problems of the conventional semiconductor device manufacturing method as described above, after the hard mask is first patterned with a photoresist film during the bit line mask process, the portion and the opening where the patterned hard mask is buried alternately present It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing the collapse phenomenon caused by the reduction of the bit line line width by performing the etching process after reforming the photoresist pattern.

In order to achieve the above object, the present invention

1) sequentially depositing a bit line barrier metal, a bit line, and a hard mask on the semiconductor substrate;

2) forming a first photoresist pattern on the hard mask, and then forming a hard mask pattern using the first photoresist pattern as a mask;

3) forming a second photoresist layer pattern in which the buried portion and the opening are alternately present on the hard mask pattern;

4) etching the lower stacked structure using the second photoresist pattern as a mask;

5) removing the second photoresist pattern and filling the interlayer insulation film between the hard mask patterns;

6) forming a bit line by etching the lower layer structure using the hard mask pattern as a mask; And

7) forming a spacer on the sidewalls of the bit line, and then forming a planarized interlayer insulating film over the entire surface thereof.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, after the bit line barrier metal 160, the bit line 170, and the hard mask 180 are sequentially stacked on the active region 110 of the semiconductor substrate having a predetermined substructure, the bit line barrier metal 160, the bit mask 170, and the hard mask 180 are sequentially stacked. The first photoresist layer pattern 190 is formed on the hard mask. In this case, the first photoresist pattern 190 is formed using a bit line mask.

Referring to FIG. 2B, the hard mask 180 is etched using the first photoresist pattern 190 as a mask to form a hard mask pattern 200.

Referring to FIG. 2C, the second photoresist layer pattern 210 may be formed such that the portions in which the hard mask patterns 200 are embedded and the openings alternately exist. The second photoresist pattern 210 is introduced to prevent collapse by dividing a bit line having a large aspect ratio into two times, and when the aspect ratio of the bit line is so large that there is a risk of collapse. The second photosensitive film pattern may be further introduced into the second photosensitive film pattern so that the ratio of the buried portion is larger than that of the opening.

Referring to FIG. 2D, after etching the lower stacked structure using the second photoresist pattern 210 as a mask, the second photoresist pattern is removed.

Referring to FIG. 2E, after filling the space between the hard mask patterns 200 with the interlayer insulating layer 230, the lower layer structure is etched using the hard mask patterns 200 as a mask to form bit lines. The process is performed by using an etching selectivity difference between the hard mask 180 and other structures, and by using the hard mask pattern 200 as a mask as described above, a separate additional mask process is not required, thereby reducing process steps. have.

Referring to FIG. 2F, after forming the spacer 220 on the sidewall of the bit line, the entire surface is coated with the interlayer insulating layer 230 and the planarization process is performed. The planarization process is preferably carried out by a CMP process, the CMP process may be divided into two or more times, or may be performed at once to simplify the process.

In the present invention, unlike the conventional method in forming a bit line, the etching process is divided into two processes, so that the first etched bit lines serve to lower the aspect ratio by supporting the bit lines in the middle to be etched later. It can effectively solve the line collapse problem.

In addition, the idea that the pattern can be prevented from being collapsed by dividing the etching process twice or more when forming a pattern having a high aspect ratio is not only a bit line applied in the present invention but also an aspect ratio is increased to collapse the pattern. It can be widely applied to any process that can cause problems. For example, the same may be applied to a storage electrode forming process in which the depth of the storage electrode is gradually increased to secure the capacitor capacity. The method of the present invention can be usefully used in a pattern forming process having an aspect ratio of at least 4,000 kPa, preferably at least 4,500 kPa.

As described above, the method of the present invention can solve the problem of pattern collapse due to high aspect ratio during bit line formation without large change in the conventional process. It can be usefully applied to all processes that can cause the pattern to collapse due to the aspect ratio.

Claims (4)

1) sequentially depositing a bit line barrier metal, a bit line, and a hard mask on the semiconductor substrate; 2) forming a first photoresist pattern on the hard mask, and then forming a hard mask pattern using the first photoresist pattern as a mask; 3) forming a second photoresist layer pattern in which the buried portion and the opening are alternately present on the hard mask pattern; 4) etching the lower stacked structure using the second photoresist pattern as a mask; 5) removing the second photoresist pattern and filling the interlayer insulating layer between the hard mask patterns; 6) forming a bit line by etching the lower layer structure using the hard mask pattern as a mask; And 7) forming a planarized interlayer insulating film over the entire surface after forming a spacer on the sidewalls of the bit line. The method of claim 1, The first photosensitive film pattern is a semiconductor device manufacturing method, characterized in that formed using a bit line mask. The method of claim 1, The planarization interlayer insulating film is a method of manufacturing a semiconductor device, characterized in that carried out by a CMP process. The method of claim 1, A method for manufacturing a semiconductor device, characterized in that it is introduced into a pattern forming step having an aspect ratio of 4,000 GHz or more.

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