KR100646967B1 - Thin film transistor and method for fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor and a method of manufacturing the same that can minimize the leakage current of the thin film transistor, the substrate; A semiconductor layer formed on the substrate and including a dopant in a lower region; A gate insulating layer formed on the semiconductor layer; A gate electrode formed on the gate insulating layer; An interlayer insulating layer formed on the gate electrode; And source and drain electrodes formed on the interlayer insulating layer and electrically connected to the semiconductor layer. With this configuration, the present invention injects a low concentration of dopant into the lower region of the semiconductor layer, thereby acting as a diffusion barrier for trace impurities between the interface between the semiconductor layer and the buffer layer, and at the same time applying back vias. Leakage current can be minimized.

Description

Thin film transistor and its manufacturing method {Thin film transistor and method for fabricating the same}

1 is a cross-sectional view of a thin film transistor according to the prior art.

FIG. 2 is a partially enlarged view of region A of FIG. 1.

3 is a cross-sectional view of a thin film transistor according to the present invention.

4 is an enlarged view of a portion B of FIG. 3.

♣ Explanation of symbols for the main parts of the drawing ♣

10: thin film transistor 11: lower insulating layer

12 substrate 13 buffer layer

14a and 14b: first region and second region 14: semiconductor layer

15 gate insulating layer 16 gate electrode

17: interlayer insulating layer 18a, 18b: source / drain electrode

The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly, to a thin film transistor and a method for manufacturing the same that can minimize the leakage current of the thin film transistor.

Recently, the role of a thin film transistor (TFT) used in the field of flat panel display is various, one of which serves as a switching element that changes the transmittance of a pixel by adjusting a voltage applied to a liquid crystal of one pixel. Amorphous-silicon (H) is mainly used as the switching element, which is easy to manufacture in large areas, and thus has high productivity, and can be deposited at a low substrate temperature of 350 ° C. or lower, so that an inexpensive insulating substrate can be used. Because there is. However, because amorphous silicon has disordered atomic arrangement, weak Si-Si bond and dangling bond exist, so it becomes metastable when irradiated with light or electric field. This is emerging. In particular, amorphous silicon has a problem in that its characteristics are deteriorated by light irradiation, and it is difficult to use in a driving circuit due to electrical characteristics (low field effect mobility) and reliability deterioration of display pixel driving elements. On the other hand, polysilicon in the polycrystalline state has a greater field effect mobility than amorphous silicon, which is advantageous for high speed operation circuits and switching devices of high resolution panels.

Polysilicon manufacturing method is divided into low temperature process and high temperature process according to the process temperature. The high temperature process has the disadvantage of using expensive quartz substrates with high thermal resistance because the process temperature is required to be above the strain temperature of the insulating substrate near 1000 ° C. Therefore, crystallization is performed using amorphous silicon capable of low temperature deposition. Efforts are being made in many directions.

In addition, the polysilicon thin film deposited by the high temperature poly process has high surface roughness and low crystallinity such as fine grains during film formation, and device application characteristics are inferior to recrystallization of the amorphous silicon thin film by the low temperature poly process. It is known. The low temperature poly thin film transistor light emitting display device is a next generation new concept technology having superior image quality, high reliability, and low power consumption than conventional amorphous silicon products. In addition, the low temperature poly-process is suitable for mobile phones with high reliability and portability such as vibration, shock, and design by incorporating driving and peripheral circuits in the process. Nevertheless, the high leakage current of the low temperature poly thin film transistor acts as an electrical defect of the thin film transistor.

Hereinafter, a conventional thin film transistor will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a conventional thin film transistor 20. Referring to FIG. 1, in the conventional thin film transistor 20, a lower insulating layer 21 is formed on a lower surface of the substrate 22, and a buffer layer 23 is formed on the substrate 22. The semiconductor layer 24 formed of polysilicon on the buffer layer 23, the gate insulating layer 25 formed on the semiconductor layer 24, the gate electrode 26 formed on the gate insulating layer 25, and the gate electrode The interlayer insulating layer 27 formed on the layer 26 and the interlayer insulating layer 27 are formed, and include source and drain electrodes 28a and 28b electrically connected to the semiconductor layer 24.

FIG. 2 is a partially enlarged view of region A of FIG. 1. Referring to FIG. 2, the substrate 22 includes a substrate 22 formed on the lower insulating layer 21, a buffer layer 23 formed on the substrate 22, and a semiconductor layer 24 formed on the buffer layer 23. A small amount of impurities remain between the buffer layer 23 on the substrate 22 and the interface of the semiconductor layer 24. These impurities are factors that degrade leakage current, mobility, and threshold voltage characteristics, which are the main characteristics of the thin film transistor. do. In particular, impurities remaining at the interface between the buffer layer 23 and the semiconductor layer 24 have a problem of increasing leakage current by passing a current during the thin film transistor operation.

In order to solve the above problems, for example, Korean Patent Laid-Open Publication No. 2003-0052561, when manufacturing a low temperature poly thin film by the metal induction crystallization method, by optimally adjusting the thickness of the amorphous silicon between the semiconductor layer and the amorphous silicon thin film By reducing the internal defects due to the interfacial lattice constant, the polysilicon layer is used as the channel to improve the characteristics of the thin film transistor by increasing the electron mobility in the channel and reducing the amount of leakage current. However, the patent also has a problem of increasing the leakage current due to impurities remaining at the interface between the buffer layer and the semiconductor layer.

Accordingly, the present invention is an invention devised to solve the above-mentioned conventional problems, and a small amount of impurities including impurities remaining between the interface between the semiconductor layer and the buffer layer by injecting a low concentration of dopant into the first region of the semiconductor layer. The present invention provides a thin film transistor and a method of manufacturing the same, which serve as a diffusion barrier and minimize leakage of carriers in a channel toward the buffer layer interface when the thin film transistor is operated.

In order to achieve the above object, according to an aspect of the present invention, the thin film transistor is a substrate, a semiconductor layer formed on the substrate, a dopant in the lower region, and a gate formed on the semiconductor layer And an insulating layer, a gate electrode formed on the gate insulating layer, an interlayer insulating layer formed on the gate electrode, and a source and drain electrode formed on the interlayer insulating layer and electrically connected to the semiconductor layer.

The semiconductor device may further include at least one buffer layer stacked between the substrate and the semiconductor layer, wherein the semiconductor layer may include a first region in which a dopant is implanted and a second region in which the dopant is not implanted. The dopant is implanted into the first region in a concentration range of 10 ¹² ppm to 10 ¹⁴ ppm, and the dopant implanted into the first region is either N-type or P-type. The first region into which the dopant is implanted is formed to have a thickness of 10 GPa or more, but not to exceed the thickness of the second region into which the dopant is not implanted. In addition, the substrate is a conductive substrate, and further includes a lower insulating layer on the lower surface of the substrate.

According to one or more exemplary embodiments, a method of manufacturing a thin film transistor includes forming a semiconductor layer on a substrate, injecting a dopant into a lower region of the semiconductor layer, and forming a gate insulating layer on the semiconductor layer. And forming a gate electrode on the gate insulating layer, forming an interlayer insulating layer on the gate electrode, and forming a source and a drain electrode on the interlayer insulating layer.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, the method comprising: forming a first region in which a dopant is implanted on a substrate, forming a second region in which the dopant is not implanted on the first region; Forming a gate insulating layer on the second region, forming a gate electrode on the gate insulating layer, forming an interlayer insulating layer on the gate electrode, and forming a source on the interlayer insulating layer; Forming a drain electrode.

According to another aspect of the present invention, a method of manufacturing a thin film transistor includes forming an amorphous silicon layer on a substrate, depositing a crystallization inducing metal on the amorphous silicon layer, and depositing amorphous silicon on which the crystallization inducing metal is deposited. Heating the layer to form a polysilicon layer, implanting a dopant in a lower region of the polysilicon layer, forming a gate insulating layer on the polysilicon layer, and forming a gate on the gate insulating layer Forming an electrode, forming an interlayer insulating layer on the gate electrode, and forming a source and a drain electrode on the interlayer insulating layer.

The region in which the dopant is implanted is formed in a concentration range of 10 ¹² ppm to 10 ¹⁴ ppm, and the first region in which the dopant is implanted is formed to have a thickness of 10 GPa or more, but not to exceed the thickness of the second region in which the dopant is not implanted. It is desirable to. In addition, the crystallization induction metal is nickel (Ni) or palladium (Pd) or cobalt (Co) or copper (Cu).

Hereinafter, a thin film transistor and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings of the present invention.

3 is a cross-sectional view of the thin film transistor 10 according to the present invention. Referring to FIG. 3, in the thin film transistor 10 according to the present invention, a lower insulating layer 11 is formed on a lower surface of the substrate 12, and a buffer layer 13 is formed on the substrate 12. On the buffer layer 13, a semiconductor layer 14 into which a low concentration of dopant is injected is formed in the lower region. The gate insulating layer 15, the gate electrode 16, and the interlayer insulating layer 17 are sequentially formed on the semiconductor layer 14. It also includes source and drain electrodes 18a and 18b formed on the interlayer insulating layer 17 and electrically connected to the semiconductor layer 14.

The substrate 12 may be formed of a conductive substrate, and stainless steel (SUS), Ti (titanium), Mo (molybdenum), Fe (iron), Co (cobalt), or the like may be used, but is not limited thereto. . In addition, the lower insulating layer 11 serves to reduce the stress applied to the substrate 12 during the process, and the buffer layer 13 is formed to prevent the substrate 12 from being damaged by external heat. The lower insulating layer 11 and the buffer layer 13 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) and silicon nitride (SiNx), or an organic insulating material such as acrylic organic compound, polyamide, polyimide, or the like. It is used, but not limited to.

4 is an enlarged view of a portion B of FIG. 3. Referring to FIG. 4, a substrate 12 is formed on the lower insulating layer 11, and a buffer layer 13 is formed on the substrate 12. The semiconductor layer 14 in which the dopant is implanted is formed in the lower region on the buffer layer 13. The concentration of the dopant implanted region, which is the lower region of the semiconductor layer, is doped in the range of 10 ¹² ppm to 10 ¹⁴ ppm, and either dopant of N type or P type is implanted. In addition, the first region in which the dopant is implanted is formed to have a thickness of 10 kPa or more, but not to exceed the thickness of the second region in which the dopant is not implanted. The thickness of the second region 14b in which the dopant is not implanted is formed to be 1000 Å or less.

In the method of forming the first region 14a into which the dopant is injected, in the case of P-MOS, dopants such as B ₂ H ₆ , B, and BH ₃ containing B, which is a group 3 element, which forms an N-layer, In the case of -MOS, a dopant such as PH ₃ , P, As, or the like containing P or As, which forms a P-layer, may be implanted or a doped layer may be deposited, but is not limited thereto. The implantation of the dopant in the first region is performed by ion implantation with a large acceleration voltage. In addition, the dopant implantation is preferably performed at room temperature, which is ion activation when the temperature is high during the dopant implantation, and ion diffusion occurs, and when the ion diffusion occurs, the dopant is implanted. This is because not all of the semiconductor layers may be ion contamination.

By forming the first region in which the dopant is implanted in the semiconductor layer, a space charge region is formed near the interface between the second region in which the dopant is not implanted and the buffer layer. The space charge region refers to a region where charges do not enter the metal and charges are accumulated around the electrode. Accumulated charges create an electromagnetic field around them, and the distribution of charge or current itself is affected.

Accordingly, the first region of the semiconductor layer into which the dopant is implanted serves as a diffusion barrier of a small amount of impurities including impurities remaining between the interface of the first region of the semiconductor layer and the buffer layer during crystallization using a metal catalyst, and at the same time, a thin film transistor It is possible to minimize the leakage of carriers in the channel toward the lower buffer layer interface during the operation.

Referring to the method of manufacturing a thin film transistor according to an aspect of the present invention, a semiconductor layer is formed on a substrate. After the semiconductor layer is formed, the semiconductor layer is crystallized by a metal catalyst utilizing crystallization method. The crystallization method using a metal catalyst is a method of crystallizing amorphous silicon by depositing a crystallization induction metal such as nickel on a part of the amorphous silicon and performing heat treatment. When crystallization, it is possible to effectively induce the crystallization of silicon by heating to a temperature of about 400 ~ 600 ℃ in the furnace. Since a large amount of substrates can be heated in a heating furnace, there is an advantage in that the productivity is high and the crystal uniformity and the yield are higher than those of the laser heat treatment method.

A dopant having a concentration of 10 ¹² ppm to 10 ¹⁴ ppm is implanted into the lower region of the crystallized semiconductor layer. The first region into which the dopant is implanted is formed to a thickness of 10 GPa or more, but not to exceed the thickness of the second region to which the dopant is not implanted. The gate insulating layer, the gate electrode, and the interlayer insulating layer are sequentially formed on the semiconductor layer. Then, source and drain electrodes are formed on the interlayer insulating layer.

The method of manufacturing a thin film transistor according to another aspect and another aspect of the present invention, for convenience of description, a detailed description of the same configuration as the manufacturing step of the thin film transistor according to one aspect of the present invention will be omitted.

Referring to a method of manufacturing a thin film transistor according to another aspect of the present invention, a first region is formed on a substrate. Then, the first region formed of amorphous silicon is crystallized into a polysilicon layer. Dopants in the range of 10 ¹² ppm to 10 ¹⁴ ppm are implanted into the crystallized first region. A second region is formed on the lightly doped first region and the second region is crystallized. A gate insulating layer is formed on the second region, and the gate insulating layer serves to insulate the semiconductor layer from the gate electrode. The gate electrode, the interlayer insulating layer, the source and the drain electrode are sequentially formed on the gate insulating layer.

According to another aspect of the present invention, a method of manufacturing a thin film transistor forms an amorphous silicon layer on a substrate. Next, a crystallization induction metal is deposited on the amorphous silicon layer, and the amorphous silicon layer on which the crystallization induction metal is deposited is heated to form a polysilicon layer. Nickel (Ni) or palladium (Pd) or cobalt (Co) or copper (Cu) is used as the crystallization inducing metal, but in addition, Ti, Ag, Au, Al, Sn, Sb, Cr, Mo, Tr, Ru, Rh Metals such as, Cd, Pt and the like may be used.

Next, a dopant is implanted into the lower region of the polysilicon layer, and a gate insulating layer, a gate electrode, and an interlayer insulating layer are sequentially formed on the polysilicon layer. Finally, source and drain electrodes are formed on the interlayer insulating layer.

In the above-described embodiment of the present invention, the dopant is implanted at a low concentration after crystallizing the semiconductor layer and injecting a low concentration of dopant into the first region of the semiconductor layer or crystallizing the first region of the semiconductor layer. After the dopant was implanted and doped, a second region was formed on the first region and then crystallized. However, it is of course possible to inject the dopant into the first region of the semiconductor layer after the source and drain electrodes are formed on the crystallized semiconductor layer or after the gate insulating layer and the gate electrode are formed. When the gate insulating layer and the gate electrode are formed after the formation of the gate insulating layer, a thermal oxide film or a silicon oxide film may be used as the gate insulating layer to minimize damage due to thermal stress.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a low concentration of dopant is injected into the lower region of the semiconductor layer to form a space charge region near the interface between the semiconductor layer and the buffer layer, thereby providing an interface between the semiconductor layer and the buffer layer. While acting as a diffusion barrier for trace impurities including impurities remaining in the thin film transistor, an electrical potential barrier structure is formed to minimize the leakage of carriers in the channel toward the lower buffer layer interface during the operation of the thin film transistor. Current characteristics, mobility, and threshold voltage characteristics can also be improved.

Claims (14)

Board; A semiconductor layer formed on the substrate and including a dopant in a lower region; A gate insulating layer formed on the semiconductor layer; A gate electrode formed on the gate insulating layer; An interlayer insulating layer formed on the gate electrode; And Source and drain electrodes formed on the interlayer insulating layer and electrically connected to the semiconductor layer; Thin film transistor comprising a. The thin film transistor of claim 1, further comprising at least one buffer layer stacked between the substrate and the semiconductor layer. The thin film transistor of claim 1, wherein the semiconductor layer comprises a first region in which a dopant is implanted and a second region in which the dopant is not implanted. The thin film transistor of claim 3, wherein the first region is doped with a dopant in a concentration range of 10 ¹² ppm to 10 ¹⁴ ppm. The thin film transistor of claim 3, wherein the dopant to be injected into the first region is one of an N type and a P type. 4. The thin film transistor of claim 3, wherein the first region into which the dopant is implanted is formed to a thickness of 10 GPa or more, but does not exceed the thickness of the second region into which the dopant is not implanted. The thin film transistor of claim 1, wherein the substrate is a conductive substrate. The thin film transistor of claim 1, further comprising a lower insulating layer formed on a lower surface of the substrate. Forming a semiconductor layer on the substrate; Implanting a dopant into the lower region of the semiconductor layer; Forming a gate insulating layer on the semiconductor layer; Forming a gate electrode on the gate insulating layer; Forming an interlayer insulating layer on the gate electrode; And Forming a source and a drain electrode on the interlayer insulating layer; Method of manufacturing a thin film transistor comprising a. Forming a first region implanted with a dopant on the substrate; Forming a second region in which the dopant is not implanted on the first region; Forming a gate insulating layer on the second region; Forming a gate electrode on the gate insulating layer; Forming an interlayer insulating layer on the gate electrode; And Forming a source and a drain electrode on the interlayer insulating layer; Method of manufacturing a thin film transistor comprising a. Forming an amorphous silicon layer on the substrate; Depositing a crystallization inducing metal on the amorphous silicon layer; Forming a polysilicon layer by heating the amorphous silicon layer on which the crystallization induction metal is deposited; Implanting a dopant into the lower region of the polysilicon layer; Forming a gate insulating layer on the polysilicon layer; Forming a gate electrode on the gate insulating layer; Forming an interlayer insulating layer on the gate electrode; And Forming a source and a drain electrode on the interlayer insulating layer; Method of manufacturing a thin film transistor comprising a. The method of claim 9, wherein the region into which the dopant is implanted is formed in a concentration range of 10 ¹² ppm to 10 ¹⁴ ppm. The method of claim 9, wherein the region of the semiconductor layer into which the dopant is implanted is formed to a thickness of 10 Å or more but does not exceed the thickness of the region of the semiconductor layer to which the dopant is not implanted. The method of claim 11, wherein the crystallization inducing metal is nickel (Ni) or palladium (Pd) or cobalt (Co) or copper (Cu).

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