KR100592383B1 - Manufacturing apparatus and manufacturing method of thin film transistor array substrate - Google Patents

Abstract

The present invention relates to a manufacturing apparatus and a manufacturing method of a thin film transistor array substrate that can simplify the manufacturing process, improve cost and productivity.

In the apparatus for manufacturing a thin film transistor array substrate, an immersion strip portion for simultaneously removing a plurality of substrates on which the photoresist and the transparent electrode are stacked in a stripping liquid and simultaneously removing the photoresist and the transparent electrode formed on the plurality of substrates in a lift off process. Wow; And a spray strip portion for spraying the strip liquid onto the photoresist and the transparent electrode remaining on the substrate passed through the immersion strip portion.

Description

TECHNICAL APPARATUS AND MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE {FABRICATION APPARATUS AND METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE}

1 is a plan view showing a portion of a conventional thin film transistor array substrate.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along line II ′. FIG.

3A through 3D are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view illustrating a thin film transistor array substrate manufactured by an apparatus and a manufacturing method of a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array substrate of FIG. 4 taken along a line II-II '.

6A through 8D are steps illustrating a method of manufacturing a thin film transistor array substrate manufactured by a manufacturing method according to an exemplary embodiment of the present invention.

9 is a view showing a manufacturing apparatus of a thin film transistor array substrate according to a first embodiment of the present invention.

10 is a cross-sectional view illustrating a thin film transistor array substrate before a lift off process.

FIG. 11 is a cross-sectional view illustrating a thin film transistor array substrate after a lift-off process through the apparatus for manufacturing the thin film transistor array substrate illustrated in FIG. 9.

12 is a view showing a manufacturing apparatus of a thin film transistor array substrate according to a second embodiment of the present invention.

         <Explanation of symbols for the main parts of the drawings>

2, 52: gate line 4, 58: data line

6, 80 thin film transistor 8, 54 gate electrode

10, 60: source electrode 12, 62: drain electrode

14, 92: active layer 16: the first contact hole

18, 72: pixel electrodes 20, 78: storage capacitor

22, 66: storage electrode 24: second contact hole

26, 82: gate pad portion 28, 56: gate pad lower electrode

30: third contact hole 32, 74: gate pad upper electrode

34, 84: data pad portion 36, 64: data pad lower electrode

38: fourth contact hole 40, 76: data pad upper electrode

42, 88: lower substrate 44: gate insulating film

47, 147: semiconductor pattern 48, 94: ohmic contact layer

50: shield 90: gator insulation pattern

98: protective film pattern 100, 200: manufacturing apparatus

102, 202: Cassette 104: Tank

106: injection nozzle 108, 208: first pump

110, 210: first filter 112: photoresist pattern

114: deposition film 116, 216: stripping liquid

118: pattern 120, 220: second filter

128, 228: second pump 130, 230: ultrasonic generator

140, 240: immersion strip portion 150: spray strip portion

204: first tank 206: first injection nozzle

224: second tank 226: second injection nozzle

250: first spray strip portion 260: second spray strip portion

270: aqua knife 280: third filter

290: fourth filter 101, 202: stripper

The present invention relates to a manufacturing apparatus and a manufacturing method of a thin film transistor array substrate, and more particularly to a manufacturing apparatus and a manufacturing method of a thin film transistor array substrate to simplify the manufacturing process and to quickly and completely remove the photoresist and transparent electrode in the lift-off process. will be.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor array substrate includes gate lines and data lines, thin film transistors formed of switch elements at intersections of the gate lines and data lines, pixel electrodes formed in liquid crystal cell units and connected to the thin film transistors, and the like. It consists of the applied alignment film. The gate lines and the data lines receive signals from the driving circuits through the respective pad parts. The thin film transistor supplies the pixel voltage signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate includes color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon. It consists of.

The liquid crystal panel is completed by separately manufacturing a thin film transistor array substrate and a color filter array substrate, and then injecting and encapsulating a liquid crystal.

In such a liquid crystal panel, the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, and thus, the manufacturing process is complicated, and thus, the cost of the LCD panel manufacturing cost is increasing. In order to solve this problem, the thin film transistor array substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. Accordingly, in recent years, a four-mask process that reduces one mask process in a five-mask process, which is a standard mask process of a thin film transistor array substrate, has emerged.

FIG. 1 is a plan view showing a portion of a conventional thin film transistor array substrate, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II ′.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 formed on the lower substrate 42 with the gate insulating film 44 interposed therebetween, and a thin film formed at each intersection thereof. The transistor 6 and the pixel electrode 18 formed in the cell area provided in the cross structure are provided. The thin film transistor array substrate includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 18 and the previous gate line 2, a gate pad portion 26 connected to the gate line 2, and a data line. The data pad part 34 connected to (4) is provided.

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 16. And an active layer 14 overlapping the gate electrode 8 and forming a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is formed to overlap the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12, and the source electrode 10 and the drain electrode ( 12) further comprises a channel section therebetween. An ohmic contact layer 48 for ohmic contact with the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 14. do. The thin film transistor 6 keeps the pixel voltage signal supplied to the data line 4 charged in the pixel electrode 18 in response to the gate signal supplied to the gate line 2.

The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 16 penetrating through the passivation layer 50. The pixel electrode 18 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

The storage capacitor 20 includes a storage electrode 22 overlapping the gate line 2 of the previous stage and the gate line 2, the gate insulating layer 44, the active layer 14, and the ohmic contact layer 48 therebetween. And the pixel electrode 18 which is overlapped with the storage electrode 22 and the passivation layer 50 interposed therebetween and connected via the second contact hole 24 formed in the passivation layer 50. The storage capacitor 20 allows the pixel voltage charged in the pixel electrode 18 to be stably maintained until the next pixel voltage is charged.

The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad portion 26 is formed through the gate pad lower electrode 28 extending from the gate line 2, and the gate pad lower electrode through the third contact hole 30 penetrating through the gate insulating layer 44 and the passivation layer 50. And a gate pad upper electrode 32 connected to (28).

The data line 4 is connected to a data driver (not shown) through the data pad unit 34. The data pad part 34 is connected to the data pad lower electrode 36 through the data pad lower electrode 36 extending from the data line 4 and the fourth contact hole 38 penetrating through the passivation layer 50. The data pad upper electrode 40 is formed.

The thin film transistor array substrate having such a configuration is formed by a four mask process.

3A through 3D are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

Referring to FIG. 3A, a gate line 2, a gate electrode 8, and a gate pad lower electrode 28 are formed on the lower substrate 42.

The gate metal layer is formed on the lower substrate 42 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form gate patterns including the gate line 2, the gate electrode 8, and the gate pad lower electrode 28. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Referring to FIG. 3B, the gate insulating layer 44, the active layer 14, the ohmic contact layer 48, and the source / drain patterns are sequentially formed on the lower substrate 42 on which the gate patterns are formed.

The gate insulating layer 44, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 42 on which the gate patterns are formed through a deposition method such as PECVD or sputtering.

A photoresist pattern is formed on the source / drain metal layer by a photolithography process using a second mask. In this case, the photoresist pattern of the channel portion has a lower height than the other source / drain pattern portions by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor as the second mask.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, thereby forming the data line 4, the source electrode 10, the drain electrode 12 integrated with the source electrode 10, and the storage electrode 22. Including source / drain patterns are formed.

Next, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form a semiconductor pattern 47 including the ohmic contact layer 48 and the active layer 14.

The photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 48 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 10 and the drain electrode 12.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a strip process.

As the material of the gate insulating film 44, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Referring to FIG. 3C, a passivation layer 50 including first to fourth contact holes 16, 24, 30, and 38 is formed on the gate insulating layer 44 on which the source / drain patterns are formed.

The passivation layer 50 is entirely formed on the gate insulating layer 44 on which the source / drain patterns are formed by a deposition method such as plasma enhanced chemical vapor deposition (hereinafter, referred to as "PECVD"). The passivation layer 50 is patterned by a photolithography process and an etching process using a third mask to form first to fourth contact holes 16, 24, 30, and 38. The first contact hole 16 is formed to pass through the passivation layer 50 to expose the drain electrode 12, and the second contact hole 24 is formed to pass through the passivation layer 50 to expose the storage electrode 22. do. The third contact hole 30 is formed to pass through the passivation layer 50 and the gate insulating layer 44 to expose the gate pad lower electrode 28. The fourth contact hole 38 penetrates through the passivation layer 50 to expose the lower data pad electrode 36.

As the material of the protective film 50, an inorganic insulating material such as the gate insulating film 44 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 3D, transparent electrode patterns are formed on the passivation layer 50.

The transparent electrode material is entirely deposited on the passivation layer 50 by a deposition method such as sputtering. Subsequently, the transparent electrode material is immersed through a photolithography process and an etching process using a fourth mask to form transparent electrode patterns including the pixel electrode 18, the gate pad upper electrode 32, and the data pad upper electrode 40. do. The pixel electrode 18 is electrically connected to the drain electrode 12 through the first contact hole 16 and overlaps the previous gate line 2 through the second contact hole 24. And electrically connected. The gate pad upper electrode 32 is electrically connected to the gate pad lower electrode 28 through the third contact hole 30. The data pad upper electrode 40 is electrically connected to the data pad lower electrode 36 through the fourth contact hole 38. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, the conventional thin film transistor substrate and the method of manufacturing the same can reduce the number of manufacturing steps and reduce the manufacturing cost in proportion to the case of using the 5 mask process by employing the 4 mask process. However, since the four-mask process is still a complicated manufacturing process, there is a limit in cost reduction, there is a need for a thin film transistor substrate and a method for manufacturing the same, which further simplify the manufacturing process and improve the production cost.

Accordingly, an object of the present invention is to provide a thin film transistor array substrate manufacturing apparatus and method for simplifying a manufacturing process and quickly and completely removing a photoresist and a transparent electrode in a lift-off process.

In order to achieve the above object, a device for manufacturing a thin film transistor array substrate according to an embodiment of the present invention is to immerse a plurality of substrates each of which a photoresist and a transparent electrode is laminated in a stripping liquid on the plurality of substrates in the lift-off process An immersion strip portion which simultaneously removes the formed photoresist and the transparent electrode; And a spray strip portion for spraying the strip liquid onto the photoresist and the transparent electrode remaining on the substrate passed through the immersion strip portion.
The immersion strip part includes a stripper containing the strip liquid, a cassette receiving the plurality of substrates, a cassette immersed in strip liquid in the stripper, an ultrasonic wave generator generating ultrasonic waves and applying ultrasonic waves into the stripper, and strip liquid in the stripper. And a pump for filtering the impurities contained in the strip liquid discharged by the pump and supplying the filtered strip liquid to the stripper.
The spray strip part includes a plurality of spray nozzles for spraying the strip liquid onto the substrate, a tank for supplying the strip liquid to the plurality of spray nozzles, and a pump for discharging the strip liquid sprayed from the plurality of spray nozzles. And a filter for filtering impurities in the strip liquid discharged by the pump and supplying the filtered strip liquid to the tank.
The spray strip portion may spray strip liquid onto the substrate that has passed through the immersion strip portion to remove photoresist and transparent electrodes remaining on the substrate, and to apply strip liquid to the substrate that has passed through the first spray strip portion. And a second spray strip portion for spraying strip liquid onto the substrate that has passed through the high pressure spray strip portion.
At least one of the first and second spray strip portions may include a plurality of spray nozzles for spraying the strip liquid onto the substrate, a tank for supplying the strip liquid to the spray nozzles, and the spray nozzles sprayed by the spray nozzles. And a pump for discharging the strip liquid and a filter for filtering impurities in the strip liquid discharged by the pump and for supplying the filtered strip liquid to the tank.
The high pressure jet strip unit includes a high pressure injector for injecting the strip liquid at a high pressure, and a filter for filtering impurities in the strip liquid supplied to the high pressure injector.
The high pressure injector has an aqua knife.
In the method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention, a plurality of substrates on which photoresist and a transparent electrode are stacked are immersed in a stripping solution, thereby performing photoresist and transparent electrodes formed on the plurality of substrates in a lift-off process. Simultaneously removing the first step; And injecting the stripping liquid into the photoresist and the transparent electrode remaining on the substrate after the first step.
Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

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      Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 12.

4 is a plan view illustrating a thin film transistor array substrate manufactured by an apparatus and a manufacturing method of a thin film transistor array substrate according to an embodiment of the present invention, Figure 5 is a thin film transistor array substrate shown in Figure 4 II-II Is a cross-sectional view taken along a line.

The thin film transistor array substrate illustrated in FIGS. 4 and 5 includes a gate line 52 and a data line 58 intersecting each other with a gate insulating pattern 90 interposed on the lower substrate 88, and formed at each intersection thereof. The thin film transistor 80 is provided with a pixel electrode 72 formed in a cell region provided in an intersecting structure. The thin film transistor array substrate includes a storage capacitor 78 formed at an overlapping portion of the storage electrode 66 connected to the pixel electrode 72 and the previous gate line 52, and a gate pad connected to the gate line 52. A unit 82 and a data pad unit 84 connected to the data line 58 are provided.

The thin film transistor 80 includes a gate electrode 54 connected to the gate line 52, a source electrode 60 connected to the data line 58, and a drain electrode 62 connected to the pixel electrode 72. The active layer 92 and the ohmic contact layer 94 overlapping each other with the gate electrode 54 and the gate insulating pattern 90 interposed therebetween to form a channel 70 between the source electrode 60 and the drain electrode 62. It includes a semiconductor pattern 147 including. The thin film transistor 80 allows the pixel voltage signal supplied to the data line 58 to be charged and held in the pixel electrode 72 in response to the gate signal supplied to the gate line 52.

The semiconductor pattern 147 includes a channel portion between the source electrode 60 and the drain electrode 62, and includes the source electrode 60, the drain electrode 62, the data line 58, and the data pad lower electrode 64. And an active layer 92 partially overlapping the gate line 52 with the gate insulating pattern 90 interposed therebetween and overlapping the storage electrode 66. The semiconductor pattern 147 is in contact with the source electrode 60, the drain electrode 62, the storage electrode 66, the data line 58, and the data pad lower electrode 64 on the active layer 92. The formed ohmic contact layer 94 is further provided.

The pixel electrode 72 is connected to the drain electrode 62 of the thin film transistor 80 exposed to the outside of the passivation layer pattern 98. The pixel electrode 72 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits light incident through the pixel electrode 72 from the light source (not shown) toward the upper substrate.

The storage capacitor 78 overlaps the previous gate line 52 with the gate line 52 interposed therebetween with the gate insulating pattern 90, the active layer 92, and the ohmic contact layer 94 interposed therebetween, and the pixel electrode 72. ) Is connected to the storage electrode 66. The pixel electrode 72 is connected to the storage electrode 66 exposed to the outside of the passivation layer 98. The storage capacitor 78 allows the pixel voltage charged in the pixel electrode 72 to be stably maintained until the next pixel voltage is charged.

The gate line 52 is connected to a gate driver (not shown) through the gate pad portion 82. The gate pad portion 82 includes a gate pad lower electrode 56 extending from the gate line 52 and a gate pad upper electrode 74 connected to the gate pad lower electrode 56.

The data line 58 is connected to a data driver (not shown) through the data pad unit 84. The data pad portion 84 includes a data pad lower electrode 64 extending from the data line 58 and a data pad upper electrode 76 connected to the data pad lower electrode 64. The data pad part 84 further includes a gate insulating pattern 90, an active layer 92, and an ohmic contact layer 94 formed between the data pad lower electrode 64 and the lower substrate 88.

The gate insulating pattern 90 and the passivation layer pattern 98 are formed in regions where the pixel electrode 72, the gate pad upper electrode 74, and the data pad upper electrode 76 are not formed.

The thin film transistor array substrate having such a configuration is formed by a three mask process. The thin film transistor array substrate manufacturing method according to an embodiment of the present invention using a three mask process includes a first mask process for forming gate patterns, a second mask process for forming semiconductor patterns 147 and source / drain patterns; And a third mask process for forming the gate insulating pattern 90, the passivation layer 98 pattern, and the transparent electrode patterns.

6A through 8D are steps illustrating a method of manufacturing a thin film transistor array substrate manufactured by a manufacturing method according to an exemplary embodiment of the present invention.

6A and 6B are plan views and cross-sectional views illustrating gate patterns formed on a lower substrate 88 by a first mask process in a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention.

6A and 6B, a gate metal layer is formed on the lower substrate 88 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form gate patterns including the gate line 52, the gate electrode 54, and the gate pad lower electrode 56. As the gate metal, Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) and the like are used in a single layer or a double layer structure.

7A to 7C are plan views and cross-sectional views of a substrate including a source / drain pattern and a semiconductor pattern 147 formed by a second mask process in a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention.

Referring to FIGS. 7A to 7C, the gate insulating layer 90a, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 88 on which the gate patterns are formed through a deposition method such as PECVD or sputtering. Is formed. As the material of the gate insulating film 90a, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Subsequently, as shown in FIG. 7B, the photoresist pattern 71b is formed by a photolithography process and an etching process using the second mask. In this case, the photoresist pattern of the channel portion has a lower height than the source / drain pattern portion by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor as the second mask.

Subsequently, the source / drain metal layer is patterned by a wet etching process using the photoresist pattern 71b so that the data line 58, the source electrode 60, the drain electrode 62 integrated with the source electrode 60, and the storage electrode are formed. Source / drain patterns comprising 64 are formed.

Next, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern 71b to form the ohmic contact layer 94 and the active layer 92.

Then, the photoresist pattern 71a having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 94 of the channel portion are etched by a dry etching process. Accordingly, the active layer 92 of the channel portion is exposed to separate the source electrode 60 and the drain electrode 62.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

8A to 8D are plan views and cross-sectional views of a substrate including a gate insulating pattern 90, a passivation layer pattern 98, and a transparent electrode pattern formed by a third mask process in a method of manufacturing a thin film transistor array substrate, according to an embodiment of the present invention. to be.

8A to 8D, inorganic insulating materials such as SiNx and SiOx, acrylic organic compounds having a low dielectric constant, BCB, or the like, may be deposited on the gate insulating film 90a on which source / drain patterns are formed. Alternatively, a protective film 98a using an organic insulating material such as PFCB is deposited on the entire surface, and a photoresist is entirely coated on the protective film 98a. A photoresist pattern 71c is then formed as shown in FIG. 8B by a photolithography process using a third mask. Subsequently, the passivation layer 98a and the gate insulating layer 90a are patterned using the photoresist pattern 71c as a mask so that the gate insulation pattern 90 and the passivation layer pattern 98 are formed in the remaining regions except for the region where the transparent electrode pattern remains. Is formed. Subsequently, the transparent electrode material 74a is deposited on the entire surface of the substrate 88 on which the photoresist pattern 71c remains by a deposition method such as sputtering as shown in FIG. 8C. Indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used as the transparent electrode 74a. The photoresist pattern 71c is removed by a strip process using a lift 0ff method on the thin film transistor array substrate on which the transparent electrode material 74a is entirely deposited. At this time, the transparent electrode material 74a deposited on the photoresist pattern 71c is removed while the photoresist pattern 71c is separated, so that the gate pad upper electrode 74 and the pixel electrode 72 are shown in FIG. 8D. And a transparent electrode pattern including the data pad upper electrode 76.

The gate pad upper electrode 74 is formed to cover the gate pad lower electrode 56, and the pixel electrode 72 is electrically connected to the drain electrode 62 of the thin film transistor and the storage electrode 66 of the storage capacitor 78. The data pad upper electrode 76 is electrically connected to the data pad lower electrode 64.

As described above, in the method of manufacturing the thin film transistor array substrate according to the present invention, the transparent electrode pattern may be formed without a separate mask process by the lift-off method applied in the third mask process. That is, the transparent electrode material is deposited on the photoresist remaining on the protective pattern, and then the photoresist pattern and the transparent electrode material overlapping the photoresist pattern are removed by a strip process using a lift-off method to form a transparent electrode pattern. do. Accordingly, the manufacturing method of the thin film transistor array substrate according to the present invention has the effect of simplifying the manufacturing process to improve productivity and reducing the manufacturing cost, compared to the conventional manufacturing method using a 5 mask or 4 mask process.

However, in order to completely remove the photoresist pattern remaining on the protective pattern through the strip process and the transparent electrode material on the photoresist pattern through the strip process, a large amount of time and a large amount of strip liquid are required. In addition, failure of the photoresist pattern and the transparent electrode material on the photoresist pattern to be completely removed may cause a failure of the thin film transistor array substrate.

To this end, the photoresist pattern and the transparent electrode material overlapping the photoresist pattern are removed using the manufacturing apparatus shown in FIGS. 9 and 12.

9 is a view showing a manufacturing apparatus of a thin film transistor array substrate according to a first embodiment of the present invention.

In the apparatus 100 for manufacturing the thin film transistor array substrate illustrated in FIG. 9, a plurality of lower substrates 88 on which the photoresist pattern 112 and the deposition film (or thin film) 114 illustrated in FIG. 10 are formed are immersed and stripped. The immersion strip part 140 and the spray strip part 150 for removing the photoresist pattern 112 and the deposition film 114 remaining on the lower substrate 88 which have been subjected to the immersion strip process are provided.

The immersion strip part 140 includes a stripper 101 filled with a strip liquid 116 therein, a cassette 102 for accommodating a plurality of lower substrates 88, and a strip liquid 116 filled in the stripper 101. ), A first filter 110 for filtering the strip liquid 106 circulated by the first pump 108, and an ultrasonic wave to generate ultrasonic waves into the cassette 102. It is provided with an ultrasonic generator 130 for applying.

The stripper 101 fills the strip liquid 116 therein, and the cassette 102 is immersed in the stripper 101.

The cassette 102 is large enough to accommodate a plurality of lower substrates 88 (for example, 20 to 30 sheets), and a photoresist pattern 112 and a deposition film formed on the lower substrate 88. Strip liquid 116 for removing 114 is immersed in the filled stripper 101.

When the plurality of lower substrates 88 on which the photoresist pattern 112 and the deposition film 114 are formed in the cassette 102 and the cassette 102 is immersed, the cassette 102 is formed on the lower substrate 88 shown in FIG. Most of the photoresist pattern 112 and the deposition film 114 except for the pattern portion to be removed are removed by the strip liquid 116. This process is called immersion strip process.

In the manufacturing method using the cassette 102, a plurality of lower substrates 88 are placed in the cassette 102 in order to improve productivity of the thin film transistor array substrate, and the cassette 102 is filled with the strip liquid 116 therein. It is immersed in the stripper 101. At this time, the period of immersing the lower substrate 88 is set to the minimum period of time that the first substrate to finish the immersion strip process of the plurality of substrates and proceed to the next process can be sufficiently stripped. When the plurality of lower substrates 88 are immersed in the strip liquid 116 by using the cassette 102, the plurality of lower substrates 88 may be simultaneously immersed and stripped in a period of immersing and stripping one lower substrate 88. . For example, if the time required to strip a single lower substrate in a general stripping process takes 2 hours, it takes 50 hours to strip all 25 lower substrates, but the manufacturing method using the cassette 102 according to the present invention can be used. In this case, all 50 lower substrates 88 may be stripped in 2 hours, which is a period of stripping one lower substrate 88.

When the plurality of lower substrates 88 on which the photoresist pattern 112 and the deposition layer 114 are formed are immersed in the strip liquid 116, the photoresist pattern 112 and the deposition layer 114 formed on the lower substrate 88 are strip liquid. 116 is removed. If the stripping process continues, the stripping liquid 116 is contaminated by impurities generated in the photoresist pattern 112 and the deposition film 114 removed from the lower substrate 88, thereby decreasing the concentration of the stripping liquid 116. To this end, the first pump 108 circulates the strip liquid 116 filled in the cassette 102 to remove impurities that contaminate the strip liquid 116. That is, the strip liquid 116 filled in the cassette 102 is sent to the filter 110 to remove the aliquots contained in the strip liquid 116, and the strip liquid from which impurities are removed by passing through the filter 110 ( 116) is sent back into the cassette.

The ultrasonic generator 130 is to reduce the removal time of the photoresist pattern 112 and the deposition film 114 formed on the lower substrate 88 during the immersion strip process. The ultrasonic generator 130 generates ultrasonic waves and converts the generated ultrasonic waves into the stripper 101. To apply. When ultrasonic waves are applied to the stripper 101, the removal time of the photoresist pattern 112 and the deposition layer 114 removed on the lower substrate 88 by the strip liquid 116 is shortened.

Most patterns to be formed are formed on the lower substrate 88 after the immersion strip process. However, the immersion strip process alone does not completely remove the photoresist pattern 112 and the deposition layer 114 formed on the lower substrate 88. In addition, impurities such as particles of the photoresist pattern 112 and the deposition layer 114 may be generated on the lower substrate 88.

The spray strip part 150 is a plurality of sprays for spraying the photoresist pattern 112 and the deposition film 114 remaining on the lower substrate 88 after the immersion strip process, and the strip liquid 116 to remove impurities The tank (140) for supplying the nozzle 106, the strip liquid 116 injected by the plurality of injection nozzles 106, and the strip liquid 116 injected by the plurality of injection nozzles 106, the tank ( A second pump 128 for reducing to 140 and a second filter 120 for filtering the strip liquid 116 reduced by the second pump 128 to the tank 140.

The plurality of injection nozzles 106 receives the strip liquid 116 from the tank 140 in which the strip liquid 116 is stored and injects the strip liquid 116 onto the lower substrate 88. When the strip liquid 116 is sprayed onto the lower substrate 88, the photoresist pattern and the deposition film remaining on the lower substrate 88, and impurities are removed from the lower substrate 88 so that the lower substrate 88 is removed. A desired pattern 118 may be formed on the substrate 88.

The second pump 128 is a device for reducing the strip liquid 116 sprayed by the plurality of spray nozzles 106 to the tank 140. The strip liquid 116 sprayed by the plurality of spray nozzles 106. ) May be reduced to the tank 140 to reduce the amount of the strip liquid 116 used.

The second filter 120 filters the strip liquid 116 reduced to the tank 140 by the second pump 128 to remove impurities contained in the strip liquid 116, and removes the strip liquid from which the impurities are removed ( Reducing the 116 to the tank 140 may prevent the manufacturing apparatus 100 from being contaminated. In particular, the pipe flowing through the strip liquid 116 is prevented from being contaminated to prevent defects of the thin film transistor array substrate, thereby maintaining the efficiency of the strip process and preventing contamination of the manufacturing apparatus 100.

According to the first embodiment of the present invention, a manufacturing method using a manufacturing apparatus of a thin film transistor array substrate is obtained by removing most of the photoresist pattern 112 and the deposition film 114 formed on the lower substrate 88 through an immersion strip process. The pattern 118 is formed by removing the photoresist pattern 112 and the deposition layer 114 remaining on the lower substrate 88 through a spray strip process.

In the apparatus 100 for manufacturing a thin film transistor array substrate according to the first embodiment of the present invention, a plurality of lower substrates 88 are immersed in the cassette 102 on the lower substrate 88 during a strip process using a lift-off method. By reducing the removal time of the formed photoresist pattern 112 and the deposition film 114 to improve the productivity of the thin film transistor array substrate, and also reduce the production cost by reducing the amount of the strip liquid 116 used in the strip process. Can be. In addition, particles and impurities of the photoresist pattern 112 and the deposition layer 114 generated during the manufacturing process may be removed to prevent contamination of the manufacturing apparatus. This can reduce the defects of the thin film transistor array substrate.

In the apparatus for manufacturing a thin film transistor array substrate according to a second embodiment of the present invention, the manufacturing apparatus 100 according to the first embodiment of the present invention, the first injection strip portion for injecting the strip liquid, and the strip liquid at high pressure Except for the addition of an aqua knife, the detailed description is omitted since it has the same components as the manufacturing apparatus 100 according to the first embodiment of the present invention.

12 is a view showing a manufacturing apparatus of a thin film transistor array substrate according to a second embodiment of the present invention.

In the apparatus 200 for manufacturing a thin film transistor array substrate according to the second embodiment of the present invention shown in FIG. 12, an immersion strip in which a lower substrate 88 on which a photoresist pattern 112 and a deposition layer 114 are formed is immersed and stripped. The first injection strip part 250 for removing the portion 240 and the photoresist pattern 112 and the deposition layer 114 remaining on the lower substrate 88 through the immersion strip process by the immersion strip part 240. ), An aqua knife 270 spraying the strip liquid 216 at a high pressure on the lower substrate 88 through the first spray strip part 250, and a lower knife 88 on the lower substrate 88 through the aqua knife 270. And a second spray strip part 260 for removing the photoresist pattern 112 and the deposited film 114 remaining in the substrate.

The first spray strip part 250 includes a plurality of first spray nozzles 206 for spraying the strip liquid 216 on the lower substrate 88 and a strip liquid 216 for the plurality of first spray nozzles 206. The first tank 204 to supply and the 3rd filter 280 which filter the impurity contained in the strip liquid 216 reduced by the 1st pump 208 to the 1st tank 204 are provided.

The plurality of first injection nozzles 206 are supplied with the strip liquid 216 from the first tank 204 in which the strip liquid 216 is stored, so that the strip liquid 216 is transferred onto the lower substrate 88 which has been subjected to the immersion strip process. The photoresist pattern 112 and the deposition layer 114 on the lower substrate 88 that are not removed by the immersion strip process are removed by spraying.

The third filter 280 filters the strip liquid 216 reduced by the first pump 208 to the first tank 204 to remove impurities contained in the strip liquid 216 and removes impurities. The liquid 216 may be reduced to the first tank 204 to prevent the manufacturing apparatus 200 from being contaminated. In particular, the pipe flowing through the strip liquid 216 is prevented from being contaminated by impurities, thereby preventing defects of the thin film transistor array substrate, thereby maintaining efficiency of the strip process and preventing contamination of the manufacturing apparatus 200.

The lower substrate 88 that has passed through the first spray strip part 250 is subjected to a high pressure spray strip process by the aqua knife 270. The high pressure spray strip process removes the photoresist pattern 112 and the deposited film 114 remaining on the lower substrate 88 through the first spray strip process using the aqua knife 270.

The fourth filter 290 filters the strip liquid 216 supplied to the aqua knife 270 by the first pump 208 to remove impurities contained in the strip liquid 216 to contaminate the manufacturing equipment 200. Can be prevented. In particular, by preventing impurities from contaminating the pipe flowing the strip liquid 216 due to impurities to prevent defects of the thin film transistor array substrate to maintain the efficiency of the strip process and to prevent contamination of the manufacturing apparatus 200.

The second spray strip part 260 includes a plurality of second spray nozzles 226 for spraying the strip liquid 216 on the lower substrate 88 that has been subjected to the high pressure spray strip process by the aqua knife 270, and a plurality of second spray nozzles 226. Impurities contained in the second tank 224 supplying the strip liquid 216 to the 2 injection nozzles 226 and the strip liquid 216 reduced to the second tank 224 by the second pump 228 are removed. And a second filter 220 for filtering. The second spray strip portion 260 plays the same role as the spray strip portion 150 according to the first embodiment of the present invention illustrated in FIG. 9. As shown in FIG. 11, both the photoresist pattern 112 and the deposition layer 114 are removed on the lower substrate 88 that has undergone the second spray strip process by the second spray strip unit 260. ) Is formed.

The high pressure spray strip process and the second spray strip process remove the photoresist pattern 112 and the deposition layer 114 cleanly than in the general strip process, thereby removing the pattern 118 formed on the lower substrate 88 in the general strip process. It can be formed more perfectly.

According to the second embodiment of the present invention, a manufacturing method using the apparatus 200 for manufacturing a thin film transistor array substrate, most of the photoresist pattern 112 and the deposition film 114 formed on the lower substrate 88 through an immersion strip process. After the removal, the photoresist pattern 112 and the deposition layer 114 of the portion except for the pattern portion to be formed on the lower substrate 88 are removed through the first spray strip process and the high pressure spray strip process. Thereafter, the pattern 118 is formed by removing particles and impurities of the photoresist pattern remaining on the lower substrate 88 through the second spray strip process.

The apparatus 200 for manufacturing a thin film transistor array substrate according to the second embodiment of the present invention reduces the time for removing the photoresist pattern remaining on the protective film pattern during the strip process using the lift-off method, thereby improving productivity of the thin film transistor array substrate. In addition to improving, it is possible to reduce the production cost by reducing the amount of the strip liquid 216 used in the strip process. In addition, particles of the photoresist pattern generated during the manufacturing process may be removed to prevent contamination of the manufacturing apparatus. This can reduce the defects of the thin film transistor array substrate.

As described above, the apparatus and method for manufacturing a thin film transistor array substrate according to the embodiments of the present invention can manufacture a thin film transistor array substrate using only three masks using a lift off process, and the photoresist and transparent in the lift off process. The electrode can be quickly and completely removed and the production cost can be reduced by reducing the amount of stripping liquid used in the strip process. In addition, particles of the photoresist pattern generated during the manufacturing process may be removed to prevent contamination of the manufacturing apparatus. This can reduce the defects of the thin film transistor array substrate.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (15)

An immersion strip portion for immersing a plurality of substrates each having a photoresist and a transparent electrode laminated in a stripping liquid to simultaneously remove the photoresist and the transparent electrode formed on the plurality of substrates in a lift-off process; And a spray strip portion for injecting the strip liquid onto the photoresist and the transparent electrode remaining on the substrate which has passed through the immersion strip portion. The method of claim 1. The immersion strip part includes a stripper containing the strip liquid, a cassette receiving the plurality of substrates, a cassette immersed in strip liquid in the stripper, an ultrasonic wave generator generating ultrasonic waves and applying ultrasonic waves into the stripper, and strip liquid in the stripper. And a pump for discharging the impurity contained in the strip liquid discharged by the pump and a filter for supplying the filtered strip liquid to the stripper. The method of claim 1. The spray strip portion, A plurality of spray nozzles for spraying the strip liquid onto the substrate; A tank for supplying the stripping liquid to the plurality of injection nozzles; A pump for discharging the strip liquid injected from the plurality of injection nozzles; And a filter for filtering impurities in the strip liquid discharged by the pump and supplying the filtered strip liquid to the tank. The method of claim 1. The spray strip portion, A first spray strip portion for removing the photoresist and the transparent electrode remaining on the substrate by spraying strip liquid onto the substrate having passed through the immersion strip portion; A high pressure spray strip portion for spraying strip liquid at a high pressure on the substrate having passed through the first spray strip portion; And a second spray strip portion for injecting strip liquid onto the substrate that has passed through the high pressure spray strip portion. The method of claim 4. At least one of the first and second spray strip portions A plurality of spray nozzles for spraying the strip liquid onto the substrate; A tank for supplying the stripping liquid to the injection nozzle; A pump for discharging the strip liquid injected by the injection nozzle; And a filter for filtering impurities in the strip liquid discharged by the pump and supplying the filtered strip liquid to the tank. The method of claim 4. The high pressure spray strip part A high pressure injector for spraying the strip liquid at a high pressure; And a filter for filtering impurities in the strip liquid supplied to the high-pressure injector. The method of claim 6. The apparatus for manufacturing a thin film transistor array substrate, wherein the high pressure injector comprises an aqua knife. Immersing a plurality of substrates on which the photoresist and the transparent electrode are stacked in a stripping liquid, respectively, to simultaneously remove the photoresist and the transparent electrode formed on the plurality of substrates in a lift-off process; And spraying the strip liquid onto the photoresist and the transparent electrode remaining on the substrate after the first step. The method of claim 8. The first step is And dipping the cassette having the plurality of substrates mounted on the strip liquid. The method of claim 8. The method of manufacturing a thin film transistor array substrate further comprising the step of applying ultrasonic waves to the strip liquid immersed in the plurality of substrates. The method of claim 8. The second step is And spraying strip liquid onto the substrate through a plurality of spray nozzles. The method of claim 8. The second step, A first spray strip step of spraying strip liquid onto the substrate after the substrates are immersed in strip liquid; A high pressure spray strip step of spraying a strip liquid at a high pressure on the substrate subjected to the first spray strip step; And a second spray strip step of spraying strip liquid onto the substrate which has undergone the high pressure spray strip step. delete delete delete

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