KR100598264B1 - Printed Circuit Boards with Stacked Vias and Manufacturing Method Thereof - Google Patents

Abstract

The present invention relates to a printed circuit board having stacked vias in which the diameters of the via holes are different from each other so that the upper via is inserted into the lower via.

A printed circuit board having a stacked via according to the present invention includes a first insulating layer; A first circuit layer patterned on said first insulating layer; A second insulating layer formed on the first insulating layer and the first circuit layer; A second circuit layer patterned on the second insulating layer; A third insulating layer formed on the second insulating layer and the second circuit layer; A third circuit layer patterned on the third insulating layer; A first via formed through the second insulating layer and having a conductive plating layer formed at a predetermined thickness on an inner wall thereof to electrically connect the first circuit layer and the second circuit layer; And penetrate the third insulating layer to the lower conductive plating layer of the first via so that a lower portion is inserted into the first via. The first circuit layer, the second circuit layer, and the third circuit layer may be formed. And a second via having a conductive plating layer formed therein so as to be electrically connected thereto.

Via Hole, Stacked Via, Staggered Via, O-Ring Via, Printed Circuit Board

Description

Printed circuit board having stack type via and method for fabricating the same}

1 is a cross-sectional view of a printed circuit board having a stacked via stacked with two conventional vias.

2 is a cross-sectional view of a printed circuit board having stacked vias in which two vias are stacked according to an embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a printed circuit board having stacked vias in which two vias are stacked according to an embodiment of the present invention.

4 is a cross-sectional view of a printed circuit board having stacked vias in which three vias are stacked according to another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100, 200: printed circuit board

111, 112, 113, 211, 212, 213, 214: insulating layer

121, 122, 123, 221, 222, 223, 224: circuit layer

Via: 131, 132, 231, 232, 233

B1, B2: Via Hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board having a stack type via and a method for manufacturing the same. More particularly, the diameter of each via hole is different from each other so that the upper via is formed on the lower via. A printed circuit board having a stacked via inserted therein and a method of manufacturing the same.

As the trend of light and shortening of electronic products has recently accelerated, only the necessary circuit layers are connected by connecting only necessary circuit layers, not the plated through hole processing method implemented in a multi-layer printed circuit board. There is an increasing production of printed circuit boards that employ a build-up method that implements bonding.

The printed circuit board adopting the build-up method applies sequential lamination without mass lamination of the multilayer printed circuit board, and processes the insulating layer with a laser to form a circuit-to-layer bonding. By forming a via hole diameter of 0.15 mm or less, which could not be realized in a mechanical drill, the ball pad of the fine ball grid array (BGA) can be realized, the wiring density is increased through the interlayer connection, and the light and small size of electronic products is reduced. And contributes to performance improvement.

Vias formed on the printed circuit board to which the build-up method is applied include staggered type vias, O-ring type vias, and stack type vias. Among them, stacked vias that form vias on vias have been actively studied as one of the technologies applied to all printed circuit boards in the future.

1 is a cross-sectional view of a printed circuit board having a stacked via stacked with two conventional vias.

As shown in FIG. 1, a printed circuit board 10 having a stack-type via in which two conventional vias are stacked has a first insulating layer 11 and a first patterned pattern on the first insulating layer 11. The second insulating layer 12 formed on the circuit layer 21, the first insulating layer 11, and the first circuit layer 21, and the second circuit layer 22 patterned on the second insulating layer 12. ), The third insulating layer 13 formed on the second insulating layer 12 and the second circuit layer 22, the third circuit layer 23 patterned on the third insulating layer 13, and the first A first via 31 filled with copper plating inside the first via 31 filled with copper plating to electrically connect the circuit layer 21 and the second circuit layer 22, and the second circuit layer and the third circuit. It includes a second via 32 filled with copper plating to electrically connect the layers.

The above-described printed circuit board 10 having the stacked vias is electrically connected between the first circuit layer 21, the second circuit layer 22, and the third circuit layer 23 so that the degree of integration of the circuit may be increased. Improved.

However, the conventional printed circuit board 10 having the stacked vias has a narrow interface between the first via 31 and the second via 32, which is a portion A, which is indicated by a circular dotted line. Stress was concentrated at the interface (especially at the corners of the interface) of the first via 31 and the second via 32.

As a result, since the printed circuit board 10 having the stacked vias is easily cracked at the interface between the first via 31 and the second via 32, the electrical connection between the circuit layers is opened, and thus the There was a problem of lowering reliability.

The technical problem of the present invention for solving the above problems is to provide a printed circuit board having a stacked via which can ensure the reliability of the product by preventing cracks at the interface between the vias and a manufacturing method thereof.

In order to solve the above technical problem, a printed circuit board having a stacked via according to the present invention comprises a first insulating layer; A first circuit layer patterned on said first insulating layer; A second insulating layer formed on the first insulating layer and the first circuit layer; A second circuit layer patterned on the second insulating layer; A third insulating layer formed on the second insulating layer and the second circuit layer; A third circuit layer patterned on the third insulating layer; A first via formed through the second insulating layer and having a conductive plating layer formed at a predetermined thickness on an inner wall thereof to electrically connect the first circuit layer and the second circuit layer; And penetrate the third insulating layer to the lower conductive plating layer of the first via so that a lower portion is inserted into the first via. The first circuit layer, the second circuit layer, and the third circuit layer may be formed. And a second via having a conductive plating layer formed therein so as to be electrically connected thereto.

The material constituting the conductive plating layer of the printed circuit board having the stacked via according to the present invention is preferably selected from the group consisting of Cu, Au, Ni, Sn and alloys of the materials.

In order to solve the above technical problem, a method of manufacturing a printed circuit board having a stacked via according to the present invention (A) after forming a patterned first circuit layer on a first insulating layer, the first insulating layer And laminating a second insulating layer on the first circuit layer. (B) forming a first via hole penetrating the second insulating layer so as to be connected to the first circuit layer; (C) forming a first via by forming a conductive plating layer having a predetermined thickness on an inner wall of the first via hole, and forming a second circuit layer on the second insulating layer; (D) depositing a third insulating layer on the second insulating layer, the second circuit layer and the first via; (E) forming a second via hole penetrating the third insulating layer to the lower conductive plating layer of the first via so as to be connected to the first circuit layer and the second circuit layer; And (F) forming a second via by forming a conductive plating layer in the second via hole, and forming a third circuit layer on the third insulating layer.

The process of forming the first via hole of step (B) and the second via hole of step (E) of the method of manufacturing a printed circuit board having stacked vias according to the present invention may be performed by using a laser. It is preferable to form the via holes and the second via holes.

The process of forming the second circuit layer of step (C) and the third circuit layer of step (F) of the method of manufacturing a printed circuit board having a stacked via according to the present invention may be carried out using a subtractive method ( It is preferable to form using at least one of a subtractive process, a full additive process, and a semi-additive process.

The material constituting the conductive plating layer of the method of manufacturing a printed circuit board having a stacked via according to the present invention is preferably selected from the group consisting of Cu, Au, Ni, Sn and alloys of the materials.

Hereinafter, a printed circuit board having a stacked via according to the present invention and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of a printed circuit board having stacked vias in which two vias are stacked according to an embodiment of the present invention. In FIG. 2, one side of the printed circuit board is shown, but a stacked via is formed in which substantially two vias are stacked on both sides of the printed circuit board.

As shown in FIG. 2, a printed circuit board 100 having a stacked via in which two vias are stacked according to the present invention may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer. And a first circuit layer 121, a second circuit layer 122, a third circuit layer 123, a first via 131, and a second via 132.

The first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 serve to provide electrical insulation between the circuit layers 121, 122, and 123.

The first circuit layer 121, the second circuit layer 122, and the third circuit layer 123 serve as signal lines for transmitting electrical signals, and the first circuit layer 121 is the first insulating layer 111. Patterned on the second circuit layer 122 is patterned on the second insulating layer 112, and the third circuit layer 123 is patterned on the third insulating layer 113. . Here, it is preferable that the 1st circuit layer 121, the 2nd circuit layer 122, and the 3rd circuit layer 123 consist of a copper foil layer, a copper plating layer, etc.

The first via 131 is formed through the second insulating layer 112, and a conductive plating layer is formed on the inner wall to have a predetermined thickness so as to electrically connect the first circuit layer 121 and the second circuit layer 122. It is.

The second via 132 is formed through the third insulating layer 113 to the lower conductive plating layer of the first via 131 so that the lower portion is inserted into the first via 131, and the first circuit layer 121. ), And the inside is filled with a conductive plating layer to electrically connect the second circuit layer 122 and the third circuit layer 123.

In this case, Cu, Au, Ni, Sn, an alloy of the materials, or the like may be used as the material forming the conductive plating layer formed on the first via 131 and the second via 132, and Cu may be used.

As shown, the printed circuit board 100 having the stacked vias in which the two vias are stacked according to the present invention has a large interface between the first via 131 and the second via 132, and thus, is not affected by temperature change. The stress is distributed evenly across the interface. Thus, no crack occurs at the interface between the first via 131 and the second via 132.

3A to 3F are cross-sectional views illustrating a method of manufacturing a printed circuit board having stacked vias in which two vias are stacked according to an embodiment of the present invention. Although one side of the printed circuit board is shown here, it is substantially performed on both sides of the printed circuit board.

As shown in FIG. 3A, after the patterned first circuit layer 121 is formed on the first insulating layer 111, the second insulating layer is formed on the first insulating layer 111 and the first circuit layer 121. It warmed in the layer 112 (for example, a prepreg (prepreg)) after laminating a predetermined temperature and pressure (e.g., about 150 ℃ ~200 ℃ and ^{30kg / cm 2 ~40kg / cm 2} ) and Pressurize.

Here, the first insulating layer 111 and the first circuit layer 121 may use a copper foil laminated plate coated with a copper foil layer on both sides of the insulating resin layer. In this case, the insulating resin layer corresponds to the first insulating layer 111, and the copper foil layer patterned on one surface of the insulating resin layer corresponds to the first circuit layer 121.

As shown in FIG. 3B, a first via hole B1 penetrating the second insulating layer 112 is formed by using a laser so as to be connected to the first circuit layer 121.

The laser may be a YAG laser (Yttrium Aluminum Garnet laser) and a carbon dioxide laser (CO ₂ laser).

In a preferred embodiment, after the first via hole B1 is formed by laser processing, the first insulating layer 111 melts due to heat generated when the first via hole B1 is formed, and is generated on the inner wall of the first via hole B1. It is preferable to further perform a desmear process to remove smear.

As shown in FIG. 3C, a conductive plating layer is formed on an inner wall of the first via hole B1 to a predetermined thickness to form a first via 131, and a circuit pattern forming process is performed on the second insulating layer 112. The second circuit layer 122 is formed to a predetermined thickness.

Here, since the second insulating layer 112 is exposed on the inner wall of the first via hole B1, the conductive plating layer preferably forms an electroless plating layer, and then forms an electrolytic plating layer.

In the process of forming the second circuit layer 122, the subtractive method of forming the second circuit layer 122 after forming the conductive plating layer on the inner walls of the second insulating layer 112 and the first via hole B1 ( A subtractive process may be used, and a full additive process or a semi-additive process may be used to form the second circuit layer 122 in the process of forming the conductive plating layer.

As shown in FIG. 3D, after laminating the third insulating layer 113 (eg, prepreg) on the second insulating layer 112, the second circuit layer 122, and the first via 131, Heat and pressurize at a predetermined temperature and pressure (eg, about 150 ° C. to 200 ° C. and 30 kg / cm ^{2 to} 40 kg / cm ² ).

As shown in FIG. 3E, the first penetrating layer 113 penetrates the third insulating layer 113 to the lower conductive plating layer of the first via 131 by using a laser to be connected to the first circuit layer 121 and the second circuit layer 122. 2 via holes B2 are formed.

The laser may be a YAG laser, a carbon dioxide laser and the like.

In addition, it is preferable to perform a desmear process of removing the smear generated on the inner wall of the second via hole B2 due to the heat generated when the second via hole B2 is formed.

As shown in FIG. 3F, a conductive plating layer is formed in the second via hole B2 to form the second via 132, and a circuit pattern forming process is performed to form a third circuit layer on the third insulating layer 113. 123 is formed.

Since the third insulating layer 113 is exposed on the inner wall of the second via hole B2, the conductive plating layer is preferably formed by forming an electroless plating layer thinly and then forming an electrolytic plating layer.

In addition, a process of forming the second circuit layer 122 may use a subtractive process, a full additive process, or a semi-additive process.

On the other hand, in another embodiment according to the present invention, by repeatedly performing the manufacturing method of the printed circuit board having the stacked vias of FIGS. 3A to 3F, printing having stacked vias in which three or more vias are stacked. A circuit board can be manufactured.

4 is a cross-sectional view of a printed circuit board having stacked vias in which three vias are stacked according to another embodiment of the present invention. In FIG. 4, one side of the printed circuit board is shown, but stacked vias are formed in which three vias are substantially stacked on both sides of the printed circuit board.

As shown in FIG. 4, the printed circuit board 200 having the stacked vias in which three vias are stacked according to the present invention includes a first insulating layer 211, a second insulating layer 212, and a third insulating layer. 213, fourth insulating layer 214, first circuit layer 221, second circuit layer 222, third circuit layer 223, fourth circuit layer 224, and first via 231. And a second via 232 and a third via 233.

The first insulating layer 211, the second insulating layer 212, the third insulating layer 213, and the fourth insulating layer 214 serve to provide electrical insulation between the circuit layers.

The first circuit layer 221, the second circuit layer 222, the third circuit layer 223, and the fourth circuit layer 224 serve as signal lines for transmitting electrical signals, and the first circuit layer 221. Is patterned on the first insulating layer 211, the second circuit layer 222 is patterned on the second insulating layer 212, and the third circuit layer 223 is formed on the third insulating layer ( Patterned on 213, and the fourth circuit layer 224 is patterned on the fourth insulating layer 214. Here, it is preferable that the 1st circuit layer 221, the 2nd circuit layer 222, the 3rd circuit layer 223, and the 4th insulating layer 214 consist of a copper foil layer, a copper plating layer, etc.

The first via 231 is formed through the second insulating layer 212, and a conductive plating layer is formed on the inner wall to have a predetermined thickness to electrically connect the first circuit layer 221 and the second circuit layer 222. It is.

The second via 232 is formed through the third insulating layer 213 to the lower conductive plating layer of the first via 231 so that the lower portion is inserted into the first via 231, and the first circuit layer 221. ), The conductive plating layer is formed on the inner wall to a predetermined thickness so as to electrically connect the second circuit layer 222 and the third circuit layer 223.

The third via 233 is formed through the fourth insulating layer 214 to the lower conductive plating layer of the second via 232 so that the lower portion is inserted into the second via 232, and the first circuit layer 221. ), The second circuit layer 222, the third circuit layer 223 and the fourth circuit layer 224 is filled with a conductive plating layer inside to electrically connect.

The conductive plating layer formed on the first via 231, the second via 232, and the third via 233 may be formed of Cu, Au, Ni, Sn, an alloy thereof, and the like. It is preferable to use Cu.

As shown, a printed circuit board 200 having a stacked via in which three vias are stacked according to the present invention includes a boundary between a first via 231 and a second via 232 and a second via 232. Since the interface between the and the third via 233 is wide, the stress due to temperature change is evenly distributed on the interfaces. Accordingly, cracks do not occur at the interface between the first via 231 and the second via 232 and at the interface between the second via 232 and the third via 233.

Although the present invention has been described above, this is only one embodiment, and it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. . However, it will be confirmed through the claims that such changes and modifications fall within the scope of the present invention.

As described above, the printed circuit board having the stacked vias according to the present invention and the method of manufacturing the same have different diameters of the respective via holes, so that the upper vias are inserted into the lower vias so that the interface between the vias is wide. There is an effect that the crack does not occur at the interface between the vias.

In addition, the printed circuit board having the stacked vias according to the present invention and the manufacturing method thereof do not cause cracks between the vias, thereby improving the reliability of the product.

In addition, a printed circuit board having a stacked via according to the present invention and a method of manufacturing the same are electrically connected to various circuit layers through the stacked via, and thus, the degree of integration of the circuit is improved to provide a high density printed circuit board. have.

Claims (6)

A first insulating layer; A first circuit layer patterned on said first insulating layer; A second insulating layer formed on the first insulating layer and the first circuit layer; A second circuit layer patterned on the second insulating layer; A third insulating layer formed on the second insulating layer and the second circuit layer; A third circuit layer patterned on the third insulating layer; A first via formed through the second insulating layer and having a conductive plating layer formed at a predetermined thickness on an inner wall thereof to electrically connect the first circuit layer and the second circuit layer; And A lower conductive plating layer of the first via penetrates through the third insulating layer to insert a lower portion into the first via, and electrically connects the first circuit layer, the second circuit layer, and the third circuit layer. And a second via having a conductive plating layer formed therein so as to be connected to the printed circuit board. The method of claim 1, The material of the conductive plating layer is a printed circuit board having a stacked via, characterized in that selected from the group consisting of Cu, Au, Ni, Sn and alloys of the materials. (A) forming a patterned first circuit layer on the first insulating layer, and then laminating a second insulating layer on the first insulating layer and the first circuit layer; (B) forming a first via hole penetrating the second insulating layer so as to be connected to the first circuit layer; (C) forming a first via by forming a conductive plating layer having a predetermined thickness on an inner wall of the first via hole, and forming a second circuit layer on the second insulating layer; (D) depositing a third insulating layer on the second insulating layer, the second circuit layer and the first via; (E) forming a second via hole penetrating the third insulating layer to the lower conductive plating layer of the first via so as to be connected to the first circuit layer and the second circuit layer; And (F) forming a conductive via layer in the second via hole to form a second via, and forming a third circuit layer on the third insulating layer. Method of manufacturing a printed circuit board. The method of claim 3, wherein In the forming of the first via hole of step (B) and the second via hole of step (E), the first via hole and the second via hole are formed using a laser, respectively. A method of manufacturing a printed circuit board. The method of claim 3, wherein The process of forming the second circuit layer of step (C) and the third circuit layer of step (F) is carried out in a subtractive process, a full additive process and a semiadditive. A method for manufacturing a printed circuit board with stacked vias, characterized in that it is formed using at least one of a semi-additive process. The method of claim 3, wherein The material of the conductive plating layer is Cu, Au, Ni, Sn and a method of manufacturing a printed circuit board having a stacked via, characterized in that selected from the group consisting of alloys thereof.

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