KR100596885B1 - Series Diode Cells and Nonvolatile Memory Devices Using the Same - Google Patents

Abstract

The present invention relates to a series diode cell and a nonvolatile memory device using the same, and discloses a technique for reducing the number of cell arrays by forming a multi-layer cell array including a nonvolatile ferroelectric capacitor and a series diode cell. The present invention provides a bit line on top of an interlayer insulating film, a series PN diode chain switch on top of a bit line, a nonvolatile ferroelectric capacitor on top of a series PN diode chain switch, and an interlayer insulating film. In this way, the series diode cell array can be configured in multiple layers to reduce the overall chip size.

Description

Serial diode cell and non-volatile memory device using the same

1 is a unit cell configuration diagram of a series diode cell according to the present invention.

2 is a unit cell cross-sectional view of the series diode cell of FIG.

3 is a plan view of a bit line of the series diode cell of FIG.

4 is a plan view of the series diode cell of FIG.

5 is a cross-sectional view of a series diode cell of FIG.

6 is a view for explaining the operation of the series diode switch of FIG.

7 is a block diagram of a nonvolatile memory device using a series diode cell according to the present invention.

FIG. 8 is a layout diagram of the series diode cell array of FIG. 7. FIG.

9 is a detailed circuit diagram of the series diode cell array of FIG.

10 is a detailed circuit diagram of the sense amplifier of FIG.

11 is a timing diagram of an operation in a read mode of a nonvolatile memory device using a series diode cell according to the present invention;

12 is a timing diagram of an operation in a write mode of a nonvolatile memory device using a series diode cell according to the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a series diode cell and a nonvolatile memory device using the same, and to reduce the number of cell arrays by forming a multi-layer cell array including a nonvolatile ferroelectric capacitor and a series diode cell.

In general, the nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about DRAM (DRAM) and is attracting attention as a next-generation memory device due to its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FeRAM and its operation will be omitted.

The unit cell of the conventional nonvolatile ferroelectric memory device includes one switching element connecting a sub bit line and a nonvolatile ferroelectric capacitor by switching according to a state of a word line, and one connected between one end of the switching element and a plate line. Of nonvolatile ferroelectric capacitors.

Here, the switching element of the conventional nonvolatile ferroelectric memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

However, when the cell array is implemented using the NMOS transistor as a switching device, there is a problem in that the overall chip size is increased. Accordingly, as described above, a cross point cell is implemented by using a nonvolatile ferroelectric memory device having nonvolatile characteristics and a series diode switch that does not need a separate gate control signal, and the cross point cell and a circuit element region for controlling the same. There is a need for the present invention to efficiently reduce the size of the overall chip.

The present invention has been made to solve the above problems and has the following object.

First, the purpose of the present invention is to improve the process efficiency by forming a bit line on the interlayer insulating film, stacking a series diode switch on top of the bit line, and stacking a nonvolatile ferroelectric capacitor on the top of the series diode switch. .

Secondly, the purpose of the present invention is to reduce the overall size of the nonvolatile memory by arranging a series diode cell array in a multi-layer and a circuit element region under the interlayer insulating film.

The serial diode cell of the present invention for achieving the above object is at least two or more connected to both ends of the bit line formed on top of the insulating layer and the bit line contact node, serially connected to the top of the bit line contact node A series diode switch having a diode element; A nonvolatile ferroelectric capacitor having a top electrode, a ferroelectric layer, and a bottom electrode to read / write data corresponding to the magnitude of current applied from a word line or a bit line; And a unit series diode cell having a contact node connecting a common node and a bottom electrode to which two or more diode elements are connected.

In addition, a nonvolatile memory device using a series diode cell of the present invention includes a plurality of series diode cell arrays each including a plurality of series diode cells arranged in a row and column direction and stacked in a multilayer structure and separated from each other by an insulating layer. ; A plurality of word line drivers selectively driving word lines of the plurality of series diode cell arrays; And a plurality of sense amplifiers for sensing and amplifying data applied from the plurality of series diode cell arrays, each of the plurality of series diode cells having a bit line formed over the insulating layer; A series diode switch connected to both ends of the bit line through a bit line contact node, the series diode switch having at least two diode elements connected in series with the upper portion of the bit line contact node; A nonvolatile ferroelectric capacitor having a top electrode, a ferroelectric layer, and a bottom electrode to read / write data corresponding to the magnitude of current applied from a word line or a bit line; And a contact node connecting the common node and the bottom electrode to which two or more diodes are connected.

In addition, a nonvolatile memory device using a series diode cell of the present invention, a plurality of series diode cell array including a plurality of unit series diode cells arranged in a row and column direction; A circuit element region formed on a silicon substrate provided under the plurality of series diode cell arrays to drive control the plurality of series diode cell arrays; And an insulating layer formed between the plurality of series diode cell arrays and the circuit element regions to insulate the plurality of series diode cell arrays and the circuit element regions from each other, each of the plurality of series diode cells having a bit line formed over the insulating layer. ; A series diode switch connected to both ends of the bit line through a bit line contact node, the series diode switch having at least two diode elements connected in series with the upper portion of the bit line contact node; A nonvolatile ferroelectric capacitor having a top electrode, a ferroelectric layer, and a bottom electrode to read / write data corresponding to the magnitude of current applied from a word line or a bit line; And a contact node connecting the common node and the bottom electrode to which two or more diodes are connected.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a block diagram of a unit series diode cell according to the present invention.

The unit series diode cell includes one nonvolatile ferroelectric capacitor FC and one series diode switch 10. Here, the series diode switch 10 includes a PNPN diode switch 11 and a PN diode switch 12. The PNPN diode switch 11 and the PN diode switch 12 are connected in parallel between the bottom electrode of the nonvolatile ferroelectric capacitor FC and the bit line BL.

The PNPN diode switch 11 is connected in a reverse direction between one electrode of the nonvolatile ferroelectric capacitor FC and the bit line BL, and the PN diode switch 12 is connected in a forward direction between one electrode of the nonvolatile ferroelectric capacitor FC and the bit line BL. do. The other electrode of the nonvolatile ferroelectric capacitor FC is connected to the word line WL.

FIG. 2 is a cross-sectional view of the series diode cell of FIG. 1.

In the series diode switch 10, an insulating layer 31 made of SiO 2 is formed on the silicon substrate 30, and a bit line BL is stacked on the insulating layer 31. The silicon layer 32 is formed on the bit line BL through the bit line contact node BLCN. The silicon layer 32 is formed by stacking a PNPN diode switch 11 and a PN diode switch 12 made of growth silicon or polysilicon and connected in series.

In the PNPN diode switch 11, the P-type region and the N-type region are alternately connected in series, and in the PN diode switch 12, the P-type region is formed adjacent to the N-type region of the PNPN diode switch 11.

The bit line BL is formed through the bit line contact node BLCN under the N-type region of the PN diode switch 12 and the P-type region of the PNPN diode switch 11. In addition, the P-type region of the PN diode switch 12 and the N-type region of the PNPN diode switch 11 are connected to the bottom electrode 22 of the nonvolatile ferroelectric capacitor FC through the common contact node CN.

Accordingly, the present invention forms a series diode switch 10 between the bit line BL and the nonvolatile ferroelectric capacitor FC so that the bit line BL and the nonvolatile ferroelectric capacitor FC do not have a fair influence on each other.

Here, the nonvolatile ferroelectric capacitor FC includes a top electrode 20, a ferroelectric layer 21, and a bottom electrode 22. The top electrode 20 of the nonvolatile ferroelectric capacitor FC is connected to the word line WL.

3 is a plan view of the bit line BL and the insulating layer 31 of FIG. 2.

It can be seen that the series diode cell forms a bit line BL electrode, which is a nano scale conductor wire, on the insulating layer 31.

4 is a plan view of a series diode cell according to the present invention.

In the series diode switch 10, the PNPN diode switch 11 and the PN diode switch 12 made of the silicon layer 32 are continuously connected in series chain form. That is, one series diode cell has a PN diode switch 12 and a PNPN diode switch 11 connected in series. In the series diode cell adjacent to the same direction as one series diode cell, the PN diode switch 12 and the PNPN diode switch 11 are connected in series.

In addition, the series diode switch 10 is arranged in a plurality of layers with the insulating layer 31 interposed therebetween, and each of the upper series diode switch 10 and the lower series diode switch 10 is separated through the insulating layer 31. It is. Each silicon layer 32 is insulated from the upper and lower portions through the insulating layer 31.

Accordingly, one PN diode switch 12 and one PNPN diode switch 11 are sequentially selected among the diode elements connected in series to form one series diode cell region.

In the series diode switch 10, the P-type region of the PN diode switch 12 and the N-type region of the PNPN diode switch 11 are formed adjacent to each other so as to be commonly connected to the contact node CN of the nonvolatile ferroelectric capacitor FC. .

In addition, the N-type region of the PN diode switch 12 and the P-type region of the PNPN diode switch 11 are connected to the bitline BL through the bitline contact node BLCN. The bitline contact node BLCN is commonly connected with the bitline contact node BLCN of the neighboring series diode cell. That is, the same bit line contact node BLCN is commonly connected to the P-type region of the PNPN diode switch 11 and the N-type region of the PN diode switch 12 of the neighboring cell.

In addition, a word line WL is formed on the nonvolatile ferroelectric capacitor FC.

The series diode cell having such a structure forms a bit line BL electrode, which is a nano scale conductor wire, on the insulating layer 31. The bit line contact node BLCN is formed at a portion connecting the series diode switch 10 and the bit line BL, and then the series diode switch 10 of the series PN diode chain structure is formed. Accordingly, the N-type region of the PN diode switch 12 and the P-type region of the PNPN diode switch 11 are connected to the bit line contact node BLCN.

Thereafter, a contact node CN is formed on the series diode switch 10 and connected to the bottom electrode 22 of the nonvolatile ferroelectric capacitor FC. The upper top electrode 20 itself of the nonvolatile ferroelectric capacitor FC operates as word line WL.

5 is a cross-sectional configuration diagram of a series diode cell according to the present invention forming a multilayer structure.

According to the present invention, the series diode cell array 40 is disposed in a multi-layer, based on the insulating layer 31. That is, the series diode cell array 40 is formed as a first cell array, and a second layer cell array is stacked in a multi-layer structure on top of the first cell array. Here, an insulating layer 31 is deposited on the nonvolatile ferroelectric capacitor FC formed on the first layer cell array to insulate and separate the first cell array and the second cell array.

The unit cell C includes a series diode switch 10 including a PN diode switch 12 and a PNPN diode switch 11, a word line WL, a bit line BL, and a nonvolatile ferroelectric capacitor FC.

In addition, a plurality of circuit element regions 150 for driving the series diode cell array 40 are disposed in the lower silicon substrate 30 based on the insulating layer 31. Here, the circuit element region 150 includes a word line driver, a sense amplifier, a data bus, a main amplifier, a data buffer, an input / output port, and the like. The series diode cell array 40 and the circuit element region 30 are insulated and separated based on the insulating layer 31.

6 is a view for explaining the operation of the series diode switch 10 of FIG.

Based on the nonvolatile ferroelectric capacitor FC, when the applied voltage of the bit line BL increases in the positive direction, the series diode switch 10 is kept off at the operating voltage Vo due to the operating characteristic of the PNPN diode switch 11. No current flows

Subsequently, when the applied voltage of the bit line BL is further increased to reach the threshold voltage Vc, the PNPN diode switch 11 is turned on and the series diode switch 10 is turned on according to the forward operation characteristic of the diode, thereby rapidly increasing the current. . At this time, the value of the current I consumed when the applied voltage of the bit line BL is greater than or equal to the threshold voltage Vc is due to the value of a resistor (not shown) connected to the bit line BL and serving as a load.

After the PNPN diode switch 11 is turned on, even a small voltage Vs is applied to the bit line BL, so that a large amount of current can flow. At this time, the PN diode switch 12 is maintained in the off state by the reverse operating characteristics.

On the other hand, when the applied voltage of the bit line BL increases in the negative direction, that is, when a constant voltage is applied to the word line WL, based on the nonvolatile ferroelectric capacitor FC, the forward operating characteristics of the PN diode switch 12 are affected. As a result, the series diode switch 10 is turned on so that current flows at any operating voltage. At this time, the PNPN diode switch 11 maintains the off state due to the reverse operation characteristic.

7 is a configuration diagram of a nonvolatile memory device using a series diode cell according to the present invention.

The present invention provides a plurality of series diode cell arrays 40, a plurality of word line drivers 50, a plurality of sense amplifiers 60, a data bus 70, a main amplifier 80, a data buffer 90 and input / output. It has an output port 100.

Each series diode cell array 40 has a plurality of unit series diode cells having a structure as shown in FIG. 1 in a row and column direction. The plurality of word lines WLs arranged in the row direction are connected to the word line driver 50. The plurality of bit lines BL arranged in the column direction are connected to the sense amplifier 60.

Here, one series diode cell array 40 is connected in correspondence with one word line driver 50 and one sense amplifier 60.

The plurality of sense amplifiers 60 share one data bus 70. The data bus 70 is connected to the main amplifier 80, and the main amplifier 80 amplifies data applied from each sense amplifier 60 through the data bus 70.

The data buffer 90 buffers and outputs amplified data applied from the main amplifier 80. The input / output port 100 outputs output data applied from the data buffer 90 to the outside, or applies input data applied from the outside to the data buffer 90.

FIG. 8 is a layout diagram of the series diode cell array 40 of FIG. 7.

In the series diode cell array 40, a plurality of word lines WL are arranged in a row direction, and a plurality of bit lines BL are arranged in a column direction, respectively. In addition, since the unit cell C is positioned only in an area where the word line WL and the bit line BL cross each other, a cross point cell that does not require an additional area may be implemented.

Here, the cross point cell does not include an NMOS transistor device using a separate word line WL gate control signal. In addition, the nonvolatile ferroelectric capacitor FC may be directly positioned at the intersection of the bit line BL and the word line WL by using the series diode switch 10 having two connection electrode nodes.

9 is a detailed circuit diagram of the series diode cell array 40 of FIG.

In the series diode cell array 40, a plurality of word lines WL <0> to WL <n> are arranged in a row direction, and a plurality of bit lines BL <0> to BL <m> are arranged in a column direction, respectively. The unit cell C is located only in an area where the word line WL and the bit line BL cross each other. Here, one unit cell C includes a nonvolatile ferroelectric capacitor FC and a series diode switch 10.

A plurality of sense amplifiers 60 are connected to each bit line BL in a one-to-one correspondence. Each sense amplifier 60 amplifies the result of comparing the voltage applied from the bit line BL with a predetermined reference voltage REF at the time of activation of the sense amplifier enable signal SEN.

In addition, the bit line pull-down element N1 is connected to the bit line BL <0>, and the bit line pull-down element N2 is connected to the bit line BL <m>. Accordingly, when the bit line pull-down signal BLPD is activated, the ground voltage is applied to the bit line BL to pull down the bit line BL to the ground level.

The series diode cell array 40 of this structure allows each nonvolatile ferroelectric capacitor FC to store one data.

FIG. 10 is a detailed circuit diagram illustrating the sense amplifier 60 of FIG. 7.

The sense amplifier 60 includes an amplifier 61 and a column select switch 62.

Here, the amplifier 61 includes PMOS transistors P1 to P3 and NMOS transistors N1 to N3. The PMOS transistor P1 is connected between the power supply voltage terminal and the common source terminal of the PMOS transistors P2 and P3 so that the sense amplifier enable signal SEP is applied through the gate terminal. The PMOS transistors P2 and P3 are connected in a cross-coupled structure to latch the power supply voltage applied through the PMOS transistor P1.

The NMOS transistor N5 is connected between the ground voltage terminal and the common source terminal of the NMOS transistors N3 and N4 so that the sense amplifier enable signal SEN is applied through the gate terminal. The NMOS transistors N3 and N4 are connected in a cross-coupled structure to latch the ground voltage applied through the NMOS transistor N5.

Here, the sense amplifier enable signal SEN and the sense amplifier enable SEP are signals having opposite phases, and the amplification unit 61 operates when the sense amplifier enable signal SEN is activated. One output terminal of the amplifier 61 is connected to the bit line BL <m> and the other output terminal is connected to the reference voltage REF applying terminal.

In addition, the column select switching unit 62 includes NMOS transistors N6 and N7. The NMOS transistor N6 is connected between the bit line BL <m> and the data bus 70 to control input / output of the data / D according to the column select signal CS <n> applied through the gate terminal. The NMOS transistor N7 is connected between the reference voltage REF applying terminal and the data bus 70 to control the input and output of the data D according to the column select signal CS <n> applied through the gate terminal.

15 is a timing diagram of an operation in a read mode of a nonvolatile memory device using a series diode cell according to the present invention.

First, in the t0 period, the bit line pull-down signal BLPD is activated to apply the ground voltage to the bit line pair BL to precharge the bit line BL to the ground level.

Subsequently, when the word line WL transitions high when the t1 section enters, and a constant voltage is applied to the word line WL, the PN diode switch 12 of the series diode switch 10 is turned on. Accordingly, the data of the series diode cell is transferred to the bit line BL. At this time, the bit line pull-down signal BLPD transitions to low.

Next, in the period t2, the sense amplifier enable signal SEN is activated to amplify the data carried on the bit line BL. Further, when the voltage of the bit line BL is amplified to the low level while the voltage level of the word line WL is high, the data " 0 "

Thereafter, in the period t3, the voltage of the word line WL transitions to a negative voltage which is a value less than or equal to the threshold voltage Vc. That is, the difference between the low voltage level of the bit line BL and the negative voltage level of the word line WL does not reach the state of the threshold voltage Vc for turning on the PNPN diode switch 11 of the series diode switch 10.

However, according to the difference between the high amplification voltage of the bit line BL and the negative voltage of the word line WL, a voltage higher than or equal to the threshold voltage Vc for turning on the PNPN diode switch 11 is applied. As a result, the PNPN diode switch 11 is turned on, and data "1" is restored in the series diode cell.

In this case, after the PNPN diode switch 11 is turned on, a large amount of current may flow even when a small voltage Vs is applied to the bit line BL, as shown in the operation characteristic of FIG. 9. Therefore, even if the voltage of the word line WL rises from the negative voltage to the low state again in the period t3, the current can sufficiently flow.

In addition, when the column select signal CS transitions high in the period t3, the NMOS transistors N6 and N7 of the column select switch 62 are turned on, and the data D and / D loaded on the bit line BL are output to the data bus 70 and serialized. Data stored in the diode cell C can be read.

12 is a timing diagram of an operation in a write mode of a nonvolatile memory device using a series diode cell according to the present invention.

First, in the t0 period, the bit line pull-down signal BLPD is activated to apply the ground voltage to the bit line pair BL to precharge the bit line BL to the ground level.

Subsequently, if the word line WL transitions high when entering the t1 section, the data of the series diode cell is transferred to the bit line BL. At this time, the bit line pull-down signal BLPD transitions to low. Then, new data D, / D to be written through the data bus 70 is input to the bit line BL.

Next, in the period t2, the sense amplifier enable signal SEN is activated to amplify the data carried on the bit line BL. Further, when the voltage of the bit line BL is amplified to the low level while the voltage level of the word line WL is high, data " 0 "

At this time, when the column select signal CS transitions high, the NMOS transistors N6 and N7 of the column select switch 62 are turned on and the data D and / D input through the data bus 70 are applied to the bit line BL. .

Thereafter, in the period t3, the voltage of the word line WL transitions to a negative voltage. That is, the difference between the low voltage level of the bit line BL and the negative voltage level of the word line WL does not reach the state of the threshold voltage Vc for turning on the PNPN diode switch 11 of the series diode switch 10.

However, according to the difference between the high amplification voltage of the bit line BL and the negative voltage of the word line WL, a voltage higher than or equal to the threshold voltage Vc for turning on the PNPN diode switch 11 is applied. As a result, the PNPN diode switch 11 is turned on and data " 1 " is written to the series diode cell.

As described above, the present invention has described a memory device for storing data as a nonvolatile ferroelectric memory device as an embodiment thereof, but the present invention is not limited thereto. It may be done.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

As described above, the present invention provides the following effects.                     

First, a bit line is formed on the interlayer insulating layer, a series diode cell is stacked on the bit line, and a nonvolatile ferroelectric capacitor is stacked on the series diode cell to improve process efficiency.

Secondly, a series diode cell array is arranged in a multi-layer on the upper side of the interlayer insulating film, and a circuit element region is disposed on the lower side to reduce the overall size of the nonvolatile memory.

Claims (16)

A series diode switch connected to both ends of a bit line formed on the insulating layer and a bit line contact node, the series diode switch having at least two diode elements connected in series with the bit line contact node; A nonvolatile ferroelectric capacitor having a top electrode, a ferroelectric layer, and a bottom electrode to read / write data corresponding to the magnitude of the current applied from the word line or the bit line; And And a unit series diode cell having a common node connected between the two or more diode elements and a contact node connecting the bottom electrode. 2. The series diode cell of claim 1, wherein the unit series diode cell is provided in plural in the row and column directions, and the plurality of unit series diode cells are stacked in a multilayer structure and separated from each other by the insulating layer. 3. The series diode cell of claim 1 or 2, wherein the series diode switch alternately series-connects a plurality of PNPN diode switches and the plurality of PN diode switches to form a continuous diode chain. 4. The series diode cell of claim 3, wherein the bit line contact node is connected to a P-type region of the plurality of PNPN diode switches and an N-type region of the plurality of PN diode switches, respectively. 4. The series diode cell of claim 3, wherein the contact node is formed at the common node to which the N-type regions of the plurality of PNPN diode switches and the P-type regions of the plurality of PN diode switches are connected. A plurality of series diode cell arrays each arranged in a row and column direction and stacked in a multi-layer structure, the plurality of series diode cells each separated from each other by an insulating layer; A plurality of word line drivers selectively driving word lines of the plurality of series diode cell arrays; And And a plurality of sense amplifiers for sensing and amplifying data applied from the plurality of series diode cell arrays. Each of the plurality of series diode cells A bit line formed on the insulating layer; A series diode switch connected to both nodes of the bit line through a bit line contact node, the series diode switch having at least two diode elements connected in series with the bit line contact node; A nonvolatile ferroelectric capacitor having a top electrode, a ferroelectric layer, and a bottom electrode to read / write data corresponding to the magnitude of the current applied from the word line or the bit line; And And a contact node connecting the common node to which the at least two diode elements are connected and the bottom electrode. The method of claim 6, A data bus shared by the plurality of sense amplifiers; A main amplifier for amplifying data applied from the data bus; A data buffer for buffering amplified data applied from the main amplifier; And And an input / output port configured to output the output data applied from the data buffer to the outside or to apply the input data applied from the outside to the data buffer. The method of claim 6 or 7, wherein each of the plurality of series diode cell array, A plurality of series diode cells positioned in an intersection region between a plurality of word lines and a plurality of bit lines arranged in row and column directions, respectively; And And a plurality of bit line pull-down elements connected one-to-one to the plurality of bit lines, respectively. The method of claim 6 or 7, wherein the series diode switch A PN diode switch connected forward between the bottom electrode of the nonvolatile ferroelectric capacitor and the bit line; And And a PNPN diode switch connected in a reverse direction between the bottom electrode of the nonvolatile ferroelectric capacitor and the bit line. The nonvolatile memory device of claim 9, wherein the P-type region of the PN diode switch is connected to the bottom electrode, and the N-type region is connected to the bit line. The nonvolatile memory device of claim 9, wherein an upper N-type region of the PNPN diode switch is connected to the bottom electrode, and a lower P-type region is connected to the bit line. A plurality of series diode cell arrays comprising a plurality of unit series diode cells arranged in a row and column direction; A circuit element region formed on a silicon substrate disposed below the plurality of series diode cell arrays to control driving of the plurality of series diode cell arrays; And An insulating layer formed between the plurality of series diode cell arrays and the circuit element region to insulate the plurality of series diode cell arrays and the circuit element region from each other, Each of the plurality of unit series diode cells A bit line formed on the insulating layer; A series diode switch connected to both nodes of the bit line through a bit line contact node, the series diode switch having at least two diode elements connected in series with the bit line contact node; A nonvolatile ferroelectric capacitor having a top electrode, a ferroelectric layer, and a bottom electrode to read / write data corresponding to the magnitude of the current applied from the word line or the bit line; And And a contact node connecting the common node to which the at least two diode elements are connected and the bottom electrode. The method of claim 12, wherein the series diode switch A PN diode switch connected in a forward direction between the bottom electrode of the nonvolatile ferroelectric capacitor and the bit line; And And a PNPN diode switch connected in a reverse direction between the bottom electrode of the nonvolatile ferroelectric capacitor and the bit line. The nonvolatile memory device of claim 13, wherein the P-type region of the PN diode switch is connected to the bottom electrode, and the N-type region is connected to the bit line. The nonvolatile memory device of claim 13, wherein an upper N-type region of the PNPN diode switch is connected to the bottom electrode, and a lower P-type region is connected to the bit line. 13. The circuit device of claim 12, wherein the circuit element region is A plurality of word line drivers selectively driving word lines of the plurality of series diode cell arrays; A plurality of sense amplifiers for sensing and amplifying data applied from the plurality of series diode cell arrays; A data bus shared by the plurality of sense amplifiers; A main amplifier for amplifying data applied from the data bus; A data buffer for buffering amplified data applied from the main amplifier; And And an input / output port configured to output the output data applied from the data buffer to the outside or to apply input data applied from the outside to the data buffer.

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