KR100578816B1 - Plasma Display and Driving Method - Google Patents

Abstract

The present invention relates to a method of driving a plasma display device. According to the present invention, when the scan voltage is sequentially applied to the Y electrode, the Y electrode is divided into a plurality of groups according to the scanning order, the scan voltage is set differently for each group, and the scan voltage is applied to the first Y electrode of each group. Before the voltage of the Y electrode is gradually lowered and the bias voltage of the X electrode is further included. In this case, since the state of the discharge cell before the application of the scan voltage is restored to the state immediately after the reset, the address discharge efficiency can be increased, and the voltage difference between the X-Y electrodes can be compensated to prevent erroneous discharge from occurring in the sustain period.

Plasma display, scanning pulse, address discharge

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is a partial perspective view of a plasma display device.

2 is a driving waveform diagram of a plasma display device according to the prior art.

3 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

4 is a driving waveform diagram applied to a plasma display panel according to an exemplary embodiment of the present invention.

5 is a circuit diagram for applying a driving waveform according to an embodiment of the present invention.

The present invention relates to a method of driving a plasma display device.

Among the flat panel display devices, the plasma display device has been in the spotlight as a flat panel display device due to the advantages of higher luminance and luminous efficiency and a wider viewing angle than other display devices.

Plasma display devices are flat display devices that display characters or images using plasma generated by gas discharge, and dozens to millions of pixels are arranged in a matrix form according to their size. First, the structure of the plasma display device will be described with reference to FIG. 1.

1 is a partial perspective view of a plasma display device.

As shown in FIG. 1, the plasma display device includes two glass substrates 1 and 6 facing away from each other. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

The electrode of the plasma display panel has a matrix structure of n × m. The plurality of address electrodes A ₁ -A _m are arranged in the vertical direction, and the plurality of scan electrodes Y ₁ -Y _n and the storage electrodes X ₁ -X _n are arranged in pairs in the horizontal direction.

In general, a plasma display device is driven by dividing one frame into a plurality of subfields, and gray levels are expressed by a combination of subfields. In general, each subfield includes a reset period, an address period, and a sustain period.

The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

In this case, the wall charge refers to a charge formed in the wall of the discharge cell (eg, the dielectric layer) close to each electrode and accumulated in the electrode. Such wall charges are not actually in contact with the electrodes themselves, but here wall charges are described as "formed", "accumulated" or "stacked" on the electrodes. In addition, wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

2 is a view showing a driving waveform according to the prior art.

As shown in FIG. 2, at the end of the reset period, the voltage of the scan electrode is maintained while the sum of the wall voltage between the scan electrode and the sustain electrode and the voltages applied to the scan electrode and the sustain electrode is close to the discharge start voltage. Was lowered to the voltage VscL. In the address period, scan pulses having the low voltage VscL and the high voltage VscH are sequentially applied to the scan electrodes, and at the same time, data pulses are applied to the address electrodes to cause address discharge.

On the other hand, the address discharge is determined by the density of the priming particles and the wall voltage formed in the discharge space. However, since the time when the scan pulse is applied after the reset discharge is generated toward the bottom of the panel from the first scan electrode toward the bottom of the panel, the density of the priming particles is gradually lowered toward the bottom of the panel. Further, the wall voltage gradually collapses toward the lower end, and the voltage on the discharge space gradually decreases. Therefore, there is a problem that the discharge delay time is longer toward the bottom, thereby reducing the address margin.

An object of the present invention is to provide a method of driving a plasma display device which can improve a discharge margin in an address period.

According to an aspect of the present invention, a plasma display device includes a panel including a plurality of first electrodes and a plurality of second electrodes; And a driving circuit outputting a signal for driving the first electrode.

The drive circuit,

The first transistor is connected to the first electrode to apply a scanning voltage to the selected first electrode and the second terminal is connected to the first electrode to supply non-scanning voltage to the unselected first electrode. A plurality of selection circuits each including a second transistor, a third transistor electrically connected to a second end of the first transistor, the third transistor operative to gradually decrease a voltage of the first electrode, and the third A fourth transistor electrically connected between a second end of the transistor and a first power supply for supplying the scan voltage and a second power supply electrically connected to the second end of the third transistor and supplying a first voltage And a fifth transistor electrically connected to the second end thereof,

The plurality of first electrodes are driven by being divided into a plurality of groups including a first group and a second group.

In the address period,

Sequentially turning on the first transistor connected to the first electrode of the first group while the fifth transistor is turned on to apply the first voltage to the first electrode of the first group,

Turning off the fifth transistor and turning on the third transistor to gradually lower the voltage of the first electrode from the first voltage to the scan voltage;

In the state where the fourth transistor is turned on, the first transistor connected to the first electrode of the second group is sequentially turned on to apply the scan voltage to the first electrode of the second group.

In addition, the first voltage is applied to the first electrode of the first group in a state in which the voltage of the second electrode is biased to the second voltage,

The scan voltage is applied to the first electrode of the second group in a state in which the voltage of the second electrode is biased to a third voltage lower than the second voltage.

The driving circuit may further include a sixth transistor electrically connected between a third power supply for supplying a fourth voltage for sustain discharge and the fifth transistor,

In the retention period,

The sixth transistor and the fifth transistor are alternately turned on to alternately apply the second voltage and the first voltage to the first electrode.

A driving method of a plasma display device according to an aspect of the present invention is a driving method of a plasma display device including a plurality of first electrodes and a second electrode.

The plurality of first electrodes are driven by being divided into a plurality of groups including a first group and a second group.

a) lowering the voltage of the first electrode to a first voltage through a first path; b) applying a first scan voltage corresponding to the first voltage to the first electrode of the first group through a second path; Sequentially applying, c) lowering the voltage of the first electrode to a second voltage lower than the first voltage through the first path, and d) a first of the second group through the third path. Sequentially applying a second scan voltage corresponding to the second voltage to an electrode.

In step b), the voltage of the second electrode is biased to a third voltage, and in step d), the voltage of the second electrode is biased to a fourth voltage lower than the third voltage.

In this case, the first path is electrically connected between the first electrode and a first power supply for supplying the second scan voltage, and is formed by a first switch operative to gradually decrease the voltage of the first electrode. ,

The second path is formed by a second switch electrically connected between the first electrode and a second power supply for supplying the first voltage.

In addition, the third path is formed by a third switch connected in parallel with the first switch.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

First, a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, an address driver 200, a Y electrode driver 320, an X electrode driver 340, and a controller 400. Include.

The plasma display panel 100 includes a plurality of address electrodes A1 to Am arranged in the column direction, first electrodes Y1 to Yn (hereinafter referred to as Y electrodes), and second electrodes arranged in the row direction. X1 to Xn) (hereinafter referred to as X electrode).

The address driver 200 receives an address driving control signal SA from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The Y electrode driver 320 and the X electrode driver 340 receive the Y electrode driving signal SY and the X electrode driving signal SX from the controller 200 and apply them to the X electrode and the Y electrode, respectively.

The control unit 400 receives an image signal from the outside, generates an address driving control signal SA, a Y electrode driving signal SY, and an X electrode driving signal SX, respectively, and generates an address driving unit 200 and a Y electrode driving unit ( 320 and the X electrode driver 340.

4 is a driving waveform diagram applied to a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 4, when the scan voltage is sequentially applied to the Y electrode, the Y electrode is divided into two groups according to the scanning order, and the scan voltage is set differently for each group. The method further includes a second reset period for gradually decreasing the voltage of the Y electrode, such as a falling ramp reset period, before applying the scan voltage to the first Y electrode of each group. In addition, the X electrode is divided into two groups so as to correspond to each group of the Y electrode, and the voltage of the Y electrode is gradually lowered while the voltage of the Y electrode is gradually lowered before the scan voltage is applied to the first Y electrode of each group during the address period. Lower the voltage on the electrode.

That is, after lowering the voltage of the Y electrode to 0 V in the falling reset period, 0 V scan pulses are sequentially applied to the first scan group while the voltage VscH is applied to all the Y electrodes in the first address period. The X electrode group corresponding to one scan group is biased with the Ve voltage. At this time, the voltage of the Y electrode after the addressing of the first scan group is completed is 0V.

However, in the discharge cell including the Y electrode of the second scan group while applying the scan voltage pulse to the first scan group, the wall voltage may collapse, so that only 0 V scan voltage pulse may not cause stable address discharge. Therefore, the voltage of the Y electrode is gradually lowered from 0V to the voltage VscL before addressing the second scan group, that is, in the second reset period. In addition, the bias voltage of the X electrode group corresponding to the second scan group is also lowered to the Ve 'voltage lower than the Ve voltage.

Then, a weak discharge is generated between the X electrode and the Y electrode and the wall charge is erased to restore the state of the discharge cell to an easy state for address discharge, such as applying a falling ramp waveform in the reset period. When the scan pulses of the voltage VscL are sequentially applied to the second scan group, stable address discharge may occur. In addition, since the voltage difference between the X-Y electrodes is increased as the voltage of the second scan group is lowered, erroneous discharge can be prevented from occurring in the sustain period. At this time, in order to make the address condition of the first scan group and the second scan group the same, the voltage applied to the unselected scan line of the second scan group is also lowered to the voltage VscH '.

FIG. 5 is a detailed circuit diagram of the Y electrode driver 320 of the plasma display panel according to the exemplary embodiment of the present invention which generates the driving waveform of FIG. 4, and has the same configuration as the circuit for supplying the driving waveform of FIG. 3.

That is, the Y electrode driver 320 according to the exemplary embodiment of the present invention includes a rising reset driver 321, a falling reset and scan driver 322, and a sustain driver 323 as shown in FIG. 5.

The reset driver 321 is a rising ramp that generates a reset waveform rising in the reset period. The reset driver 321 gradually supplies voltage Vset-Vs for supplying the voltage Vset-Vs, capacitor Cset operating with a floating power supply, and voltage. The switch Yrr and the switch Ypp formed in the main path to which the sustain voltage generated by the sustain driver 323 is applied to the panel capacitor to prevent the reverse flow of the current Yrr.

Before the reset period, the capacitor Cset is charged to the voltage (Vset-Vs) by the power supply Vset-Vs to which the switch Yg supplies the voltage (Vset-Vs) at turn-on. At the beginning of the reset period, the switch Ys is turned on to apply the voltage Vs to the Y electrode. When the switch Yrr is turned on, the voltage of the panel capacitor Cp is changed by the voltage charged in the capacitor Cset. Gradually rises up to Vset).

The sustain driver 323 generates a sustain discharge pulse in the sustain period, the switches Ys and Yg connected between the power supply Vs and the ground GND, the power recovery capacitor Cyr and the switches Yr and Yf, Inductors Ly and diodes YDr, YDf, YDCH, YDCL.

Before the sustaining period, the capacitor Cyr is charged with the voltage Vs / 2. When the switch Yr is turned on in the sustaining period, resonance occurs between the inductor Ly and the panel capacitor Cp, causing the panel capacitor ( Cp is charged, and then the voltage Vs is continuously supplied to the panel capacitor Cp through the switch Ys. In addition, when the switch Yf is turned on, resonance occurs between the inductor Ly and the panel capacitor Cp to discharge the panel capacitor Cp, and thereafter, the voltage of the panel capacitor Cp is changed through the switch Yg. Keep it at 0V.

At this time, the diodes YDr and YDf are formed in the opposite direction to the body diodes of the switches Yr and Yf in order to block currents that may be formed by the body diodes of the switches Yr and Yf, and the diodes YDCH and YDCL. ) Clamp the second stage potential of the inductor Ly to voltage Vs and voltage GND, respectively.

The falling reset and scan driver 322 generates a scan pulse in a ramp waveform and an address section falling in the reset section, and includes a scan IC including a plurality of selection circuits connected to a power supply VscH, a capacitor Csc, and a Y electrode; And a switch Ysc for supplying a scan voltage VscL and a switch Yfr for gradually lowering the voltage. The scan IC includes switches SCH and SCL, and a source of the switch SCH and a drain of the switch SCL are connected to the Y electrode of the panel capacitor Cp.

In FIG. 5, the panel capacitor Cp equivalently represents the capacitance component between the X electrode and the Y electrode. Also, for convenience, the X electrode of the panel capacitor Cp is displayed as being connected to the ground terminal, but the X electrode driver 340 is actually connected to the X electrode.

In addition, in FIG. 5, each of the switches is represented by an n-channel MOSFET, and each switch may include a body diode.

When the scanning pulse is applied to the panel capacitor Cp by the driving circuit according to the embodiment of the present invention will be described in detail.

According to the exemplary embodiment of the present invention, the rising lamp reset waveform is applied to the Y electrode, and the switch Yfr is turned on while the voltage of the Y electrode maintains the voltage Vs. Then, the current path of the switch SCL-switch Yfr-power VscL is formed, and the Y electrode voltage of the panel capacitor gradually decreases through the operation of the lamp switch Yfr. At this time, when the voltage of the Y electrode becomes 0V, the switch Yfr is turned off and the switch Yg is turned on.

As described above, in the state where the voltage of the Y electrode falls to 0V, the switches SCL of all the selection circuits are first turned off and the switches SCH are turned on at the beginning of the first address period. At this time, since the voltages VscH-VscL are charged in the capacitor Csc, the voltage VscH is applied to all the Y electrodes. Thereafter, when the switch SCH of the selection circuit connected to the first scan group is turned off and the switch SCL is sequentially turned on, the body diode-switch Ypp-switch of the switch SCL-switch Ypn A scan pulse of 0V is applied to the Y electrode of the first scan group through the current path of Yg).

After all of the scan pulses are applied to the first scan group, the switch Yg is turned off and the switch Yfr is turned on again in the second reset period. Then, the current path of the switch SCL-switch Yfr-power source VscL is formed, and the Y electrode voltage of the panel capacitor gradually decreases from 0V to the voltage VscL through the operation of the lamp switch Yfr. At this time, since the voltage charged in the capacitor Csc is kept constant, the voltage on the high side drops from the voltage VscH to the voltage VscH 'as the voltage on the low side of the selection circuit decreases.

In such a state that the voltage VscL of the Y electrode is lowered, when the switches SCL of all the selection circuits are turned off and the switch SCH is turned on in the second address period, the voltage VscH 'is applied to the Y electrode. . Subsequently, while the switch Ysc is turned on, the switch SCH of the selection circuit connected to the second scan group is turned off and the switch SCL is sequentially turned on to supply the voltage VscL to the Y electrode of the second scan group. Apply a scan pulse of.

As described above, according to the exemplary embodiment of the present invention, different scan voltages may be applied to each scan group by adjusting only the drive timing of the switch without adding a separate switch or the like in the circuit for supplying a conventional driving waveform.

Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited thereto, and various other changes and modifications are possible.

As described above, according to the present invention, when the scan voltage is sequentially applied to the Y electrode, the Y electrode is divided into two groups according to the scanning order, and the scan voltage is set differently for each group, and the first Y electrode of each group is provided. The address discharge efficiency can be increased by restoring the state of the discharge cell before applying the scan voltage to the state immediately after the reset by further including a period of gradually lowering the voltage of the Y electrode before applying the scan voltage to.

In addition, according to the present invention, when the voltage of the Y electrode is gradually lowered during the address period, the bias voltage of the X electrode is also lowered to compensate for the voltage difference between the X and Y electrodes, thereby preventing the occurrence of erroneous discharge in the sustain period.

In addition, according to the present invention, since only the driving timing of the switch is adjusted without adding a separate switch, the scan voltage for each scan group can be supplied differently without any additional cost increase.

Claims (10)

A panel including a plurality of first electrodes and a plurality of second electrodes; And a driving circuit outputting a signal for driving the first electrode. The drive circuit, The first transistor is connected to the first electrode to apply a scanning voltage to the selected first electrode and the second terminal is connected to the first electrode to supply non-scanning voltage to the unselected first electrode. A plurality of selection circuits each including a second transistor; A third transistor electrically connected to a second end of the first transistor to operate to gradually decrease a voltage of the first electrode; A fourth transistor electrically connected between a second end of the third transistor and a first power supply for supplying the scan voltage; And A fifth transistor electrically connected to a second end of the third transistor and electrically connected to a second power source for supplying a first voltage; The plurality of first electrodes are driven by being divided into a plurality of groups including a first group and a second group. In the address period, Sequentially turning on the first transistor connected to the first electrode of the first group while the fifth transistor is turned on to apply the first voltage to the first electrode of the first group, Turning off the fifth transistor and turning on the third transistor to gradually lower the voltage of the first electrode from the first voltage to the scan voltage; Sequentially turning on the first transistor connected to the first electrode of the second group while the fourth transistor is turned on to apply the scan voltage to the first electrode of the second group Plasma display device. The method of claim 1, In the address period, Applying the first voltage to the first electrode of the first group in a state in which the voltage of the second electrode is biased to a second voltage, The scanning voltage is applied to the first electrode of the second group while the voltage of the second electrode is biased to a third voltage lower than the second voltage. Plasma display device. The method of claim 1, In the reset period, Turning on the fifth transistor to gradually lower the voltage of the first electrode to the first voltage; Plasma display device. The method of claim 1, The driving circuit further includes a sixth transistor electrically connected between a third power supply for supplying a fourth voltage for sustain discharge and the fifth transistor, In the retention period, Alternately turning on the sixth transistor and the fifth transistor to alternately apply the second voltage and the first voltage to the first electrode; Plasma display device. In the driving method of a plasma display device including a plurality of first electrodes and a plurality of second electrodes, The plurality of first electrodes are driven by being divided into a plurality of groups including a first group and a second group. a) lowering the voltage of the first electrode to a first voltage through a first path; b) sequentially applying a first scan voltage corresponding to the first voltage to the first electrodes of the first group through a second path; c) lowering the voltage of the first electrode to a second voltage lower than the first voltage through the first path; And d) sequentially applying a second scan voltage corresponding to the second voltage to the first electrode of the second group through a third path; Method of driving a plasma display device comprising a. The method of claim 5, In step b), biasing the voltage of the second electrode to a third voltage; In step d), biasing the voltage of the second electrode to a fourth voltage lower than the third voltage. A method of driving a plasma display device. The method of claim 5, The first path is electrically connected between the first electrode and a first power supply for supplying the second scan voltage, and is formed by a first switch operative to gradually decrease the voltage of the first electrode. A method of driving a plasma display device. The method of claim 5, The second path is formed by a second switch electrically connected between the first electrode and a second power supply for supplying the first voltage. A method of driving a plasma display device. The method of claim 5, The third path is formed by a third switch connected in parallel with the first switch. A method of driving a plasma display device. The method according to claim 5 or 7, In the sustain period, a voltage for sustain discharge and the first voltage are alternately applied to the first electrode, and the first voltage is applied through the second path. A method of driving a plasma display device.

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