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KR100532769B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR100532769B1
KR100532769B1 KR10-2003-0099526A KR20030099526A KR100532769B1 KR 100532769 B1 KR100532769 B1 KR 100532769B1 KR 20030099526 A KR20030099526 A KR 20030099526A KR 100532769 B1 KR100532769 B1 KR 100532769B1
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insulating film
gate insulating
region
semiconductor device
manufacturing
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KR20050070252A (en
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오태원
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 안정적인 공정으로 신뢰성 있게 제1 전압 제2 전압, 제3 전압에서 구동할 수 있는 모스 트랜지스터의 트리플 게이트를 제조할 수 있는 방법을 제공하기 위한 것으로, 이를 위해 본 발명은 실리콘 기판 상에 제1 게이트용 절연막을 형성하는 단계와, 제1 게이트용 절연막 상의 제1 영역에 불순물을 임플란트시키는 단계와, 불순물이 임플란트된 제1 영역과 불순물이 임플란트되지 않은 소정의 제2 영역에 형성된 제1 게이트용 절연막을 제거하여 제3 영역에만 제1 게이트용 절연막을 남기는 단계와, 제1 내지 제3 영역 상에 제2 게이트용 절연막을 형성하는 단계를 포함하며, 제1 내지 제3 영역이 서로 다른 두께의 게이트 절연막으로 형성되는 것을 특징으로 하는 반도체 장치의 제조 방법을 제공한다.The present invention is to provide a method for manufacturing a triple gate of a MOS transistor that can be driven at a first voltage, a second voltage, a third voltage in a stable process reliably. Forming a first gate insulating film, implanting an impurity in a first region on the first gate insulating film, a first region in which the impurity is implanted, and a first gate formed in a predetermined second region in which the impurity is not implanted Removing the insulating film to leave the first gate insulating film only in the third region, and forming the second gate insulating film on the first to third regions, wherein the first to third regions have different thicknesses. It provides a manufacturing method of a semiconductor device, characterized in that formed of a gate insulating film.

Description

반도체 장치의 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 각각 서로 다른 3가지의 두께를 가지는 트리플게이트의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a triple gate having three different thicknesses.

반도체 소자의 고집적화에 따라서, 최근에는 하나의 소자 내에 고전압용 모스트랜지스터를 위한 게이트와 저전압용 모스트랜지스터를 위한 게이트가 동시에 형성된 듀얼 게이트 트랜지스터의 쓰임이 보편화되었다.Background Art In recent years, with the high integration of semiconductor devices, the use of dual gate transistors in which a gate for a high voltage MOS transistor and a gate for a low voltage MOS transistor are simultaneously formed in one device has become common.

고전압용 트랜지스터와 저전압 트랜지스터는 각각 고전압과 저전압을 게이트로 인가 받게 되므로, 각각의 게이트 절연막의 유전율도 달라야 한다. 따라서 고전압용 트랜지스터의 게이트 절연막과 저전압 트랜지스터의 게이트 절연막의 두께는 상대적으로 다르게 형성되어야 한다.Since the high voltage transistor and the low voltage transistor are applied with the high voltage and the low voltage as the gates, the dielectric constant of each gate insulating film must also be different. Therefore, the thickness of the gate insulating film of the high voltage transistor and the gate insulating film of the low voltage transistor should be relatively different.

도 1a 내지 1c는 종래 기술에 의한 반도체 장치의 제조 방법에 관한 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a를 참조하면, 종래 기술에 의한 반도체 장치의 제조방법은 실리콘기판(10)상에 열 공정을 이용하여 실리콘 산화막으로 제1 게이트용 절연막(11)을 형성한다. 여기서 제1 게이트용 절연막(11)은 후에 고전압용 게이트 절연막으로 사용되기 때문에, 그 두께는 게이트에 인가된 고전압을 고려하여 결정한다. 여기서는 40 ∼ 60Å 정도로 형성한다.Referring to FIG. 1A, in the method of manufacturing a semiconductor device according to the related art, a first gate insulating film 11 is formed of a silicon oxide film using a thermal process on a silicon substrate 10. Since the first gate insulating film 11 is later used as the high voltage gate insulating film, the thickness thereof is determined in consideration of the high voltage applied to the gate. Here, it forms about 40-60 Hz.

이어서 도 1b에 도시된 바와 같이, 제1 게이트용 절연막(11) 상에 저전압 영역이 오픈된 감광막 패턴(12)을 형성한다. 이어서 감광막 패턴(12)을 이용하여 저전압영역의 제1 게이트용 절연막(11)을 식각한 뒤, 감광막 패턴(12)을 제거하고, 세정공정을 진행한다.Subsequently, as illustrated in FIG. 1B, a photosensitive film pattern 12 having a low voltage region open is formed on the first gate insulating layer 11. Subsequently, the first gate insulating film 11 in the low voltage region is etched using the photosensitive film pattern 12, and then the photosensitive film pattern 12 is removed to perform a cleaning process.

다음에, 고전압 영역과 저전압 영역 모두에 제2 게이트용 절연막(13)을 형성한다.Next, the second gate insulating film 13 is formed in both the high voltage region and the low voltage region.

그 결과, 도 1b에 도시된 바와 같이, 고전압 영역에는 제1 및 제2 게이트용 절연막(11, 13)이 모두 형성되고, 저전압 영역에는 제2 게이트용 절연막(13)만 형성되는 상태가 된다.As a result, as shown in FIG. 1B, both the first and second gate insulating films 11 and 13 are formed in the high voltage region, and only the second gate insulating film 13 is formed in the low voltage region.

여기에서, 고전압 영역에 형성되는 모스 트랜지스터의 게이트 절연막은 고전압이 인가되기 때문에, 게이트 두께를 상대적으로 두껍게 형성하고, 저전압 영역에 형성되는 모스 트랜지스터의 게이트 절연막은 저전압이 인가되기 때문에, 게이트 두께를 상대적으로 얇게 형성하는 것이다.Here, since the gate insulating film of the MOS transistor formed in the high voltage region is applied with a high voltage, the gate thickness is relatively thick, and the gate insulating film of the MOS transistor formed in the low voltage region is applied with the low voltage, so that the gate thickness is relatively It is to form a thin.

전술한 제1 게이트용 절연막(11)과 제2 게이트용 절연막(13)은 대체로 실리콘 산화막을 이용하여 형성하게 된다.The first gate insulating film 11 and the second gate insulating film 13 described above are generally formed using a silicon oxide film.

메모리 장치가 고집적화되면서, 정밀하게 제1 게이트용 절연막(11)과 제2 게이트용 절연막(13)을 고전압 영역과 저전압 영역에 정확하게 형성하기가 어려워지고 있다.As memory devices become highly integrated, it is difficult to accurately form the first gate insulating film 11 and the second gate insulating film 13 in the high voltage region and the low voltage region.

더구나 기술이 점점 더 발달하면서 하나의 반도체 장치 내에서 3개의 서로 다른 두께를 가지는 트리플 게이트를 제조하는 경우도 발생하는데, 이 경우에는 더욱 신뢰성 있게 모스 트랜지스터의 게이트 절연막을 형성하기가 쉽지 않다.In addition, as the technology develops, a triple gate having three different thicknesses is manufactured in one semiconductor device. In this case, it is difficult to form a gate insulating film of a MOS transistor more reliably.

본 발명은 안정적인 공정으로 신뢰성 있게 제1 전압 제2 전압, 제3 전압에서 구동 가능한 모스 트랜지스터의 트리플게이트를 제조할 수 있는 반도체 장치의 제조방법을 제공함을 목적으로 한다.It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of manufacturing a triple gate of a MOS transistor that can be driven at a first voltage, a second voltage, and a third voltage in a stable process.

상기 목적을 달성하기 위한 본 발명은, 실리콘 기판상에 제1 게이트용 절연막을 형성하는 단계와, 상기 제1 게이트용 절연막 상의 제1 영역에 불순물을 임플란트시키는 단계와, 상기 불순물이 임플란트된 제1 영역과 불순물이 임플란트되지 않은 소정의 제2 영역에 형성된 상기 제1 게이트용 절연막을 제거하여 제3 영역에만 상기 제1 게이트용 절연막을 남기는 단계와, 상기 제1 내지 제3 영역 상에 제2 게이트용 절연막을 형성하는 단계를 포함하며, 상기 제1 내지 제3 영역이 서로 다른 두께의 게이트 절연막으로 형성되는 것을 특징으로 하는 반도체 장치의 제조 방법을 제공한다.According to an aspect of the present invention, there is provided a method of forming an insulating film for a first gate on a silicon substrate, implanting an impurity into a first region on the insulating film for the first gate, and a first implanted with the impurity. Removing the insulating film for the first gate formed in the predetermined second region where the region and the impurity are not implanted, and leaving the insulating film for the first gate only in the third region; and forming a second gate on the first to third regions. A method of manufacturing a semiconductor device, the method comprising: forming an insulating film for forming a semiconductor film, wherein the first to third regions are formed of gate insulating films having different thicknesses.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시 할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시 예를 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 2a 내지 2d는 본 발명의 바람직한 실시 예에 따른 반도체 장치의 제조방법에 관한 공정 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 본 실시 예에 따른 반도체 장치의 제조 방법은 먼저 웰 임플란트 공정을 통해 P웰 또는 N웰(도시 생략)이 형성된 실리콘 기판(20)상에, 예를 들면 실리콘 산화막으로 된 제1 게이트용 절연막(21)을 형성하는데, 이러한 제1 게이트용 절연막(21)은, 예를 들면 대략 40 ∼ 60Å 정도의 두께로 형성한다.As shown in FIG. 2A, a method of manufacturing a semiconductor device according to an embodiment of the present invention first includes a silicon oxide film on a silicon substrate 20 on which P wells or N wells (not shown) are formed through a well implant process. The first gate insulating film 21 is formed, and the first gate insulating film 21 is formed to a thickness of, for example, about 40 to 60 kPa.

다음에, 감광막을 이용하여 게1 게이트용 절연막(21) 상에 임의의 패턴을 갖는 감광막 패턴(22a, 22b)을 형성, 즉 제2 전압 영역의 일부를 노출시키는 형태로 감광막 패턴(22a, 22b)을 형성한다.Next, the photosensitive film patterns 22a and 22b having arbitrary patterns are formed on the first gate insulating film 21 by using the photosensitive film, that is, the photosensitive film patterns 22a and 22b are formed in such a manner as to expose a part of the second voltage region. ).

이어서, 도 2b에 도시된 바와 같이, 감광막 패턴(22a, 22b)에 의해 노출된 제2 전압 영역에 한하여 불소(Flourine)를 주입하는 임플란트 공정을 진행하는데, 이때 사용하는 에너지는 5KeV ∼ 50 KeV, 도즈(Dose)는 1E15atoms/cm2 ∼ 5E15atoms/cm2정도로 한다. 도 2b에 있어서, 점선으로 표시된 부분은 불소 임플란트가 적용되는 영역을 의미한다.Subsequently, as shown in FIG. 2B, an implant process of injecting fluorine in the second voltage region exposed by the photoresist patterns 22a and 22b is performed. The energy used is 5 KeV to 50 KeV, Dose should be about 1E15 atoms / cm 2 to 5E 15 atoms / cm 2. In FIG. 2B, a portion indicated by a dotted line means a region to which a fluorine implant is applied.

다시, 도 2c에 도시된 바와 같이, 제1 전압 영역의 감광막 패턴(22b)을 제거하고, 세정공정을 통해 제1 전압 영역과 제2 전압 영역에 있는 제1 게이트용 절연막(21)을 선택적으로 제거하여 기판표면의 일부를 노출시키며, 이후 제3 전압 영역에 잔류하는 감광막 패턴(22a)을 제거한다.2C, the photoresist pattern 22b of the first voltage region is removed, and the first gate insulating layer 21 in the first voltage region and the second voltage region is selectively removed through a cleaning process. The substrate surface is removed to expose a portion of the substrate surface, and then the photoresist pattern 22a remaining in the third voltage region is removed.

이어서, 도 2d에 도시된 바와 같이, 실리콘 산화막을 이용하여 제2 게이트용 절연막(23)을 형성하는데, O2와 H2를 사용하여 습식산화를 진행하며, HCl 6%를 혼합하여 산소 퀄리티(Quality)를 향상시킨다. 다시, 가스를 사용하여 않고 대략 750℃의 온도 조건에서 30분 정도의 열 공정을 진행한다. 이때 열 공정을 진행하는 이유는 얇은 제2 게이트용 절연막(23)의 취약한 문제점인 보론의 침투를 방지 할 수 있도록 하기 위한 것이다.Subsequently, as shown in FIG. 2D, the second gate insulating film 23 is formed using a silicon oxide film, and wet oxidation is performed using O 2 and H 2 , and HCl 6% is mixed to obtain an oxygen quality ( Improve quality. Again, the thermal process is carried out for about 30 minutes at a temperature condition of approximately 750 ° C. without using gas. In this case, the thermal process is performed to prevent penetration of boron, which is a weak problem of the thin second gate insulating layer 23.

여기에서, 불소의 이온 주입된 영역에서는 산화막 성장이 촉진되므로, 이온이 주입되지 않는 영역보다 두꺼운 산화막을 얻을 수 있다.Here, since the oxide film growth is promoted in the fluorine ion implanted region, an oxide film thicker than the region where no ions are implanted can be obtained.

최종적으로, 게이트 절연막의 두께가 서로 다른 3가지의 트리플 게이트를 얻을 수 있으며, 이를 이용한 모스 트랜지스터는 구동 전압이 서로 다른 회로에 사용될 수 있다.Finally, three triple gates having different thicknesses of the gate insulating layer may be obtained, and the MOS transistor using the same may be used in a circuit having different driving voltages.

이상에서 설명한 본 발명은 전술한 실시 예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

이상에서 살펴본 바와 같이 본 발명에 의하여 게이트 절연막을 세 번의 공정으로 나누어 진행하지 않고, 트리플 게이트 구조를 형성할 수 있기 때문에 공정 단순화 및 이를 통한 생산원가의 절감을 기대할 수 있다.As described above, a triple gate structure can be formed without dividing the gate insulating film into three processes, thereby simplifying the process and reducing production costs.

또한, 본 발명은 열 공정이 줄어듦에 따라 이온 불순불의 확산을 예방하고, 불소 임플란트 공정을 사용함으로서, 게이트 절연막에 의한 누설전류 특성이 향상되므로, 이를 통해 반도체 장치의 제조 공정의 신뢰성을 향상시킬 수 있다.In addition, the present invention prevents the diffusion of ion impurities as the thermal process is reduced, and by using the fluorine implant process, the leakage current characteristics by the gate insulating film is improved, thereby improving the reliability of the manufacturing process of the semiconductor device. have.

도 1a 내지 1d는 종래 기술에 의한 반도체 장치의 제조 방법에 관한 공정 단면도,1A to 1D are cross sectional views of a process for manufacturing a semiconductor device according to the prior art;

도 2a 내지 2d는 본 발명의 바람직한 실시 예에 따른 반도체 장치의 제조 방법에 관한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

20 : 기판20: substrate

21 : 제1 게이트용 절연막21: insulating film for first gate

22 : 감광막패턴22: photosensitive film pattern

23 : 제2 게이트용 절연막.23: insulating film for second gate.

Claims (8)

실리콘 기판상에 게이트용 절연막을 형성하는 단계와,Forming a gate insulating film on the silicon substrate; 상기 게이트용 절연막 상에 제1 영역을 오픈시키는 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern on the gate insulating layer to open a first region; 상기 제1 영역에 불순물을 임플란트시키는 단계와,Implanting impurities into the first region; 상기 제1 영역의 게이트용 절연막과 상기 불순물이 임플란트되지 않은 제2 영역의 게이트용 절연막과 그 위의 상기 감광막 패턴을 제거함으로써, 제3 영역에만 상기 게이트용 절연막을 선택적으로 잔류시키는 단계와,Selectively removing the gate insulating film only in the third region by removing the gate insulating film in the first region, the gate insulating film in the second region where the impurities are not implanted, and the photoresist pattern thereon; 상기 제3 영역의 게이트용 절연막 상에 잔류하는 상기 감광막 패턴을 제거하는 단계와,Removing the photoresist pattern remaining on the gate insulating film of the third region; 산화막 형성 공정을 실시하여 상기 제1 영역, 제2 영역 및 제3 영역 상의 막 두께가 서로 다른 구조의 게이트 절연막을 완성하는 단계Performing a process of forming an oxide film to complete a gate insulating film having a structure having different thicknesses on the first region, the second region, and the third region 를 포함하는 반도체 장치의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 불순물은, 불소인 것을 특징으로 하는 반도체 장치의 제조 방법.The impurity is fluorine, the manufacturing method of a semiconductor device. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 불순물을 임플란트시킬 때의 에너지는 5KeV ~ 50 KeV, 도즈(Dose)는 1E15atoms/cm2 ~ 5E15atoms/cm2 정도인 것을 특징으로 하는 반도체 장치의 제조 방법.The energy of implanting the impurity is 5 KeV ~ 50 KeV, the dose (Dose) is about 1E15 atoms / cm2 ~ 5E15 atoms / cm2 manufacturing method of a semiconductor device. 삭제delete 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 방법은, 상기 게이트 절연막을 완성한 후에 불순물이 침투되지 않도록 열 공정을 진행하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.The method further comprises the step of performing a thermal process such that impurities do not penetrate after completing the gate insulating film. 제 1 항에 있어서,The method of claim 1, 상기 게이트용 절연막은, 실리콘 산화막인 것을 특징으로 하는 반도체 장치의 제조 방법.The said insulating film for gates is a silicon oxide film, The manufacturing method of the semiconductor device characterized by the above-mentioned. 제 7 항에 있어서,The method of claim 7, wherein 상기 실리콘 산화막은, O2와 H2를 사용하여 습식산화를 진행함으로서 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.The silicon oxide film is formed by advancing wet oxidation using O 2 and H 2 .
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