KR100516677B1 - Method for manufacturing transistor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor. In particular, in a process of forming a double-gate device, a source is formed after forming a lower gate on a silicon on insulator (SOI) wafer having an buried oxide film formed under an upper silicon substrate After forming a nitride film under the buried oxide film in the drain region, the wafer is turned over, and the upper gate and the lower gate are formed by a buried wiring method by etching the silicon substrate of the portion where the lower gate is formed by using the nitride film as a barrier. It features the ability to precisely align the gate to improve device yield and reliability.

Description

Method for manufacturing transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor, and more particularly, to a method of fabricating a transistor in which a double-gate device in which an upper gate and a lower gate are precisely aligned is formed to improve the yield and reliability of the device.

Currently, research is being conducted on double-gate devices suitable for the next generation of low voltage and high speed devices.

The double-gate device generally forms the gate electrode 2 above and below the silicon substrate 1 forming the channel, as shown in FIG. 1.

In addition, the double-gate device has an advantage of having a good subthreshold slope, an excellent short channel property, and a fully-depleted device property. There is a disadvantage in that it is difficult to accurately align the upper gate electrode and the lower gate electrode.

The conventional method of manufacturing a transistor has a problem in that it is difficult to accurately align the upper gate electrode and the lower gate electrode in the process of forming a double-gate device, thereby degrading yield and reliability of the device.

The present invention has been made to solve the above problems, and in the process of forming a double-gate device, after forming a lower gate on an SOI wafer having an buried oxide film formed under an upper silicon substrate, a nitride film is formed under the buried oxide film of a source-drain region. Forming and flipping the wafer and then etching the silicon substrate of the portion where the lower gate is formed with the nitride film as a barrier to form an upper gate by a buried wiring method to provide a method of manufacturing a transistor to accurately align the upper gate and the lower gate. There is a purpose.

In the method of manufacturing a transistor of the present invention, forming a first gate electrode on a first semiconductor substrate of an SOI formed by stacking a lower silicon layer, an buried oxide film, and a p-type upper silicon layer, and lower silicon on both sides of the first gate electrode. Forming a nitride film in the surface of the layer, forming an interlayer insulating film on the entire surface, bonding a second semiconductor substrate to the interlayer insulating film, rotating the entire structure up and down, removing the lower silicon layer and removing the nitride film Selectively etching the buried oxide film over the first gate electrode using a mask, forming a second gate electrode on the exposed upper silicon layer above the first gate electrode, removing the nitride film and the buried oxide film; A source / drain impurity region is formed in upper silicon layers on both sides of the first and second gate electrodes. It is characterized by consisting of a system.

When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a transistor according to the present invention as follows.

In the method of manufacturing a transistor according to an exemplary embodiment of the present invention, as illustrated in FIG. 2A, a silicon on insulator (SOI) formed by stacking a lower silicon layer 43, an buried oxide film 45, and a p-type upper silicon layer 47 is stacked. A second oxide film 53 and a first photosensitive film (not shown) are sequentially formed of the first oxide film, the first polycrystalline silicon layer, and the hard mask layer on the semiconductor substrate 41.

 After selectively exposing and developing the first photoresist film so as to remain only at a portion where the first gate electrode is to be formed, the second oxide film 53 and the first polycrystalline silicon are formed using the selectively exposed and developed first photoresist film as a mask. The layer and the first oxide film are selectively etched to form the first gate oxide film 49 and the first gate electrode 51, and then the first photosensitive film is removed.

As shown in FIG. 2B, nitrogen (N) ions are implanted into the entire surface using the second oxide layer as a mask, and then drive-in to lower silicon layers 43 on both sides of the first gate electrode 51. A nitride film 55 having a thickness of 100 to 5000 GPa is formed in the surface.

As shown in FIG. 2C, an interlayer insulating layer 57 is formed on the entire surface including the first gate electrode 51, and a planarization process is performed.

Then, the support silicon substrate 59 is bonded to the interlayer insulating film 57.

Here, the support silicon substrate 59 is irrelevant to element formation and is only used as a support in a subsequent process, so that a wafer of poor quality may be used.

As shown in Figure 2d, the bonded structure is turned upside down.

As shown in FIG. 2E, after etching the entire lower silicon layer 43 by the chemical mechanical polishing method using the nitride film 55 as an etch stop layer, the remaining lower silicon layer 43 is removed.

The buried oxide film 45 is selectively etched using the nitride film 55 as a mask.

As shown in FIG. 2F, after the channel control ion is implanted into the entire surface, a second gate oxide layer 61 is grown on the exposed upper silicon layer 47 by a thermal oxidation process.

A second polycrystalline silicon layer is formed on the entire surface, and the second gate electrode 63 is formed by etching the entire surface of the second polycrystalline silicon layer by a chemical mechanical polishing method using the nitride film 55 as an etch stop layer.

As shown in FIG. 2G, the nitride film 55 and the buried oxide film 45 are removed.

The source / drain impurity region 65 is formed in the upper silicon layer 47 by implanting and driving in the n-type impurity ions on the entire surface of the second gate electrode 63 as a mask.

In the method of manufacturing a transistor of the present invention, in the process of forming a double-gate device, a lower gate is formed on an SOI wafer in which an investment oxide film is formed under an upper silicon substrate, and then a nitride film is formed under the investment oxide film in a source-drain region and the wafer is inverted. Thereafter, by etching the silicon substrate in the portion where the lower gate is formed using the nitride layer as a barrier, the upper gate is formed by a buried wiring method, thereby accurately aligning the upper gate and the lower gate, thereby improving the yield and reliability of the device.

1 shows a typical double-gate device

2A to 2G are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

41 semiconductor substrate 43 lower silicon layer

45: buried oxide film 47: upper silicon layer

49: first gate oxide film 51: first gate electrode

53: second oxide film 55: nitride film

57 interlayer insulating film 59 silicon substrate

61: second gate oxide film 63: second gate electrode

65 source / drain impurity region

Claims (2)

Forming a first gate electrode on the first semiconductor substrate of the SOI formed by stacking the lower silicon layer, the buried oxide film, and the p-type upper silicon layer; Forming an etch stop layer on a surface of the lower silicon layer on both sides of the first gate electrode; Forming an interlayer insulating film on the entire surface; Bonding a second semiconductor substrate to the interlayer insulating film; Rotating the entire structure up and down; Removing the lower silicon layer and selectively etching the buried oxide layer on the first gate electrode with the etch stop layer as a mask; Forming a second gate electrode on the exposed upper silicon layer above the first gate electrode; Removing the etch stop layer and the buried oxide film; And forming a source / drain impurity region in the upper silicon layers on both sides of the first and second gate electrodes. The method of claim 1, The etching prevention film is formed of a nitride film having a thickness of 100 ~ 5000 kPa.