KR100476699B1 - Electrostatic discharge protection circuit and method of manufacturing the same - Google Patents

Abstract

The present invention relates to an electrostatic discharge protection circuit and a method of manufacturing the same, comprising an input pad, a resistor connected between the input pad and an internal circuit, a transfer gate connected between the input pad and a resistor, and a transmission with the input pad. A bipolar junction transistor connected between the node between the gate and the ground terminal, first and second NMOS transistors connected in series between the node between the transfer gate and the resistor and the ground terminal, and between the resistor and the internal circuit. Electrostatic discharge which includes a third NMOS transistor connected between the node and the ground terminal to effectively improve the ESD protection of the mixed threshold voltage input / output structure used in the integrated circuit of the high speed circuit, thereby improving the reproducibility of the integrated circuit. A protection circuit and a method of manufacturing the same are provided.

Description

Electrostatic discharge protection circuit and method of manufacturing the same {Electrostatic discharge protection circuit and method of manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (hereinafter referred to as "ESD") protection circuit. In particular, it is possible to effectively improve ESD protection by using a transfer gate consisting of a bipolar junction transistor and two NMOS transistors. The present invention relates to an ESD protection circuit that can improve the reliability.

There are various failure modes generated in integrated circuits of memory devices, but EOS and ESD modes include electrical phenomena. Among them, the ESD phenomenon is a phenomenon caused by the flow of static electricity, and the current flows concentrated in the most vulnerable portion of the transistor, which causes defects due to melting in the junction region, the contact, or the gate oxide layer. ESD phenomena are classified into HBM, MM, and CDM depending on the cause, and ESD protection circuits are configured on the input pads to protect internal circuits against such ESD phenomena.

1 is a diagram of a conventional ESD protection circuit, in which a resistor R11 is connected between an input pad 11 and an internal circuit, and is connected between a node between the input pad 11 and a resistor R11 and a ground terminal Vss. The first and second NMOS transistors N11 and N12 are connected in series, and the third NMOS transistor N13 is connected in a diode form between the node between the resistor R11 and the internal circuit and the ground terminal Vss.

The conventional ESD protection circuit configured as described above has low ESD discharge levels of the first and second NMOS transistors. This is because the breakdown occurs through the two NMOS transistors, so the turn-on time of the ESD is late, which causes a lot of parasitic operation. Therefore, more than necessary junctions have to be consumed, which creates a problem of increasing parasitic capacitance. Integrated circuits that feature high-speed operation require very small parasitic capacitances on the pins, making it difficult to solve this problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide an ESD protection circuit and a method of manufacturing the same, which can reduce parasitic capacitance and improve reliability of an integrated circuit.

Another object of the present invention is to provide an ESD protection circuit and a method of manufacturing the same, which can disconnect the circuit using a transfer gate and form an ESD protection transistor to secure the characteristics of the ESD.

An ESD protection circuit according to the present invention for achieving the above object includes an input pad, a resistor connected between the input pad and an internal circuit, a transfer gate connected between the input pad and a resistor, and a transfer with the input pad. A bipolar junction transistor connected between the node between the gate and the ground terminal, first and second NMOS transistors connected in series between the node between the transfer gate and the resistor and the ground terminal, and between the resistor and the internal circuit. And a third NMOS transistor connected between the node and the ground terminal.

In addition, a method of manufacturing an ESD circuit according to the present invention for achieving the above object is a bipolar junction transistor, a transfer gate, a first and second NMOS transistor, a resistor and a third NMOS transistor connected in series between the input pad and the internal resistor. In the method of manufacturing an electrostatic discharge protection circuit, the bipolar junction transistor and the transfer gate form a plurality of field oxide films in a predetermined region on a semiconductor substrate to form an NMOS transistor region, a bipolar junction transistor region, a pickup region, and a well guard ring region. Determining, forming a gate electrode on a predetermined region of the semiconductor substrate in the NMOS transistor region, performing a low concentration impurity ion implantation process, forming a spacer on the sidewall of the gate electrode formed in the NMOS transistor region; High concentration impurities on top of the whole structure And forming a source region and a drain region in the NMOS transistor region by forming an ion implantation process, and forming the bipolar junction transistor region, a pickup region, and a well guard ring region.

The present invention will be described in detail with reference to the accompanying drawings.

2 is an ESD protection circuit diagram according to the present invention, and is configured as follows.

A resistor R21 is connected between the input pad 21 and the internal circuit. The transfer gate T21 is connected between the input pad 21 and the resistor. The transfer gate T21 has a structure in which two NMOS transistors are connected, and two portions thereof are respectively driven according to a power supply voltage Vcc. A parasitic bipolar junction transistor B21 is connected in a diode form between the node between the input pad 21 and the transfer gate T21 and the ground terminal Vss, and the collector is connected to the node between the input pad and the transfer gate. The base and emitter are connected to ground terminal Vss, respectively. The first and second NMOS transistors N21 and N22 are connected in series between the node between the transfer gate T21 and the resistor R21 and the ground terminal Vss. A third NMOS transistor N23 is connected in the form of a diode between the node between the resistor and the internal circuit and the ground terminal Vss.

The driving method of the ESD protection circuit according to the present invention configured as described above is as follows.

In driving a typical DRAM, an ESD protection circuit is used as a resistor having a small value. However, the ESD zapping mode serves to protect the ESD. That is, the parasitic bipolar junction transistor B21 serves to flow most of the current due to ESD to the ground terminal Vss, and transfers the transfer gate T21 and the first and second NMOS transistors N21 and N22. The current through the ESD flows to the ground terminal (Vss). Since current flows through these three transistors, the resistance is large and the current does not flow well. Here, the channel length of the transfer gate T21 is 0.5 μm or more, and the transfer gate T21 is provided within 1 μm from the input pad 21, that is, the element to be protected. On the other hand, the gate bias for turning on the transfer gate T21 uses a voltage to which the threshold voltage of the NMOS transistor is further added to the voltage to which the input signal is applied in a high state.

3 is a cross-sectional view of an ESD protection circuit in accordance with the present invention, a cross-sectional view of a transfer gate and a bipolar junction transistor.

A plurality of field oxide films 32 are formed in predetermined regions on the semiconductor substrate 31. By forming a plurality of field oxide films 32, the NMOS transistor region 40, the bipolar junction transistor region 50, the pick up region 60, and the well guard ring region 70 are determined. . After the gate electrode 33 is formed in a predetermined region over the semiconductor substrate 31 of the NMOS transistor region 40, a low concentration impurity ion implantation process is performed to form a low concentration impurity region. After forming the spacer 34 on the sidewall of the gate electrode 33, a high concentration impurity ion implantation process is performed on the entire structure to form the source region 35 and the drain region 36 in the NMOS transistor region 40. Then, the bipolar junction transistor region 50, the pick up region 60, and the well guard ring region 70 are formed.

As described above, according to the present invention, it is possible to effectively improve the ESD protection of the mixed threshold voltage input / output terminals mainly used for the integrated circuit of the high speed circuit, thereby improving the reliability of the integrated circuit.

1 is a conventional electrostatic discharge protection circuit diagram.

2 is an electrostatic discharge protection circuit diagram according to the present invention.

3 is a cross-sectional view of an electrostatic discharge protection circuit according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11 and 21: input pads R11 and R21: first and second resistors

N11, N12, and N13: first, second, and third NMOS transistors

N21, N22, and N23: first, second, and third NMOS transistors

T21: transfer gate B21: bipolar junction transistor

40: NMOS transistor region 50: bipolar junction transistor region

60: pickup area 70: well guard ring area

31 semiconductor substrate 32 field oxide film

33 gate electrode 34 spacer

35 source region 36 drain region

Claims (6)

With an input pad, With internal circuits, A resistor connected between the input pad and the internal circuit, A transfer gate connected between the input pad and the resistor, A bipolar junction transistor connected between a node between the input pad and the transfer gate and a ground terminal, a collector connected to a node between the input pad and a transfer gate, and a base and an emitter respectively connected to a ground terminal; First and second NMOS transistors connected in series between a node between the transfer gate and the resistor and the ground terminal; And a third NMOS transistor connected between the node between the resistor and the internal circuit and the ground terminal. 2. The electrostatic discharge protection circuit of claim 1, wherein the transfer gate is comprised of two NMOS transistors. 2. The electrostatic discharge circuit according to claim 1, wherein the channel length of the transfer gate is 0.5 mu m or more. The electrostatic discharge protection circuit of claim 1, wherein the transfer gate is formed within 1 μm of the input pad. 2. The electrostatic discharge protection circuit of claim 1, wherein the transfer gate is driven by a sum of a high voltage and a threshold voltage of the NMOS transistor. A method of manufacturing an electrostatic discharge protection circuit consisting of a bipolar junction transistor, a transfer gate, first and second NMOS transistors connected in series, an resistor, and a third NMOS transistor between an input pad and an internal resistor, Determining a NMOS transistor region, a bipolar junction transistor region, a pick-up region and a well guarding region by forming a plurality of field oxide films in a predetermined region on the semiconductor substrate; Performing a low concentration impurity ion implantation process after forming a gate electrode on a predetermined region of the semiconductor substrate in the NMOS transistor region; Forming a spacer on a sidewall of a gate electrode formed in the NMOS transistor region; Forming a source region and a drain region in the NMOS transistor region by forming a high concentration impurity ion implantation process over the entire structure, and forming the bipolar junction transistor region, a pickup region, and a well guard ring region. Method of manufacturing an electrostatic discharge protection circuit.