KR100439239B1 - Apparatus for interface between virtual concatenation block and generic framing procedure block - Google Patents

Abstract

The present invention contemplates that the virtual concatenated block operates at a high speed clock, so that the virtual concatenated block is suitable for performing an interface with the generic framing procedure (GFP) block using a minimum number of control signals while using a multi-bit bus. The GFP block is designed to provide an interface device between the generic framing block and the GFP block that attenuates the speed difference between the data transmitted from the virtual connection block and the data transmitted from its upper layer and performs the set error check. and; It includes a virtual connection block that attenuates the speed difference between the data transmitted from the GFP block and the data transmitted from its lower layer to include a set error checking pattern, and then delivers it to the destination, respectively. By using a multi-bit bus, a low speed clock can be used while using minimal control signals, enabling accurate interface configuration and simplified hardware implementation.

Description

Interface device between virtual concatenation block and generic framing procedure block

The present invention relates to an interface between a virtual concatenation block and a generic framing procedure (GFP) block. More specifically, a multi-bit bus is considered in consideration of a virtual concatenation block operating at a high speed clock. The present invention relates to an interface device between a virtual connection block and a generic framing block suitable for performing an interface with a generic framing procedure block using a minimum control signal.

In general, the interface between a virtual connection and a GFP requires high speed data movement. And it requires data movement at various speeds. Currently, the interface that can accommodate such various needs is the UTOPIA (Universal Test and Operations Physical Interface for ATM) interface.

UTOPIA interface is used in Asynchronous Transfer Mode (ATM), and it is applied to synchronous transmission method such as Synchronous Digital Hierarchy (SDH) or Synchronous Optical Network (SONET) using virtual connection or GFP. Is difficult.

1 is a block diagram of a general UTOPIA interface.

According to FIG. 1, the UTOPIA interface is an interface that connects between the ATM layer 110 and the physical layer 120. This is composed of transmission data (TxData) and reception data (RxData), transmission control signal (TxContro) and reception control signal (RxContro). Meanwhile, a management operation and a joint test action group (JTAG) test are performed through the connection between the physical layer 120 and the microprocessor 130.

The transmission control signal TxContro is as follows.

TxSOC: Indicates the starting point of a cell to be transmitted.

TxEnb: A signal sent from the ATM layer 110 to the physical layer 120 to indicate that data sent is valid.

TxEmpty / TxClav: A signal transmitted from the physical layer 120 to the ATM layer 110 to indicate that the data can no longer be received due to saturation of data that can be received at the physical layer 120.

TxClk: A signal transmitted from the ATM layer 110 to the physical layer 120 and is a clock for synchronization of transmission data (TxData).

The reception control signal RxContro is as follows.

RxSOC: Represents a starting point of a received cell.

RxEnb: A signal transmitted from the ATM layer 110 to the physical layer 120 to indicate that data transmitted is valid.

RxEmpty / RxClav: A signal transmitted from the physical layer 120 to the ATM layer 110 to indicate that there is no data to transmit.

RxClk: A signal transmitted from the ATM layer 110 to the physical layer 120 and is a clock for synchronization of received data (RxData).

By using the signals listed above, the UTOPIA interface can effectively interface signals between the ATM layer 110 and the physical layer 120. The timing of this operation is as shown in FIG.

The unique feature of the UTOPIA interface is that signals such as RxSOC and TxSOC are generated because ATM cells are fixed length. In particular, when using the Cell Level Handshaking method, the starting point of each cell can be indicated as the starting point of RxSOC and TxSOC. These signals can be generated when a valid transmission of 53 bytes is made.

Since the conventional UTOPIA interface was developed for the transmission of the asynchronous transmission method, there are many aspects that are not suitable for use as it is for the interface of the GFP and the virtual connection developed for the synchronous transmission method. In other words, in order to use the UTOPIA interface between the virtual connection and the GFP interface, some signals need to be redefined.

First, considering the RxSOC and TxSOC signals, the virtual connection block cannot generate a signal because the starting point of the frame is unknown. And even if it can be generated, it is not a useful signal. This is because the GFP block that accepts the signal of the virtual connection block has a boundary identification algorithm that knows the starting point of the frame by itself. This situation occurs in the opposite case, namely, when data is transmitted from the GFP block to the virtual connection block. When processing data in a virtual concatenation block, you don't need to know where the data starts. It only needs to be able to tell if it is valid data.

In addition, the RxClav signal is a signal used in cell-level handshaking, which allows one cell to be transmitted at a time. However, since there is no fixed length unit called a cell at the interface of the virtual connection and the GFP, the RxClav signal is not necessary. will be.

And the 'RxPrty' signal, which can be selectively used in the UTOPIA interface, must be an essential signal, not an option. This is because there is no way to check for errors between the virtual connection and the interface of the GFP.

In addition, in case of TxEnb and RxEnb signals, it is possible to determine which is enabled in the physical layer 120 in the UTOPIA interface, but in the interface of virtual connection and GFP, there is no criterion to determine in the virtual connection block, so the TxFull and RxEmpty signals of GFP To determine whether to enable it.

The present invention was created to solve the above-mentioned conventional problems, and an object of the present invention is to use a multi-bit bus while using a minimal control signal in consideration of the fact that the virtual connection block operates at a high speed clock. It is to provide an interface device between a virtual connection block and a generic framing block suitable for performing an interface with a framing procedure block.

In order to achieve the above object, an interface device between a virtual connection block and a generic framing block according to the present invention performs a set error check by attenuating a speed difference between data transmitted from a virtual connection block and data transmitted from its upper layer. A GFP block to be delivered to each destination; It characterized by including a virtual connection block to attenuate the speed difference between the data transmitted from the GFP block and the data transmitted from its upper layer to include a set error check pattern and to deliver to the destination, respectively.

1 is a block diagram of a general UTOPIA interface.

2 is an operation timing diagram of a general UTOPIA interface.

3 is a block diagram of an interface device between a virtual connection block and a generic framing block according to an embodiment of the invention.

4 is a detailed view of the GFP block in FIG.

5 is a detailed view of a virtual connection block in FIG. 3.

Explanation of symbols on the main parts of the drawings

310: GFP block 320: virtual connection block

401, 501: transmit buffer address generator 402, 502: receive buffer address generator

403 and 503: transmission buffer unit 404 and 504: reception buffer unit

405: reception parity check unit 406: reception parity generation unit

505: transmission parity check unit 506: transmission parity generation unit

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of an interface device between a virtual connection block and a generic framing block according to an embodiment of the present invention, FIG. 4 is a detailed view of the GFP block in FIG. 3, and FIG. 5 is a detailed view of the virtual connection block in FIG. to be.

According to FIG. 3, the interface device of the present embodiment includes a GFP block 310 and a virtual connection block 320. Here, the signal flowing from the virtual connection block 320 toward the GFP block 310 is defined as a transmission (Tx), and the reverse signal is defined as a reception (Rx).

As shown in Fig. 4, the GFP block 310 writes the transmission buffer address generator 401 and the GFP receiver buffer 404 to generate the write and read addresses of the GFP side transmit buffer unit 403. And a receive buffer address generator 402 for generating a read address, a transmit buffer unit 403 for attenuating the speed difference between the Tx signal and the Rx signal with respect to the Tx side in the GFP block 310, and the GFP block 310. The reception buffer unit 404 for attenuating the speed difference between the Tx signal and the Rx signal on the Rx side, the reception parity check unit 405 for determining whether there is an error by checking the parity of the received data, and the data to be transmitted. And a receiving parity generating unit 406 for generating an RxPtyEn signal capable of generating parity and indicating a location of the parity.

As shown in FIG. 5, the virtual connection block 320 includes a transmission buffer address generator 501 and a virtual connection side receive buffer unit 504 for generating a write and read address of the virtual connection side transmit buffer unit 503. Reception buffer address generation unit 502 for generating write and read addresses of the transmission line), transmission buffer unit 503 for attenuating the speed difference between the Tx signal and the Rx signal with respect to the Tx side in the virtual connection block 320, and the virtual In the connection block 320, the reception buffer unit 504 for attenuating the speed difference between the Tx signal and the Rx signal on the Rx side, and generates a TxPtyEn signal capable of generating parity for the data to be transmitted and indicating the location of the parity. And a transmission parity check unit 505 for checking the parity of the received data and determining whether there is an error.

In this configuration, the signals used for the interface between the GFP block 310 and the virtual connection block 320 are as follows.

First, the transmission data TxData and the reception data RxData are data to be transmitted by the interface. These data are 8-bit or 16-bit data streams. That is, the clock cycle of the processing side can be reduced by processing interfaces that should be operated at high speed in parallel. If you need a faster interface, you can expand to 32 bits or more.

The RxEmpty and TxFull signals are generated by the transmit buffer unit 403 and the receive buffer unit 404 on the GFP block 310 side. In the case of Tx, the RxEmpty and TxFull signals cannot be received anymore because the buffer is full. In case of Rx, it means that there is no data to send anymore, so it cannot send any data.

The TxEnb and RxEnb signals are signals generated at the virtual connection block 320 and are signals indicating that they can no longer be transmitted or received by the RxEmpty or TxFull signals.

The TxPrtyError and RxPrtyError signals indicate the result of parity check on the transmitted data. The result is sent to the other side and the side receiving the data performs parity check in the same way. If a parity error is found, it generates TxPrtyError and RxPrtyError signals.

In this case, the parity check needs to be performed with a constant length, so a signal indicating the parity check unit is required. TxPrtyEn and RxPrtyEn signals are used to achieve this function. The TxPrtyEn and RxPrtyEn signals are generated every 32 bits and are generated by counters inside the reception parity generator 406 and the transmission parity generator 506.

Referring to FIG. 4, the GFP block 310 includes a plurality of transmission data (TxData) transmitted from the virtual connection block 320 and received data (RxData) transmitted from an upper layer of the GFP block 310 to the destination, respectively. Module exists.

In this case, the transmission buffer unit 403 is different from the speed of the data coming from the virtual connection block 320 and the speed of the data to be delivered to the upper layer, and thus exists for attenuation of the speed difference. The address read and written by the transmission buffer unit 403 is generated by the transmission buffer address generation unit 401. In particular, care must be taken not to cause data overflow or underflow when generating an address, and the TxFull signal is generated by the transmission buffer unit 403 before overflow or underflow occurs.

In the case of the reception buffer unit 404 as well, it transmits a higher layer signal to the virtual connection block 320 to attenuate the speed difference, and generates an RxEmpty signal so that no underflow or overflow occurs. .

The reception parity checker 405 checks parity in units of 32 bits, and if the value is incorrect, transmits a TxPrtyError signal to a higher layer. The TxPrtyEn signal is a signal that cuts each data in 32 bit units. That is, a pulse is generated every 32 bits, and parity is checked when there is a pulse.

The reception parity generator 406 generates parity in units of 32 bits, and generates an RxPrtyEn signal to indicate the generated parity.

In the case of the virtual connection block 320, compared to the GFP block 310 shown in FIG. 4, as shown in FIG. 5, similar to the GFP block 310, the transmission signal and the reception signal are reversed. That is, the role of the Tx side of the GFP block 310 is performed in the Rx side in the virtual connection block 320. However, the difference is that the TxFull and RxEmpty signals generated by the GFP block 310 are used to generate the write / read addresses of the transmit buffer unit 503 and the receive buffer unit 504, and each buffer unit 503 (504). ) To generate the TxEnb and RxEnb signals to prevent underflow and overflow.

The technical standard has not yet been established for the interface between the virtual connection block and the GFP block. By applying the present embodiment, the interface between the virtual connection block and the GFP block can be efficiently performed.

The embodiments described above are within the scope of various changes, modifications, and equivalents of the present invention. Therefore, the present invention is not limited to the description of the examples.

According to the interface device between the virtual connection block and the generic framing block of the present invention, an accurate interface can be configured by using a minimal clock while using a low speed clock using a multi-bit bus to increase the accuracy of the interface. Hardware implementation also has the effect of being simplified.

Claims (5)

A GFP block configured to attenuate a speed difference between data transmitted from a virtual connection block and data transmitted from a higher layer of the virtual connection block, to perform a set error check, and to deliver each to a destination; Virtual connection block and generic, characterized in that it includes a virtual connection block to attenuate the speed difference between the data transmitted from the GFP block and the data transmitted from its upper layer to include a set error check pattern, and to deliver to the destination, respectively Interface device between framing blocks. The method of claim 1, wherein the GFP block, A transmit buffer address generator for generating write and read addresses of the GFP block side transmit buffer; A receive buffer address generator for generating write and read addresses of the GFP block side receive buffer; A transmission buffer unit for attenuating the speed difference between the transmission signal and the reception signal for the transmission side in the GFP block; A reception buffer unit for attenuating a speed difference between a transmission signal and a reception signal for a reception side in a GFP block; A reception parity check unit for checking an error of the received data to determine whether there is an error; And a receiving parity generating unit for generating a parity with respect to data to be transmitted and generating a signal capable of indicating a location of the parity. The method of claim 1, wherein the virtual connection block, A transmission buffer address generator for generating write and read addresses of the virtual connection side transmit buffer; A reception buffer address generation unit for generating write and read addresses of the virtual connection side reception buffer unit; A transmission buffer section for attenuating the speed difference between the transmission signal and the reception signal with respect to the transmission side in the virtual connection block; A reception buffer unit for attenuating a speed difference between a transmission signal and a reception signal for a reception side in a virtual connection block; A transmission parity check unit for generating parity with respect to data to be transmitted and generating a signal capable of indicating a location of the parity; And a transmission parity checker configured to check parity of the received data to determine whether there is an error. 2. An interface apparatus between a virtual connection block and a generic framing block. The method of claim 1, When the data is transmitted, the GFP block generates a signal indicating that the transmission buffer is full and no more data can be received.There is no data in the reception buffer when there is no data to be transmitted. Generates a signal that represents The virtual concatenation block generates a signal informing the data transmitter that it can no longer receive a signal indicating that the transmission buffer of the GFP block is full, and the receiving buffer of the GFP block is deactivated in the virtual concatenation block. By generating a signal informing the data receiving side that it can no longer transmit on a signal indicating that An interface device between a virtual connection block and a generic framing block, which prevents overflow and underflow of a transmission buffer and a reception buffer. The method of claim 1, The set error check is a parity check. The GFP block or the virtual connection block generates a result of performing a parity check on data to be transmitted, sends the check result to the other side, and receives the transmitted data. And the opposite side performs the same parity check as the parity check side, and transmits a signal indicating a parity error to the opposite side.