KR100439216B1 - Apparatus and method for generating read/write address of channel switch in a synchronous transmission system - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides an apparatus and method for generating a read / write address of a channel switch of a synchronous transmission system. The apparatus includes data for storing input data according to a write address and transferring the data to each channel according to the read address. Storage means; Switching information storage means for storing switching information for each channel; A write address generation unit for generating a write address signal suitable for the type of the input data on the basis of an input frame pulse to designate a data recording position of the data storage means; And a read address generator for generating a read address signal of the switching information storage means based on the input frame pulse, and generating a read address signal of the data storage means according to the switching information of the switching storage means. Read / write address of memory for receiving AU-3 / AU-4 signal of TU11, TU12, TUG2, TUG3 or TU3 unit, TU11 / TU12 mixed switching and AU-3 / AU-4 unit switching Will generate

Description

Apparatus and method for generating read / write address of channel switch in a synchronous transmission system}

The present invention relates to the generation of a read / write address of a channel switch of a synchronous transmission system, and more particularly, to an AU-3 / AU-4 in a TU / AU unit switch of a synchronous digital hierarchy (or SDH) transmission system. A synchronous transmission system for generating a read / write address of a memory to receive a signal and perform TU11, TU12, TUG2, TUG3, or TU3 switching, TU11 / TU12 mixed switching, and AU-3 / AU-4 unit switching. A read / write address generator of a channel switch and a method thereof are provided.

In general, the transmission technology forms a stage of development into lesiochronous digital hierarchy (PDH), synchronous optical network (SONET), SDH, and asynchronous transfer module (ATM).

A synchronous optical network (SONET) has a structure of 125 ms, and as a synchronization, only single stage multiplexing and demultiplexing can form independent signals, thereby providing a lot of flexible services.

Recent synchronous transmission systems use a multiplexing scheme according to the SDH standard of the International Telecommunication Union-Telecommunication standardization section (ITU-T). The multiplexing method according to SDH facilitates circuit branching, combining, and circuit distribution functions, and provides various OAMP functions to speed performance monitoring and maintenance between transmission stations and signal paths.

The SDH system generates the STM-1 signal by accepting the signals, mapping them by the virtual box (VC), and processing and multiplexing the hierarchy unit (TU) pointer. The STM-1 signal is 155Mbps, which is multiplexed to produce STM-N (N = 1, 4, 16, 64 ...) signals.

In such a synchronous transmission system, signals output from a station apparatus or a multiplexing apparatus are interconnected between channels in predetermined units. The switch for performing signal switching between channels includes a memory for reading and writing an input signal, and controls the memory with an address signal indicating a writing position in the memory.

The prior art related to the generation of read / write addresses in a synchronous transmission system is patent 1996-0009535 (July 20, 1996). The cited technology applies to SONET based on STS-1 (51.84 Mbps). The block configuration is shown in FIG.

According to Fig. 1, the read / write address generator generates VT counting means 110 for counting an input frame pulse FRP up to a set count value, and converts the signal counted by the VT counting means 110 into a write address signal. A read address converting means (120) comprising at least one read address converting means for converting a record address converting means (120), a count signal obtained from the VT counting means (110) into a read address signal, and outputting the read address signal; After switching information consisting of 4 bits of synchronous transmission channel information, 2 bits of VT group information, and VT channel information is stored, the switching information of the corresponding address is converted into the read address by the read address conversion signal by the read address converting means 130. Switching information memory means comprising at least one data RAM which is converted by the conversion means 130 into a read address signal and outputted 140 and the synchronization stored in the address by the read address signal obtained by converting the input synchronization transmission data into the corresponding address by the recording address signal obtained by the recording address conversion means 120, And synchronous transmission memory means 150 for outputting transmission data.

When the frame pulse is input to the read / write address generator, the VT counting means 110 counts the input frame pulse.

The output of the VT counting means 110 is converted into a write address signal through the write address converting means 120 and input to the synchronous transfer memory means 150 and simultaneously converted into a read address signal through the read address converting means 130. It is input to the data RAM of the switching information memory means 140. The size of the synchronous transmission memory means 150 used here is 64 words * 8 bits * 12 channels, and the size of the switching information memory means 140 is 32 words * 9 bits * 12 channels.

The VT counting unit 110 counts the VT group and the VT number of the input frame pulse air.

Since the synchronous transmission data recorded at the corresponding address of the synchronous transmission memory means 150 by the write address signal of the recording address conversion means 120 is composed of seven VT groups, overhead, R bytes, and the like, each VT The groups are numbered 0 through 6, and the overhead and R bytes are numbered 7. Since each VT group has a structure of 12 columns * 9 rows, numbers 0 to 11 are assigned to each column.

The output of the VT counting means 110 is converted into a write address signal by the write address converting means 120 and input to the synchronous transfer memory means 150. After a predetermined time, the read address of the switching information memory means 140 is passed. The second VT counting means 110 is operated to generate a signal.

The synchronous transmission memory means 150 has a capacity of 64 words for each channel. In the case of VT1.5 switching, the synchronous transmission memory means 150 should have a capacity of 32 words in total with 28 VT1.5 channels and 4 overheads. At this time, in order to store the synchronous transmission data input during the switching operation, 32 words are required again. Therefore, the minimum size of the synchronous transmission memory means 150 is 64 words.

The switching information supplied from the operating system and stored in the switching information memory means 140 by the read address signal of the read address conversion means 130 is stored for each VT group and channel. Each switching information stored is composed of 4-bit synchronous transmission channel information, 2-bit VT group information, and 2-bit VT channel information.

Since the synchronous transmission channel is 12 channels, it is composed of 4 bits, and the VT group information is composed of 35 bits because 8 pieces of VT group, 8 pieces of overhead and R bytes are required. The VT channel information requires two bits because each VT group can obtain up to four VT channels.

Here, the VT group information lacks 2 bits because each of the 3 bits of the VT group information and the 2 bits of the VT channel information must represent the column information of the synchronous transmission data. In order to solve this problem, we introduce a phase concept. This phase refers to the number of each VT channel in the main VT group, and switching only occurs between data having the same phase.

Thus, the VT channel and phase are extracted from the VT number output from the VT counting means 110 so that the VT channel is inputted as a read address signal of the switching information memory means 140, and the phase is output from the switching information memory means 140. The VT channel and the read address converting means 130 are combined to form a VT number of the data to be read and input to the synchronous transfer memory means 150 as a read address signal.

However, such a read / write address generator is adaptable to SONET but not SDH. For example, it was not possible to channel-connect a signal input such as AU-3 / AU-4 of SDH through TU switching or mixed switching.

The present invention was created to solve the above-mentioned conventional problems, and an object of the present invention is to receive the AU-3 / AU-4 signal of the SDH transmission system and to switch the unit of TU11, TU12, TUG2, TUG3 or TU3. The present invention provides a device for generating a read / write address of a channel switch of a synchronous transmission system that generates a read / write address of a memory to enable TU11 / TU12 mixed switching and AU-3 / AU-4 unit switching.

Another object of the present invention is to read a channel switch of a synchronous transmission system in which the input data of each input channel is written to a write address in the synchronous transmission system, and switching for each channel is performed with a read address generated according to switching information for each output channel. It is to provide a method for generating a write address.

Another object of the present invention is to record the SDH management unit data input for each input channel according to the input frame pulse, and then output the data according to the switching information of the output channel read on the basis of the input frame pulse channel switch of the synchronous transmission system It provides a read / write address generation method of.

1 is a block diagram of a read / write device of a synchronous transmission system according to the prior art.

2 is a block diagram of an apparatus for generating read / write addresses of channel switches in a synchronous transmission system according to an embodiment of the present invention.

3 is a configuration diagram of a switching information memory in FIG.

4 is a configuration diagram of a data memory in FIG.

5 is a relationship diagram between a channel and a phase in the TUG2 signal according to the present embodiment;

6 is an output data timing diagram according to the present embodiment.

7 is a flowchart of a method of generating a read / write address of a channel switch of a synchronous transmission system according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

210: data storage means 211: data memory

212: channel selector 213: selection signal generator

220: write address generation unit 221: address generation block

222: multiplexing unit

230: data memory read address generator

240: switching information read address generator

250: switching information storage unit 251: memory

The read / write address generating device of the channel switch of the synchronous transmission system of the present invention for achieving the above object is a write for generating a write address signal for designating a data recording position on the basis of an input frame pulse according to the type of input data. An address generator; A plurality of data memories provided with the number of data input channels and written according to an instruction of the write address generator, and configured to read data written by an instruction of a read address generator; A read address generator for generating a switching information read address signal in the switching information storage means and for generating a read address signal of the data memory in accordance with the switching information; Switching information storage means for storing and providing switching information of input data for each channel; A selection signal generator for receiving switching information from the switching information storage means and outputting a selection signal for controlling an output channel; And a plurality of channel selectors configured to output data input from the data memory to each channel according to the selection signal received by the selection signal generator. The read address generator may be configured based on the input frame pulse. A first read address generator for generating a read address signal of the switching information storage means; And a second read address generator for generating a read address signal of the data storage means by the switching information read from the switching information storage means.

The data storage means stores the input data in the position designated by the write address and reads it from the position designated by the read address. The data storage means can be implemented using a general memory, and uses a plurality of memories in parallel according to the number of input data strings.

The switching information storage means stores information for switching between channels of the SDH system and may be implemented as a memory such as a RAM. The switching information held in the switching information storage means is used as a basis for determining the timing and position of reading out the data recorded in the data storage means.

The write address generator generates a write address based on an input frame pulse used for frame synchronization between input data. The write address indicates a position at which input data is written to the data storage means.

The first read address generator generates a read address for designating a position at which the switching information of the switching information storage unit is read out based on the input frame pulse. This read address is called a switching information read address.

The second read address generator generates a read address of the data storage means by the switching information read from the switching information storage means. This read address is called a data memory read address.

In this configuration, the input data is recorded in each memory in the data storage means in accordance with the write address. The input data can have various types. For example, signal types such as AU-3 or AU-4 of SDH are possible.

The recorded input data is read based on the switching information according to the type of data. Therefore, the switching information storage means should store the switching information for each type of channel-to-channel connection of the transmission system.

The switching information read address is generated based on an input frame pulse and designates a position at which switching information for switching input data is read. The switching information read address is applied to the switching information storage means, and the read switching information is transferred to the second read address generator.

When the second read address generator that receives the switching information generates the data memory read address, input data is read from the data storage means. At this time, the data read from the data storage means is distributed to each channel according to the switching information read from the switching information storage means. As such, switching between input data is performed.

A method of generating a read / write address of a channel switch of a synchronous transmission system of the present invention for achieving the above object comprises the steps of: writing input data from each input channel to data storage means according to a write address; And generating a read address according to the inter-channel switching information and switching the data recorded in the data storage means for each channel.

This address generation method switches data input from multiple input channels of a synchronous transmission system and connects them to multiple output channels. Input data is recorded in the data storage means allocated for each channel, and a write address is used to designate the recording position.

Data recorded in the data storage means is read out for each output channel according to the read address. The read address is formed based on the switching information for each output channel.

A method of generating a read / write address of a channel switch of a synchronous transmission system of the present invention for achieving the above object comprises the steps of: recording SDH management unit data input for each input channel to data storage means in accordance with an input frame pulse; Reading switching information of an output channel by switching information storage means in accordance with an input frame pulse applied as a synchronization reference of the recorded data; And outputting data recorded in the data storage means to a corresponding channel according to the read switching information.

Here, SDH management unit (AU) signals applied to multiple input channels are connected to multiple output channels. The write address of the data storage means is generated in accordance with the input frame pulses and applied to each data memory allocated for each of the plurality of input channels.

Data written according to the write address is read in accordance with the read address. The read address is formed to correspond to the switching information for each channel. For this purpose, the switching information is read from the switching information storage means based on the input frame pulse.

The read address generated at any point in time is specified by outputting switching information of a channel to which data is to be connected at that point in time with an input frame pulse.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

2 is a block diagram of an apparatus for generating a read / write address of a channel switch of a synchronous transmission system according to an exemplary embodiment of the present invention, FIG. 3 is a configuration diagram of a switching information memory in FIG. 2, and FIG. 4 is a data memory in FIG. 5 is a diagram showing the relationship between the channel and the phase in the TUG2 signal according to the present embodiment, and FIG. 6 is an output data timing diagram according to the present embodiment.

According to FIG. 2, input data DATA IN is recorded in the data storage means 210 and output in a predetermined order. The write and read positions of the data are designated by the write address WADD and the read address RADD. In order to perform a series of functions for storing and outputting input data DATA IN, the data storage unit 210 includes a data memory 211, a channel selector 212, and a selection signal generator 213.

The data memory 211 is provided with the number of data input channels, and when the number of input channels is m, m memories are used in parallel.

The channel selector 212 is activated according to the selection signal SEL to output data read from the data memory 211 to each channel. When the number of output channels is n, the channel selector 212 is provided with n / 8.

The selection signal generator 213 applies the selection signal SEL to the channel selection unit 212. The selection signals SEL are generated with reference to the switching information for each channel of the switching information storage means 250, and n / 8 selection signals SEL are required for the n output channels.

The write address generator 220 generates a write address WADD according to the type of the input data DATA IN based on the input frame pulse, and applies the write address WADD to the data memory 211.

3 and 4, in the case where the type of the input data DATA IN is AU-3 or AU-4 according to the SDH definition, the path overhead (POH) and stuffing of the payload according to the type thereof are stuffed. (Stuffing) data is recorded in the address address 11100-11111, and the write address WADD is generated so that the remaining data of the payload can be sequentially recorded for each TU type.

Thus, the write address generator 220 has an address generation block 221 which generates a write address WADD for the case where the type of the input data DATA IN is AU-3 and the case of AU-4, respectively. The two types of write addresses WADD generated by the address generation block 221 are 2: 1 multiplexed by the multiplexer 222. The output of the multiplexer 222 becomes a write address WADD applied to the data memory 211 of each input channel. Therefore, the write address WADD has a plurality of types to match the type of the input data DATA IN.

The switching information storage unit 250 stores switching information of each output channel, and the switching information is read according to the read address RADD. The switching information storage means 250 may be composed of a plurality of memories.

The switching information read address generator 240 receives the information on the output channel based on the configuration information of each channel so that the corresponding output can access the data memory 211 according to each type. Generates a read address RADD. Information about the output channel is the AU type, TU type, whether TU11 / TU12 / TUG / TUG3 switching.

As shown in FIG. 3, the switching information recorded in each memory of the switching information storage means 250 is in a TUG2 group. Thus, the address for reading the switching information storage means 250 is generated by the switching memory read address generator 240 and is generated 28 bytes behind the write address of the data memory 211.

The data memory read address generation unit 230 receives data from the switching memory read address generation unit 240 and the configuration information block (not shown) and outputs the data RDT from the data memory 211 according to each type of the corresponding output. Create a read address (RADD) to read

The data memory 211 is divided into two areas by the Most Significant Bit (MSB). The reason why the memory is divided into two areas is to prevent data loss by storing the input data DATA IN on the other side while one side switches. This MSB value can be varied to switch the role of each region. Therefore, the read address RADD of the data memory 211 is generated by 29 bytes later than the write address WADD.

The AU-3 signal consists of seven TUG2s, overhead, and stuff, and each TUG2 has 12 rows to accommodate four TU11, three TU12, and one TUG2. In each TUG2, the column in which one specific column is located in the AU3 signal is always fixed.

In addition, if only the information about the TU type, the column number located in the TUG2 can be easily identified, and the column number can be known by knowing the TUG2, the TU channel, and the TU type.

And the phase represents how many bytes in each component signal.

According to Fig. 5, the column number in TUG2 is determined as in Equation 1 below.

Column number = (phase * TU constant) + TU channel number

Here, the TU constant has a value of 4 for TU11, 3 for TU12, and 1 for TUG2.

If the column number in the TUG2 is known in this way, the column number in the AU-3 signal can be determined by this. The lower two digits of the column number in the AU-3 signal are read from the data memory 211 read address [1: 0]. Used for The data memory read address [4: 2] uses the TUG2 information of the switching information storage means 250 as it is. The data memory 211 read address [5] is made opposite to the write address [5] to prevent loss of switching data.

In the case of TUG3 (TU3) switching, data can be read sequentially without knowing the column number.

The channel selector 212 selects the output data OUTPUT of the data memory 211 by retiming the switching information received from the switching information storage means 250 to an operating frequency of 51 MHz to be applied to a designated output channel. Used as the selection signal SEL. Data generated at an operating frequency of 51 MHz is retimed and converted to an operating frequency of 6 MHz.

According to Fig. 6, when the selection signals SEL are in the order of 1, 1, 4, 3, 2, 144, ..., the 51 MHz input data string INPUT is the data storage means 210 as the read address. Are written to form temporary data. This temporary data is recorded in the order A, H, ..., S, M, ....

The formed temporary data is read by the write address to form temporary data 2 in each channel selector 212. By retiming this temporary data 2 to 6 MHz and outputting it to each channel, the operating frequency conversion of the output data OUTPUT is performed.

Next, an embodiment of the address generation method according to the present invention will be described.

7 is a flowchart illustrating a method of generating a read / write address of a channel switch of a synchronous transmission system according to an embodiment of the present invention.

Referring to FIG. 7, in order to switch the management unit signal of the SDH for each channel, the input data DATA IN of each input channel is recorded in the data storage means 210 according to the write address (S710).

Here, the input data DATA IN is an AU-n (n = 3,4) signal, and the number of input channels and data memories 211 is m.

The write address is generated based on the input frame pulse, and the write address is created differently depending on whether the input data DATA IN is AU-3 or AU-4.

Subsequently, a read address is generated according to channel-specific switching information (S720).

In order to connect data to a channel, a read address must be generated to match the switching information of the channel. Therefore, channel-specific switching information is required to generate a read address. This switching information is read based on the input frame pulse and applied to the data memory read address generator to generate the read address.

For example, the switching information of the channel may indicate whether the AU type, the TU type, or the TU11 / TU12 / TUG2 / TUG3 is switched. This enables switching of TU11, TU12, TUG2, TUG3, or TU3 units, mixed TU11 / TU12 units, and AU-3 / AU-4 units for incoming AU-3 or AU-4 signals.

This switching of various signal units enables the adaptability to the SDH.

Subsequently, the data recorded in the data storage means 210 is read to the data memory read address and applied to the channel selector 212 (S730).

In response to the input selection signal SEL, the channel selector 212 retimes the data and applies the data to the corresponding channel (S740).

The retiming causes the output data (DATA OUT) to 6MHz to the input data (DATA IN) 51MHz.

The selection signal SEL is formed according to the switching information output in accordance with the input frame pulse. For example, in order to generate the selection signal, a switching information read address is generated in accordance with an input frame pulse, and the switching information is read from the switching information storage means. Then, the selection signal may be generated as output data through the corresponding channel according to the read switching information.

The embodiments described above are within the scope of various changes, modifications, and equivalents of the present invention. Therefore, the present invention is not limited to the description of the examples.

According to an apparatus and method for generating a read / write address of a channel switch of a synchronous transmission system according to the present invention, a TU11 / TU12, TUG2, TUG3 or TU3 unit switching and TU11 / This has the effect of generating a read / write address of the memory for TU12 mixed switching and AU-3 / AU-4 unit switching.

In addition, the present invention has an effect of reducing the size of the memory, the number of gates, and the access time by distributing and outputting an address using 51.84 Mbps as an operating frequency without directly using an address generated at an operating frequency of 6.48 Mbps.

In addition, the present invention has the effect of implementing a signal distribution switch of the transmission system with a minimum of memory.

Claims (20)

A write address generator for generating a write address signal for specifying a data write position based on an input frame pulse according to the type of input data; A plurality of data memories provided with the number of data input channels and written according to an instruction of the write address generator, and configured to read data written by an instruction of a read address generator; A read address generator for generating a switching information read address signal in the switching information storage means and for generating a read address signal of the data memory in accordance with the switching information; Switching information storage means for storing and providing switching information of input data for each channel; A selection signal generator for receiving switching information from the switching information storage means and outputting a selection signal for controlling an output channel; And a plurality of channel selectors for outputting data input from the data memory to each channel according to the selection signal received by the selection signal generation unit. delete The method of claim 1, wherein the channel selector, A read / write address generating device of a channel switch of a synchronous transmission system, characterized in that retiming at a set operating frequency when outputting data for each channel. The method of claim 1, wherein the switching information storage means, And a plurality of memories in which switching information for each channel is recorded. The switching information is read based on an input frame pulse applied together with input data input to the input channel, and the read switching information is read from the read address. And a read / write address generating device of a channel switch of a synchronous transmission system, characterized in that it is applied to a generating section and said selection signal generating section. The method of claim 4, wherein each memory of the switching information storage means, A device for generating a read / write address of a channel switch of a synchronous transmission system, wherein switching information is recorded in units of TUG2 when the input data is AU-n (n = 3,4) of the SDH. The method of claim 1, wherein the write address generation unit, A plurality of address generation blocks for generating a write address so as to correspond to each type of input data when there are a plurality of types of input data; And a multiplexing unit for multiplexing the address signals generated in the respective address generation blocks to form one output and applying the data to the data storage means as a write address signal. Generating device. The address generation block of claim 6, wherein the address generation block of the write address generation unit comprises: When the input signal is AU-3 or AU-4 based on the input frame pulse, the path overhead and the stuffing data of the payload are recorded at a specific address of each memory of the data storage means. Read / write address generating device of a channel switch of a synchronous transmission system, wherein the write addresses are generated such that the remaining data of the data can be sequentially written to each address of each memory of the data magnetic field means according to each TU type. . The apparatus of claim 1, wherein the read address generator comprises: A first read address generator configured to generate a read address signal of the switching information storage means based on the input frame pulse; And a second read address generator for generating a read address signal of the data storage means by the switching information read from the switching information storage means. Writing input data from each input channel to data storage means according to a write address; And generating a read address according to switching information for each channel to switch data recorded in the data storage means for each channel. The method of claim 9, wherein the write address, When a plurality of types of the input data input to a plurality of input channels are generated in a plurality of types so as to correspond to the type, characterized in that to specify the location where the input data is recorded in each memory of the data storage means; Method of generating read / write address of channel switch of synchronous transmission system. The method of claim 9 or 10, wherein the recording in the data storage means is performed. Each memory is divided into a plurality of areas, and the areas are sequentially switched to a data reading area and a data recording area, and the written data is read in the data reading area and the write address is read in the data recording area. And writing the input data according to the channel switch. The method of claim 11, When the input data recorded in each memory of the data storage means is AU-n (N = 3,4) of the SDH, the write address specifies the path overhead of the payload of the input data and the stuffing data of the memory. And write to an address address, and other data of the payload to be sequentially written to addresses other than the specified address address. The method of claim 12, And other data in the payload of the input data are recorded in a set group unit. The method of claim 9, wherein the switching information for each channel, It is composed of the switching information of the output channel and stored in each memory of the switching information storage means for each channel, characterized in that whether the output channel performs the AU type, TU type, TU11 / TU12 / TUG2 / TUG3 switching A method of generating a read / write address of a channel switch of a synchronous transmission system. delete delete delete delete delete delete