KR100423064B1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR100423064B1 KR100423064B1 KR10-2002-0015394A KR20020015394A KR100423064B1 KR 100423064 B1 KR100423064 B1 KR 100423064B1 KR 20020015394 A KR20020015394 A KR 20020015394A KR 100423064 B1 KR100423064 B1 KR 100423064B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 셀 영역과 주변회로 영역으로 정의된 반도체 기판 상에 터널 산화막 및 도전막을 형성하는 단계와, 상기 셀 영역의 상기 도전막을 패터닝 하는 단계와, 전체 구조 상부에 유전막을 형성하는 단계와, 상기 주변회로 영역의 상기 유전막을 등방성 식각하는 단계와, 상기 주변회로 영역의 상기 도전막을 식각하되 상기 터널 산화막에 대한 상기 도전막의 식각선택비가 높은 식각조건으로 비등방성 식각하는 단계 및 상기 주변회로 영역의 상기 터널 산화막을 제거하는 단계를 포함하는 반도체 소자의 제조 방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, forming a tunnel oxide film and a conductive film on a semiconductor substrate defined by a cell region and a peripheral circuit region, patterning the conductive film in the cell region, and overall structure. Forming an dielectric layer thereon, isotropically etching the dielectric layer of the peripheral circuit region, and etching the conductive layer of the peripheral circuit region, but anisotropic to an etching condition having a high etching selectivity of the conductive layer with respect to the tunnel oxide layer A method of manufacturing a semiconductor device includes etching and removing the tunnel oxide layer in the peripheral circuit region.
본 발명에 의하면, 플래시메모리 소자의 제조 공정 중 주변회로 영역의 유전막 및 도전막 식각시 발생하는 유전막 리프팅(lifting) 현상과 하부 반도체 기판의 손실(loss)을 방지할 수 있다.According to the present invention, it is possible to prevent the dielectric film lifting phenomenon and the loss of the lower semiconductor substrate generated during the etching of the dielectric film and the conductive film in the peripheral circuit region during the manufacturing process of the flash memory device.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 0.18㎛ 테크(tech) 이하의 플래시메모리 소자에 있어서 주변회로 영역의 유전막 및 도전막을 식각하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of etching a dielectric film and a conductive film in a peripheral circuit region in a flash memory device of 0.18 μm tech or less.
플래시메모리(flash memory)가 가지는 고유한 특징 중의 하나는 전원이 차단이 되어도 데이터를 보전할 수 있는 것이다. 따라서 공정상의 입장에서 바라볼 때, 셀 영역에서는 플로팅게이트로서 데이터의 쓰기 및 소거를 위한 동작을 해야 하기 때문에 유전막 형성이 필요하고, 셀을 제외한 주변회로영역에서는 트랜지스터로 동작시키기 위해서 유전막이 필요로 하지 않는 공정상의 특성이 있다.One of the unique features of flash memory is that data can be preserved even when the power is cut off. Therefore, from the process point of view, since the cell region needs to operate as a floating gate for writing and erasing data, dielectric film formation is required, and in the peripheral circuit area except the cell, a dielectric film is required to operate as a transistor. Does not have process characteristics.
도 1a 내지 도 1c는 종래의 기술에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 1a를 참조하면, 종래의 셀 영역(a)과 주변회로 영역(b)으로 구분된 반도체 기판(10)에 플래시메모리용 플로팅 게이트(floating gate)를 형성하기 위해 소자 분리막(도시 되지 않음)을 형성한 다음 전체 구조 상부에 터널 산화막(tunnel oxide ; 20) 및 도전막(30)을 증착한다. 셀 영역(a)에 도전막(30) 패터닝 공정을실시하여 도전막(30) 패턴을 형성한다. 이때 패터닝 공정 상의 특징으로 인한 셀 영역(a)과 주변회로 영역(b)의 도전막은 10% 이상의 두께 편차가 나타난다.Referring to FIG. 1A, an isolation layer (not shown) is formed to form a floating gate for a flash memory in a semiconductor substrate 10 divided into a cell region a and a peripheral circuit region b. After the formation, a tunnel oxide 20 and a conductive layer 30 are deposited on the entire structure. The conductive film 30 patterning process is performed in the cell region a to form the conductive film 30 pattern. At this time, the thickness of the conductive film of the cell region (a) and the peripheral circuit region (b) due to the characteristics of the patterning process is more than 10%.
도 1b 및 도 1c를 참조하면, 전체구조 상부에 유전막(40)을 형성한다. 주변회로 영역(b)에 저전압 트랜지스터(low voltage transistor) 및 고전압 트랜지스터(high voltage transistor)를 형성하기 위해 셀 영역(a)을 제외한 주변회로 영역(b)의 유전막(40), 도전막(30) 및 터널 산화막(20)을 비등방성 식각장비에서 건식식각공정을 실시하여 제거한다.1B and 1C, the dielectric film 40 is formed on the entire structure. In order to form a low voltage transistor and a high voltage transistor in the peripheral circuit region b, the dielectric film 40 and the conductive film 30 in the peripheral circuit region b except the cell region a are formed. And the tunnel oxide film 20 is removed by performing a dry etching process in an anisotropic etching equipment.
도 2은 종래의 기술에 의해 주변회로 영역을 식각함으로써 유전막 리프팅 현상이 나타난 SEM(Scanning Electron Microscope) 사진이다.2 is a scanning electron microscope (SEM) photograph showing a dielectric film lifting phenomenon by etching a peripheral circuit region by a conventional technique.
도 3는 종래의 기술에 의해 주변회로 영역을 식각함으로써 하부 반도체 기판에 손상이 발생한 SEM 사진이다.3 is a SEM photograph of damage to a lower semiconductor substrate by etching a peripheral circuit region by a conventional technique.
도 2 및 도 3을 참조하면, 종래의 기술에 따라 비등방성 장비를 이용한 식각을 실시하게 되면, 도전막의 두께 편차로 인해 주변회로 영역(b)의 유전막 및 도전막 제거시 반도체 기판에 손상(attack)을 준다. 또한 도전막 측벽(side)에 존재해 있던 적층 구조의 유전막이 후속 습식식각 공정과 후처리 공정을 거치면서 리프팅(lifting) 현상을 유발하게 되고 이로 인해 게이트 라인 형성공정에서 게이트라인 브리지(bridge)를 유발하게 된다. 따라서 소자의 신뢰성 및 수율 저하를 가져온다.Referring to FIGS. 2 and 3, when etching using anisotropic equipment is performed according to the related art, the semiconductor substrate is damaged when the dielectric film and the conductive film of the peripheral circuit region b are removed due to the thickness variation of the conductive film. ). In addition, the dielectric layer of the stacked structure existing on the sidewalls of the conductive layer causes a lifting phenomenon during the subsequent wet etching and post-treatment processes, thereby causing the gate line bridge to be removed in the gate line forming process. Will cause. Therefore, the reliability and yield of the device are lowered.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 주변회로 영역의 유전막과 도전막을 이원화된 식각장비에서 식각함으로써 도전막 측벽에 잔류하는 질화막에 의해 발생되는 리프팅 현상을 개선할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problem, the present invention provides a method of manufacturing a semiconductor device capable of improving the lifting phenomenon caused by the nitride film remaining on the sidewall of the conductive film by etching the dielectric film and the conductive film in the peripheral circuit region by the dual etching equipment. The purpose is to provide.
또한 도전막 식각시 식각 조건을 변경하여 도전막과 산화막의 높은 식각 선택비를 확보함으로써 하부 반도체 기판의 손상을 방지할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing damage to a lower semiconductor substrate by changing an etching condition during etching of a conductive film to secure a high etching selectivity between the conductive film and the oxide film.
도 1a 내지 도 1c는 종래의 기술에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 2은 종래의 기술에 의해 주변회로 영역을 식각함으로써 유전막 리프팅 현상이 나타난 SEM(Scanning Electron Microscope) 사진이다.2 is a scanning electron microscope (SEM) photograph showing a dielectric film lifting phenomenon by etching a peripheral circuit region by a conventional technique.
도 3는 종래의 기술에 의해 주변회로 영역을 식각함으로써 하부 반도체 기판에 손상이 발생한 SEM 사진이다.3 is a SEM photograph of damage to a lower semiconductor substrate by etching a peripheral circuit region by a conventional technique.
도 4a 내지 도 4e는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다.4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 5는 본 발명에 따른 이원화된 식각장비를 사용하여 주변회로영역의 유전막 및 도전막을 식각한 후의 SEM사진이다.5 is a SEM photograph after etching the dielectric film and the conductive film in the peripheral circuit region by using the binary etching equipment according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10, 100 : 반도체 기판 20, 110 : 터널 산화막10, 100: semiconductor substrate 20, 110: tunnel oxide film
30, 120 : 도전막 40, 140 : 유전막30, 120: conductive film 40, 140: dielectric film
42, 130, 150 : 포토레지스트 패턴42, 130, 150: photoresist pattern
본 발명에 따른 셀 영역과 주변회로 영역으로 정의된 반도체 기판 상에 터널 산화막 및 도전막을 형성하는 단계와, 상기 셀 영역의 상기 도전막을 패터닝 하는 단계와, 전체 구조 상부에 유전막을 형성하는 단계와, 상기 주변회로 영역의 상기 유전막을 등방성 식각하는 단계와, 상기 주변회로 영역의 상기 도전막을 식각하되 상기 터널 산화막에 대한 상기 도전막의 식각선택비가 높은 식각조건으로 비등방성 식각하는 단계 및 상기 주변회로 영역의 상기 터널 산화막을 제거하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 제조 방법을 제공한다.Forming a tunnel oxide film and a conductive film on a semiconductor substrate defined by a cell region and a peripheral circuit region according to the present invention, patterning the conductive film in the cell region, forming a dielectric film over the entire structure, Isotropically etching the dielectric layer in the peripheral circuit region, etching the conductive layer in the peripheral circuit region, but anisotropically etching the etching condition of the conductive layer to the tunnel oxide with a high etching selectivity, and etching the conductive layer in the peripheral circuit region. It provides a method for manufacturing a semiconductor device comprising the step of removing the tunnel oxide film.
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 더욱 상세히 설명하기로 한다. 그러나 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예들은 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 도면상에서 동일 부호는 동일한 요소를 지칭한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.
도 4a 내지 도 4e는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다.4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 4a를 참조하면, 셀 영역(a)과 주변회로 영역(b)으로 분리된 반도체 기판(100)에 셀로우 트랜치 아이솔레이션(Shallow Trench Isolation; 이하 'STI'라함)공정을 실시하여 소자 분리막(도시되지 않음)을 형성한 다음 터널 산화막(110)과 도전막(120)을 형성한다. 도전막(120) 상에 제 1 감광막을 도포한 후 리소그라피공정을 실시하여 제 1 감광막 패턴(130)을 형성한다. 상기의 제 1 감광막 패턴(130)을 식각마스크로 하는 식각공정을 실시하여 셀 영역(a)의 도전막(120)을 패터닝한다.Referring to FIG. 4A, a shallow trench isolation (“STI”) process is performed on a semiconductor substrate 100 separated into a cell region a and a peripheral circuit region b. And the tunnel oxide film 110 and the conductive film 120 are formed. After applying the first photoresist film on the conductive film 120, a lithography process is performed to form the first photoresist film pattern 130. An etching process using the first photoresist layer pattern 130 as an etching mask is performed to pattern the conductive layer 120 of the cell region a.
또는 셀프 얼라인(Self Align) STI공정을 적용하여 반도체 기판(100) 상부에 터널 산화막(110)과 도전막(120)을 증 한 후 화학적 기계적 연마(Chemical Mechanical Polishing; 이하 'CMP'라함)공정을 수행하여 셀 영역(a)의 도전막(120)을 패터닝한다. 이때 주변회로 영역(b)은 제 1 감광막(130)으로 도포함으로써 도전막(120)이 식각되지 않게 한다.Alternatively, a Self Align STI process is applied to increase the tunnel oxide film 110 and the conductive film 120 on the semiconductor substrate 100, and then chemical mechanical polishing (hereinafter, referred to as 'CMP') process. Next, the conductive film 120 of the cell region a is patterned. In this case, the peripheral circuit region b is coated with the first photosensitive layer 130 so that the conductive layer 120 is not etched.
도 4b 및 도 4c를 참조하면, 제 1 감광막패턴(130)을 제거한 후 전체 구조 상부에 유전막(140)을 증착한다. 이때 유전막(140)은 산화막과 질화막의 적층구조로 형성되는데 본 실시예에서는 산화막/질화막/산화막/질화막이 적층된 구조로 각각 40/60/40/35Å의 두께로 형성한다. 상기 유전막 상에 제 2 감광막을 도포한 후리소그라피공정을 실시하여 셀 영역(a)을 차폐시키는 제 2 감광막 패턴(150)을 형성한다. 제 2 감광막 패턴(150)을 식각마스크로 이용하여 등방성 식각 장비에서 유전막(140)을 제거하고, 비등방성 식각 장비에서 도전막(120)을 제거한다.4B and 4C, after removing the first photoresist layer pattern 130, the dielectric layer 140 is deposited on the entire structure. At this time, the dielectric film 140 is formed of a stacked structure of an oxide film and a nitride film. In this embodiment, the oxide film / nitride film / oxide film / nitride film is stacked in a thickness of 40/60/40/35 40. A second photoresist pattern 150 is formed to shield the cell region a by performing a lithography process by coating a second photoresist on the dielectric layer. The dielectric layer 140 is removed from the isotropic etching equipment and the conductive layer 120 is removed from the anisotropic etching equipment using the second photoresist pattern 150 as an etching mask.
구체적으로 셀 영역(a)을 제외한 주변회로 영역(b)의 유전막(140) 제거를 위해 등방성 식각 특성을 갖는 ECR(Electron Cyclotron Resonance) 또는 헬리콘(Helicon) 소스 플라즈마를 사용하는 ATC(After Treatment Chamber) 타입의 장비에서 150 내지 250Å의 타겟으로 건식 식각을 실시한다.Specifically, ATC (After Treatment Chamber) using an ECR (Electron Cyclotron Resonance) or Helicon (Helicon) source plasma having an isotropic etching characteristic to remove the dielectric layer 140 of the peripheral circuit region (b) except for the cell region (a) Dry etching is performed on a 150-250Å target on the) type of equipment.
예를 들어 도전막(120)과 유전막(140)을 각각 1000Å과 200Å의 두께로 형성하게 될 경우 도전막(120) 측벽에 형성되는 유전막의 두께는 1200Å이 된다. 따라서 비등방성 식각 장비로 유전막(140)을 제거하기 위해서는 식각 타겟을 1200Å으로 실시하여야 하지만 등방성 식각 장비에서는 식각 타겟을 200Å만으로 진행하여도 쉽게 유전막(140)을 제거할 수 있다. 식각 타겟의 차이로 볼때 1000Å이상의 차이가 유발되고 또한 후속 습식 식각 후 질화막 리프팅 현상을 방지할 수 있다.For example, when the conductive film 120 and the dielectric film 140 are formed to have thicknesses of 1000 kPa and 200 kPa, respectively, the thickness of the dielectric film formed on the sidewalls of the conductive film 120 becomes 1200 kPa. Therefore, in order to remove the dielectric layer 140 using anisotropic etching equipment, the etching target should be performed at 1200 Å. However, in the isotropic etching equipment, the dielectric film 140 can be easily removed even if the etching target is only 200 Å. The difference between the etching targets causes a difference of more than 1000 mm 3 and also prevents the nitride film lifting phenomenon after the subsequent wet etching.
도전막(120)은 비등방성 식각 특성을 갖는 ICP(Inductively Coupled Plasma) 타입의 플라즈마를 사용하는 TCP(Transformer Coupled Plasma), IPS(Inductively-coupled Pararell-plate Semiconducting Chamber) 또는 DPS(Decoupled Plasma Source) 장비에서 식각된다. 이때 도전막(120)과 산화막(110)의 선택비가 100:1 내지 300:1이 되도록 한다.The conductive layer 120 is a transformer coupled plasma (TCP), an inductively-coupled pararell-plate semiconducting chamber (IPS), or a decoupled plasma source (DPS) device using an inductively coupled plasma (ICP) type plasma having anisotropic etching characteristics. Etched at At this time, the selectivity of the conductive film 120 and the oxide film 110 is 100: 1 to 300: 1.
도전막(120) 식각시 사용되는 가스의 화학적 조합을 Cl2/O2/N2에서 HBr/O2/He로 변경함으로 산화막(110)의 선택비를 개선한다. 즉, HBr/O2가스의 비를 100:1 내지 200:1로 하고, 활성가스로는 50 내지 200Sccm의 He를 사용함으로써 높은 식각 선택비를 갖게 한다. 이로써 주변회로 영역(b)의 도전막(120)을 완전히 제거할 수 있고, 높은 식각 선택비에 의해 하부의 터널 산화막(110)이 배리어 역활을 하여 도전막(120)의 두께 편차에 의한 하부 반도체 기판(100)의 손상을 개선할 수 있다.The selectivity of the oxide film 110 is improved by changing the chemical combination of the gas used during the etching of the conductive film 120 from Cl 2 / O 2 / N 2 to HBr / O 2 / He. That is, the ratio of HBr / O 2 gas is set to 100: 1 to 200: 1, and 50 to 200 Sccm of He is used as the active gas to have a high etching selectivity. As a result, the conductive film 120 in the peripheral circuit region b can be completely removed, and the lower tunnel oxide film 110 acts as a barrier due to a high etching selectivity, and the lower semiconductor is caused by the thickness variation of the conductive film 120. Damage to the substrate 100 may be improved.
도 4d 및 도 4e를 참조하면, 잔류하는 터널 산화막(110) 제거를 위해 습식 식각공정을 실시한 후 셀 영역(a)의 제 2 감광막 패턴(150)을 제거하고 게이트 산화막 증착을 위한 전처리 세정 공정을 실시한다. 습식 식각은 100 : 1 내지 300 : 1의 BOE(Buffered Oxide Etch) 또는 HF를 이용하여 실시한다. 또는 습식 식각공정을 실시하지 않고 제 2 감광막 패턴(150)을 제거한 후 전처리 세정공정을 실시하여 터널 산화막(110)을 제거한다. 전처리 세정공정시 셀 영역(a)의 유전막(140)의 손실을 최소화하기 위해 BN 또는 B를 이용하여 실시한다.4D and 4E, after the wet etching process is performed to remove the remaining tunnel oxide layer 110, the second photoresist pattern 150 of the cell region a is removed, and a pretreatment cleaning process for depositing the gate oxide layer is performed. Conduct. Wet etching is performed using BOE (Buffered Oxide Etch) or HF of 100: 1 to 300: 1. Alternatively, the tunnel oxide film 110 is removed by performing a pretreatment cleaning process after removing the second photoresist pattern 150 without performing a wet etching process. In the pretreatment cleaning process, BN or B is used to minimize the loss of the dielectric layer 140 in the cell region a.
도 5는 본 발명에 따른 이원화된 식각장비를 사용하여 주변회로영역의 유전막 및 도전막을 식각한 후의 SEM사진이다.5 is a SEM photograph after etching the dielectric film and the conductive film in the peripheral circuit region by using the binary etching equipment according to the present invention.
도 5를 참조하면, 도 2와 비교하여 유전막 리프팅 현상이 나타나지 않았고, 도 3과 비교하여 하부 반도체 기판의 침식이 현저하게 줄어들었다.Referring to FIG. 5, the dielectric film lifting phenomenon did not appear in comparison with FIG. 2, and erosion of the lower semiconductor substrate was significantly reduced in comparison with FIG. 3.
상술한 바와 같이, 본 발명은 주변회로 영역의 유전막을 등방성 식각장비에서 그리고 도전막을 비등방성 식각장비에서 제거함으로써 도전막 측벽에 잔류하는 질화막에 의해 발생되는 리프팅 현상을 개선할 수 있다.As described above, the present invention can improve the lifting phenomenon caused by the nitride film remaining on the sidewall of the conductive film by removing the dielectric film in the peripheral circuit region from the isotropic etching equipment and the conductive film from the anisotropic etching equipment.
또한 도전막 식각시 화학적 조합을 HBr/O2/He로 변경하여 도전막과 산화막의 식각 선택비를 높임으로써 도전막의 두께 편차에 의한 반도체 기판의 침식을 방지할 수 있다.In addition, the chemical combination may be changed to HBr / O 2 / He during etching of the conductive layer to increase the etching selectivity of the conductive layer and the oxide layer, thereby preventing erosion of the semiconductor substrate due to thickness variation of the conductive layer.
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| US4799991A (en) * | 1987-11-02 | 1989-01-24 | Motorola, Inc. | Process for preferentially etching polycrystalline silicon |
| JPH05218350A (en) * | 1991-10-11 | 1993-08-27 | Micron Technol Inc | Method for formation of array of nonvolatile memory devices using floating-gate transistors by working semiconductor wafer and for formation of peripheral region provided with cmos transistor |
| JPH06310734A (en) * | 1993-04-23 | 1994-11-04 | Nippon Steel Corp | Method of manufacturing semiconductor memory device |
| KR0155581B1 (en) * | 1994-05-10 | 1998-10-15 | 문정환 | Semiconductor device using floating gate and method of forming the same |
| KR100255512B1 (en) * | 1996-06-29 | 2000-05-01 | 김영환 | Flash memory device manufacturing method |
| US6177312B1 (en) * | 1998-03-26 | 2001-01-23 | Advanced Micro Devices, Inc. | Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4799991A (en) * | 1987-11-02 | 1989-01-24 | Motorola, Inc. | Process for preferentially etching polycrystalline silicon |
| JPH05218350A (en) * | 1991-10-11 | 1993-08-27 | Micron Technol Inc | Method for formation of array of nonvolatile memory devices using floating-gate transistors by working semiconductor wafer and for formation of peripheral region provided with cmos transistor |
| JPH06310734A (en) * | 1993-04-23 | 1994-11-04 | Nippon Steel Corp | Method of manufacturing semiconductor memory device |
| KR0155581B1 (en) * | 1994-05-10 | 1998-10-15 | 문정환 | Semiconductor device using floating gate and method of forming the same |
| KR100255512B1 (en) * | 1996-06-29 | 2000-05-01 | 김영환 | Flash memory device manufacturing method |
| US6177312B1 (en) * | 1998-03-26 | 2001-01-23 | Advanced Micro Devices, Inc. | Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device |
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