KR100416971B1 - Random keystream generation apparatus and method for use in a cryptosystem - Google Patents

Abstract

An apparatus and method are disclosed for generating a random keystream using a parallel mobile linear feedback shift register (PS-LFSR). The device's PS-LFSR is composed of n storage stages, where k is the smallest integer greater than n divided by m, where each substorage is The m-bit parallel binary data inputted from the sub storage units are simultaneously stored, and the m-bit parallel binary data stored therein are output according to the system clock. The buffer consists of m storage stages for simultaneously storing and outputting m-bit parallel binary data output from the last substorage of the shift register. The m feedback connections are provided with the outputs of the substores corresponding to a predetermined primitive polynomial and the output of the buffer, perform an operation according to the primitive polynomial, respectively, and output a result of each operation as bits of the keystream.

Description

Device and method for generating random keystream for use in cryptographic system {RANDOM KEYSTREAM GENERATION APPARATUS AND METHOD FOR USE IN A CRYPTOSYSTEM}

The present invention relates to an encryption system, and more particularly, to an apparatus and method for generating a random keystream for encrypting input information using a linear feedback shift register (LFSR).

With the recent rapid development of communication networks, the data to be processed is gradually transforming from text / voice data into multimedia data such as video conferencing and video data. Accordingly, the encryption algorithm used in the communication system has also been required to design high cost, high speed and high reliability.

In general, cipher systems can be classified into stream ciphers, block ciphers, and public key ciphers. The block cipher is classified into an Electronic CodeBook (ECB) mode, a Cipher FeedBack (CFB) mode, a Cipher Block Chaining (CBC) mode, and an Output FeedBack (OFB) mode according to an application method. The ECB mode generates a block output from a secret key and a data encryption standard (DES) function for an input of a block size. The CFB mode feeds back an output ciphertext to the input. In the CBC mode, an exclusive-OR (XOR) operation is performed on the current ciphertext block and the next plaintext block for authentication of transmission and reception data, and then inputted to the block cipher to generate a new output. This is an iterative process of XOR to get the final authentication value. In this CBC mode, since the final authentication value is changed when forging data, authenticity can be distinguished. The OFB mode changes the block cipher itself to a random stream generator and applies it as a stream cipher.

Since the block ciphers of the four schemes are all vulnerable to channel errors or have other problems in terms of practical use of actual cipher communication, some countermeasures are required. Specifically, in the ECB mode, one or more bit errors in one ciphertext block only affect the decryption of that block. In the CFB mode, one bit error in one ciphertext block affects the decryption of that block and the next block. In the CBC mode, one bit error in one ciphertext block affects all subsequent blocks. The OFB mode, introduced to reduce the error spread of the block cipher, can reduce the spread by the number of input feedback bits (this number is smaller than the block size) and, in the best case, essentially feed back one bit to prevent the spread. However, the 1-bit OFB mode reduces network processing power because the data processing rate is reduced by a block size twice that of the normal ECB mode.

In addition, since public key cryptography is slow in processing, it is not suitable for high-speed data processing, and there is a disadvantage in that an error is spread throughout the block as in ECB mode. In addition, stream ciphers have no channel error spread, and the security (non-level) factor is mathematically guaranteed in several respects, and high-speed processing is possible, but this method can also facilitate encryption processing according to high-speed communication service. Is questionable.

The linear feedback shift register (LFSR), the logic combination circuit in the form of a nonlinear coupling function, the full adder, the multiplexer, etc. have. In particular, LFSR is an almost essential element in cryptographic systems because it determines not only the variety of sizes but also the invisibility factor of the key sequence period. As shown in FIG. 1, the LFSR generates a binary key stream while synchronously moving one bit in accordance with an externally input system clock. The generated key stream is provided to an encryption combiner (not shown) and used to convert plain text into cipher text. The generation rate of the key stream is determined by the system clock and the delay time of the internal circuit.

The LFSR as shown in FIG. 1 described above is an element that is essentially used in a process for generating or encrypting a pseudo noise code. In particular, high-speed LFSR processing is needed in view of the trend that the object to be encrypted is gradually changed to data for multimedia service. However, since the LFSR structure according to the prior art enables only one bit shift in one system clock, it can be said that the structure is not suitable for high-speed LFSR processing.

Accordingly, an object of the present invention is to provide an apparatus and method for rapidly generating a random keystream for use in an encryption system or a spread spectrum communication system.

Another object of the present invention is to provide an apparatus and method for implementing a LFSR that operates at a high speed to reduce time delay in encryption processing requiring a large amount of computation and real-time processing.

It is still another object of the present invention to provide an apparatus and method for eliminating error spreading over a communication channel in an encryption system or a spread spectrum communication system.

In order to achieve these objectives, the present invention provides a random keystream generation that includes a parallel shift linear feedback shift register (PS-LFSR) capable of m-bit shifting within one system clock and allowing the final output to be m-bit generated. Suggest a device. The PS-LFSR of the device is composed of n storage stages for storing n bits of binary data, divided into k sub-storage units, where k is the least integer greater than n divided by m, Each of the sub-storage units simultaneously stores the m-bit parallel binary data input from the previous sub-storage units and outputs the stored m-bit parallel binary data according to the system clock. The buffer consists of m storage stages for simultaneously storing and outputting m-bit parallel binary data output from the last substorage of the shift register. The m feedback connections are provided with the outputs of the substores corresponding to a predetermined primitive polynomial and the output of the buffer, perform an operation according to the primitive polynomial, respectively, and output a result of each operation as bits of the keystream.

1 is a block diagram of an apparatus for generating a random keystream using a linear feedback shift register according to the prior art.

FIG. 2 is a block diagram of an apparatus for generating a random keystream using a (n, m) parallel movable linear padback shift register (PS-LFSR) according to an embodiment of the present invention. FIG.

3 is a block diagram of an apparatus for generating a random keystream using a (40, 8) linear feedback shift register according to an embodiment of the present invention.

4 is a block diagram of an apparatus for generating a random keystream using a (39, 8) linear feedback shift register according to an embodiment of the present invention.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that reference numerals and like elements among the drawings are denoted by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In the following, the present invention is a parallel mobile linear feedback shift register that combines the advantages of stream ciphers and block ciphers under the two objectives of ultra-high speed cryptographic system and design of cryptographic system that can eliminate error spread through communication channel. We propose a parallel shifting linear feedback shift register (PS-LFSR) and a device for generating a random keystream including the same. That is, the embodiment of the present invention enables high-speed encryption processing by mixing the m-bit parallel processing function of the block cipher while maintaining the degree of the level of the stream cipher and the function of preventing the error spreading. In the stream cipher, the LFSR is shifted by one bit per clock, and the present invention, which has improved this, can move m bits per clock. In addition, the present invention proposes a general form of the m-bit parallel nonlinear coupling function that can be output of multiple bits at the same time as a block cipher by complementing the disadvantage of the nonlinear coupling function processed by one bit.

2 is a block diagram of an apparatus for generating a random keystream using (n, m) PS-LFSR according to an embodiment of the present invention.

Referring to FIG. 2, the keystream generation device is for generating a random keystream of m bits, and includes a PS-LFSR 110, a buffer 120, and a feedback connection unit 130. The PS-LFSR 110 is composed of n storage stages for storing n bits of binary data. The PS-LFSR 110 is composed of n storage stages in the same manner as the LFSR 10 according to the related art shown in FIG. 1. However, the n storage stages constituting the PS-LFSR 110 are divided into a predetermined number (k) of sub storage units, and each of the divided sub storage units is composed of m storage stages arranged in parallel. It is done. This configuration allows for moving, in parallel, storing and outputting m bits of binary data in parallel within one period of the system clock. Here, assuming that the set number k is given by n and m, k is determined as the smallest integer greater than n divided by m. For example, when n = 40 and m = 8, k is determined as 5. In this case, the sub storage units are configured of the same number (m) of storage stages. As another example, when n = 39 and m = 8, k is determined as the minimum integer 5 greater than 4.875, the number divided by 8 at 39. In this case, at least one of the sub storage units includes a different number of storage stages than the other sub storage units. The keystream generation apparatus according to these examples is illustrated in FIGS. 3 and 4 to be described later. The keystream generation device may be implemented in software or hardware, and may be used in a keystream generator of a communication system using a stream cipher. In the embodiment of the present invention, the keystream generating device will be described as being used as a keystream generator in a communication system using a stream cipher, but a pseudo-noise generator in a spread spectrum communication system. Note that it can be used for).

Referring back to FIG. 2, the PS-LFSR 110 is divided into k sub storage units 111 to 115. The sub-storage unit 111 performs the first m storage stages (n-1, n-2, n-3, n-4, n-5, n-6, ..., nm) of the n storage stages. It is composed. The sub storage 113 is composed of m storage stages (3m-1, ..., 2m + 5, 2m + 4, 2m + 3, 2m + 2, 2m + 1, 2m) among the n storage stages. . The sub storage unit 114 is composed of m storage stages (2m-1, ..., m + 5, m + 4, m + 3, m + 2, m + 1, m) of the n storage stages. . The sub storage unit 115 is composed of the last m storage stages (m-1, ..., 5, 4, 3, 2, 1, 0) of the n storage stages. Storage stages constituting each of the sub storage units 111 to 115 are arranged in parallel. Accordingly, each of the sub storage units 111 to 115 simultaneously stores the m-bit parallel binary data input from the previous sub storage units and outputs the stored m-bit parallel binary data according to a system clock.

The buffer 120 stores m storage stages (-m,-(m-1), ...,-for simultaneously storing and outputting m-bit parallel binary data output from the last sub storage 115 of the PS-LFSR 110. 5, -4, -3, -2, -1). At this time, the first storage stage (-m) of the buffer 120 is not used. This is because the value stored in the first storage stage (-m) of the buffer 120 is not used in the feedback connection unit 130 described later. That is, the buffer 120 may consist of (m-1) storage stages. This buffer 120 is for storing values of storage stages to be used in the next period of the system clock.

The feedback connection unit 130 includes m feedback connections 131 to 133. The feedback connections 131 to 133 are used to perform operations according to a predetermined primitive polynomial for generating a key stream, respectively. The outputs of the sub storage units 111 to 115 corresponding to the predetermined primitive polynomial and the buffers are respectively performed. An output of 120 is provided, each operation according to the primitive polynomial is performed, and a corresponding operation result is output as each bit of the keystream. The feedback connections 131 to 133 may be implemented as a plurality of exclusive OR (XOR) operators. When an arbitrary primitive polynomial is defined for the feedback connection 131, the feedback connection 132 performs an operation according to the primitive polynomial according to the result of shifting the primitive polynomial defined for the feedback connection 131 to the left by one bit, and the feedback connection 133 Performs an operation according to the primitive polynomial according to a result of shifting the primitive polynomial defined for the feedback connection 131 to the left by m bits. Therefore, assuming that the feedback connection 131 is provided with values stored in the 0th, 1st, 2nd, ..., (n-1) th storage stages, the feedback connection 132 is (-1) th, 0 Input the values stored in the first, first, ..., and (n-2) th storage stages to perform a corresponding operation, and the feedback connection 133 is-(m-1) th and-(m-2) th Input the values stored in the-,-(m-3) th, ..., and (n-m + 1) th storage stages to perform a corresponding operation. The feedback connection 131 outputs a first feedback value, the feedback connection 132 outputs a second feedback value, and the feedback connection 133 outputs an mth feedback value. The feedback values output from the feedback connections 131 to 133 are input to corresponding storage stages of the sub storage 111 of the PS-LFSR 110 to be used for subsequent keystream generation. The first feedback value (feedback 1) output from the feedback connection 131 is input to the (nm) storage stage of the sub storage unit 111, and the second feedback value (feedback 2) output from the feedback connection 132 is the sub storage unit 111. Is input to the (nm-1) storage stage, and the mth feedback value output from the feedback connection 133 is input to the (n-1) storage stage of the sub storage 111. When feedback values according to the result calculated by all feedback connections 131 to 133 are outputted, these feedback values are generated as a m-bit keystream for encryption processing.

The operation of generating a random keystream of m bits by the apparatus for generating a random keystream shown in FIG. 2 is performed as follows.

(Process 1) The PS-LFSR 110, which consists of n storage stages for storing n bits of binary data, has k sub-storage units 111 to 115, where k is a minimum integer greater than n divided by m. Divided into.

(Process 2) Each of the sub storage units 111 to 115 simultaneously stores the m-bit parallel binary data input from the previous sub storage units and outputs the stored m-bit parallel binary data according to the system clock.

(Process 3) The buffer 120 buffers m-bit parallel binary data output from the last sub storage 115 of the PS-LFSR 110.

(Process 4) The feedback connection 131 is provided with the outputs of the sub storage units 111 to 115 corresponding to a predetermined primitive polynomial, performs an operation according to the primitive polynomial, and outputs an initial feedback result value (feedback 1).

(Step 5) Generate (m-1) primitive polynomials by shifting the primitive polynomial one bit to the left. The (m-1) primitive polynomials thus generated are primitive polynomials for use in the (m-1) feedback connections 132-133.

(Process 6) The feedback connections 132 to 133 are each provided with the output of the sub storages 111 to 115 and the buffered value of the buffer 120 corresponding to the (m-1) primitive polynomials, respectively. (M-1) feedback results (feedback 2 to feedback m) are output by performing the operation according to each of the? Primitive polynomials.

(Step 7) The m feedback result values are output as respective bits of the m-bit keystream.

As described above, in the random keystream generation apparatus including the PS-LFSR according to the embodiment of the present invention, a parallel path is configured to allow all bits to be parallel shifted in units of m bits. In the feedback connection (tab), the m bundle XOR combination operation is also performed, and the result is simultaneously provided to the rightmost array register 111. In the next system clock (time), the rightmost array is shifted from the left array to the left array in m-bit block units, and then to the left in parallel by the block size (m). After all, this random key strram generator is a generator that generates m-bit (or less) output simultaneously after moving m bits in one clock. It can be seen that the same as the general LFSR as shown in 1. In addition, the PS-LFSR is m-times faster than the LFSR that generates the bit-by-bit output, and the hardware complexity may increase somewhat due to the high speed, but the recent development of integrated circuit technology will not be a big problem.

3 is a block diagram of an apparatus for generating a random keystream using (40, 8) PS-LFSR according to an embodiment of the present invention. The random keystream generation apparatus according to this embodiment includes a (40,8) PS-LFSR in which n = km (k is an integer) as a design example of the (n, m) PS-LFSR.

Referring to FIG. 3, the keystream generation device is for generating an 8-bit random keystream and includes a PS-LFSR 210, a buffer 220, and a feedback connection unit 230. The PS-LFSR 210 is composed of 40 storage stages for storing 40 bits of binary data. The 40 storage stages constituting the PS-LFSR 210 are divided into a predetermined number (k = 5) of sub storage units, and each of the divided sub storage units includes 8 storage stages arranged in parallel. It features. This configuration allows 8-bit binary data to be moved in parallel, i.e., stored and output simultaneously, within one period of the system clock.

The PS-LFSR 210 is divided into five sub storage units 211 to 215. In this case, each of the sub storage units 211 to 215 includes the same number (m = 8) of storage stages. The sub storage unit 211 includes first eight storage stages 39 to 32 of the 40 storage stages. The sub storage unit 212 includes eight storage stages 31 to 24 of the 40 storage stages. The sub storage unit 213 includes eight storage stages 23 to 16 of the 40 storage stages. The sub storage unit 214 is composed of eight storage stages 15 to 8 of the 40 storage stages. The sub storage unit 215 is composed of the last eight storage stages 7 to 0 of the 40 storage stages. Storage stages constituting each of the sub storage units 211 to 215 are arranged in parallel. Accordingly, each of the sub storage units 211 to 215 simultaneously stores 8-bit parallel binary data input from previous sub storage units and outputs the stored 8-bit parallel binary data according to a system clock.

The buffer 220 includes eight storage stages (-8, -7, -6, -5, -4) for simultaneously storing and outputting 8-bit parallel binary data output from the last sub storage 215 of the PS-LFSR 210. , -3, -2, -1). At this time, the first storage stage (-8) of the buffer 220 is not used. That is, the buffer 220 may consist of seven storage stages. This buffer 220 is for storing values of respective storage stages to be used in the next period of the system clock.

The feedback connection unit 230 includes eight feedback connections 231 to 233. The feedback connections 231 to 233 are used to perform operations according to a predetermined primitive polynomial to generate a keystream, respectively. The outputs of the sub storage units 211 to 215 corresponding to the predetermined primitive polynomial and the buffer are respectively performed. An output of 220 is provided, each operation according to the raw polynomial is performed, and a corresponding operation result is output as each bit of the keystream. When an arbitrary primitive polynomial is defined for the feedback connection 231, the feedback connection 232 performs an operation according to the primitive polynomial according to the result of shifting the primitive polynomial defined for the feedback connection 231 to the left by one bit, and the feedback connection 233 Performs an operation according to the primitive polynomial according to the result of shifting the primitive polynomial defined for the feedback connection 231 to 8 bits to the left. Therefore, assuming that the values stored in the 0th, 1st, 2nd, ..., 35th storage stages are provided to the feedback connection 231, the feedback connection 232 is (-1) th, 0th, 1st. The corresponding operation is performed by inputting values stored in the 34th storage stages, and the feedback connection 233 stores the values stored in the -7th, -6th, -5th, ..., 28th storage stages. Enter these to perform the corresponding operation. That is, the raw polynomial given for the feedback connection 231 is s (40 + t) = s (35 + t) ^ s (2 + t) ^ s (1 + t) ^ s (t) where ^ is exclusive. Suppose that a logical OR (XOR: eXclusive OR) operation is performed.), And the feedback connection 232 is a raw polynomial s (39 + t) = s (34 + t) ^ s (1 + t) ^ s (t) ^. perform the operation according to s (-1 + t), and the feedback connection 233 is a raw polynomial s (33 + t) = s (28 + t) ^ s (-5 + t) ^ s (-6 + t) Perform the operation according to ^ s (-7 + t).

The feedback connection 231 outputs a first feedback value, the feedback connection 232 outputs a second feedback value, and the feedback connection 233 outputs an eighth feedback value. The feedback values output from the feedback connections 231 through 233 are input to corresponding storage stages of the sub storage unit 211 of the PS-LFSR 210 and used for generation of a subsequent key stream. The first feedback value (feedback 1) output from the feedback connection 231 is input to 32 storage stages of the sub storage unit 211, and the second feedback value (feedback 2) output from the feedback connection 232 is 33 of the sub storage unit 211. The eighth feedback value input to the storage stage and output from the feedback connection 233 is input to the 39 storage stage of the sub storage unit 211. When feedback values are outputted as a result of the operation by all feedback connections 231 to 233, these feedback values are generated as an 8-bit keystream for encryption processing.

4 is a block diagram of an apparatus for generating a random keystream using (39, 8) PS-LFSR according to an embodiment of the present invention. The random keystream generation apparatus according to this embodiment includes a (39,8) PS-LFSR in which n? Km (k is an integer) as a design example of the (n, m) PS-LFSR.

Referring to FIG. 4, the keystream generation device is for generating an 8-bit random keystream, and includes a PS-LFSR 310, a buffer 320, and a feedback connection unit 330. The PS-LFSR 310 is composed of 39 storage stages for storing 39 bits of binary data. 39 storage stages constituting the PS-LFSR 310 are divided into sub-storage units by a predetermined number (k = 5).

The PS-LFSR 310 is divided into five sub storage units 311 to 315. In this case, at least one of the sub storage units includes a different number of storage stages than the other sub storage units. For example, the sub storage 311 is composed of seven storage stages, and the remaining sub storages 312 to 315 are composed of eight storage stages. The first sub storage unit 311 of the PS-LFSR 310 is composed of seven storage stages, and the remaining four sub storage units 312 to 315 are composed of eight storage stages. The sub storage unit 311 includes first seven storage stages 38 to 32 of the 39 storage stages. The sub storage unit 312 includes eight storage stages 31 to 24 of the 39 storage stages. The sub storage unit 313 includes eight storage stages 23 to 16 of the 39 storage stages. The sub storage unit 314 is composed of eight storage stages 15 to 8 of the 39 storage stages. The sub storage unit 315 is composed of the last eight storage stages 7 to 0 of the 39 storage stages. Storage stages constituting each of the sub storage units 311 to 315 are arranged in parallel. Accordingly, each of the sub storage units 311 to 315 simultaneously stores 7-bit or 8-bit parallel binary data input from previous sub-storage units and stores the stored 7-bit or 8-bit parallel binary data according to the system clock. Output

The buffer 320 includes eight storage stages (-8, -7, -6, -5, -4) for simultaneously storing and outputting 8-bit parallel binary data output from the last sub storage unit 315 of the PS-LFSR 310. , -3, -2, -1). At this time, the first storage stage (-8) of the buffer 320 is not used. That is, the buffer 320 is a buffer consisting of seven storage stages. This buffer 320 is for storing values of respective storage stages to be used in the next period of the system clock.

The feedback connection unit 330 includes eight feedback connections 331 to 333. The feedback connections 331 to 333 are for performing calculation according to a predetermined primitive polynomial to generate a keystream, respectively, and output the buffers and the buffers of the sub storage units 311 to 315 corresponding to the predetermined primitive polynomial. An output of 320 is provided, each operation according to the primitive polynomial is performed, and a corresponding operation result is output as each bit of the keystream. When an arbitrary primitive polynomial is defined for the feedback connection 331, the feedback connection 332 performs an operation according to the primitive polynomial according to the result of shifting the primitive polynomial defined for the feedback connection 331 to the left by one bit, and the feedback connection 333 Performs an operation according to the primitive polynomial according to the result of shifting the primitive polynomial defined for the feedback connection 331 to 8 bits to the left. Therefore, assuming that the feedback connection 331 is provided with values stored in the 0th, 1st, 2nd, ..., 38th storage stages, the feedback connection 332 is (-1) th, 0th, 1st. Input the values stored in the 37th storage stages to perform a corresponding operation, and the feedback connection 333 stores the -7th, -6th, -5th, ..., 30th storage stages. Enter these to perform the corresponding operation. That is, the raw polynomial defined for the feedback connection 331 is Assume that the feedback connection 332 is a primitive polynomial And the feedback connection 333 is a primitive polynomial Perform the operation according to

The feedback connection 331 outputs a first feedback value, the feedback connection 332 outputs a second feedback value, and the feedback connection 333 outputs an eighth feedback value. The feedback values output from the feedback connections 331 to 333 are input to corresponding storage stages of the sub storage unit 311 of the PS-LFSR 310 to be used for generating a later keystream. The first feedback value (feedback 1) output from the feedback connection 331 is input to 31 storage stages of the sub storage unit 312, and the second feedback value (feedback 2) output from the feedback connection 332 is 32 of the sub storage unit 311. The eighth feedback value input to the storage stage and output from the feedback connection 333 is input to the 38 storage stage of the sub storage unit 311. When feedback values according to the result calculated by all feedback connections 331 to 333 are outputted, these feedback values are generated as an 8-bit keystream for encryption processing.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. For example, in a specific embodiment of the present invention, the random keystream generation device has been described as an example of being used as a keystream generator of a stream cipher, but the random keystream generation device may be used equally as a pseudo noise generator of a spread spectrum communication system. Could be. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

As described above, the present invention has an advantage of significantly reducing time delay in real time processing, large processing, and encryption processing requiring a large amount of computation through LFSR operating at high speed.

Claims (8)

An apparatus for generating a random key stream of m bits for use in a cryptographic system, n storage stages for storing n bits of binary data, divided into k sub-stores, where k is the least integer greater than n divided by m, and each of the sub-stores A parallel shift linear feedback shift register (PS-LFSR) for simultaneously storing m-bit parallel binary data inputted from previous sub storages and outputting m-bit parallel binary data according to a system clock; A buffer comprising m storage stages for simultaneously storing and outputting m-bit parallel binary data output from the last sub storage of the shift register; M feedback connections for receiving the output of the substores corresponding to a predetermined primitive polynomial and the output of the buffer, performing operations according to the primitive polynomial, and outputting operation results as respective bits of the keystream. The device, characterized in that. 2. The apparatus of claim 1, wherein the first bit of the buffer is not used. The apparatus as claimed in claim 1, wherein the sub storage units are configured of the same number of storage stages. 2. The apparatus as claimed in claim 1, wherein at least one of the sub storage units comprises a different number of storage stages than the remaining sub storage units. A method of generating an m-bit random keystream for use in a cryptographic system, Partition the linear feedback shift register (PS-LFSR), consisting of n storage stages for storing n bits of binary data, into k sub-stores, where k is the smallest integer greater than n divided by m. Process, Simultaneously storing the m-bit parallel binary data inputted from the previous sub-storage units in each of the sub-storage units and outputting the stored m-bit parallel binary data according to a system clock; Buffering m-bit parallel binary data output from the last sub storage of the shift register through a buffer; Receiving an output of the sub storage units corresponding to a predetermined primitive polynomial, performing an operation according to the primitive polynomial, and outputting an initial feedback result value; Generating (m-1) primitive polynomials by shifting the primitive polynomial one bit left; The output of the substores corresponding to the (m-1) primitive polynomials and the value buffered in the buffer are provided, and the operation according to each of the (m-1) primitive polynomials is performed (m-1). Outputting) feedback results, And outputting the m feedback results as respective bits of the keystream. 6. The method of claim 5, wherein the first bit of the buffer is not used. 6. The method as claimed in claim 5, wherein the sub storage units are configured of the same number of storage stages. 6. The method as claimed in claim 5, wherein at least one of the sub storage units comprises a different number of storage stages than the remaining sub storage units.