KR100386627B1 - Circuit for testing semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory test circuit capable of improving test efficiency, comprising: a sequence controller for outputting an internal control signal by an external input signal and a refresh signal, and an address of a memory cell to be tested by the sequence controller; An address generator for outputting a signal, a signal generator for outputting a test control signal, a test address signal, and a test data signal by the internal control signal and the address signal, an output signal of the signal generator, and a control signal during normal operation A memory unit for outputting corresponding data according to the output of the multiplexer for selectively outputting a signal, a test data signal of the signal generator, and output data of the memory unit to determine whether there is an abnormality of data, and to detect a memory defect. Department, the comparison unit and A result generator which outputs the information value of the defective cell and the row and column addresses to the outside so as to determine the location of the memory cell in which the defect is detected by the output signal of the dress generator; And a defect counter unit for feeding back a defect non-repair signal to the sequence control unit when the count is exceeded.

Description

Semiconductor Memory Test Circuits {CIRCUIT FOR TESTING SEMICONDUCTOR MEMORY}

The present invention relates to a semiconductor memory test circuit, and more particularly to a semiconductor memory test circuit that can simplify the memory test process and save time.

In general, a semiconductor memory test process is a process of inspecting the characteristics and defects of a completed semiconductor device, and in the wafer test step, a pre-test is performed to test whether a cell having a bit defect or a decoder defect is repaired. The pre-repair test, the post-repair test that determines whether the repair is complete and the finished product for the repaired cell, and passes based on the results of the post-repair test Pre-burn in test to test the packaged cells in the assembly line and test them in the assembly line, and whether the cells and peripheral circuits of the device are operating normally and whether any abnormality has occurred in each device parameter. Post-burn in test to determine whether or not.

However, although the method of testing embedded DRAM is an embedded DRAM, it is necessary to create a path for accessing the DRAM externally for testing and to create unnecessary pins in normal logic operation to test the DRAM even after being packaged.

In addition, to test the Memory Merged on Logic (MML) chip with embedded DRAM, the test equipment and logic test equipment must be alternately tested in wafer state and package state, which makes the process complicated.

To solve this problem, a built-in circuit that directly tests DRAM, called built in self test (BIST), is used, which can replace many parts of a conventional semiconductor memory test step.

The BIST may be divided into a BIST for go / nogo, a BIST for diagnosis, a built in self diagnosis (BISD), and a built in self repair (BISR) according to which part can be replaced in a memory test step.

The go / nogo BIST can be used for post-repair test and package state test by simply determining the defect / defect of DRAM. The diagnosis BIST can also be used for pre-repair test for the go / nogo BIST function. It is attached to the function.

In addition, BISD is a function that can be directly interfaced to the repair equipment in the pre-repair test, BISR can be repaired itself.

Hereinafter, a semiconductor memory test circuit according to the related art will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a conventional semiconductor memory test circuit.

As shown in FIG. 1, the conventional semiconductor memory test circuit includes a sequence control unit 1 that receives a predetermined signal from an external source and outputs an internal control signal and a test end signal (bist-done). And a refresh counter 2 for automatically outputting a refresh signal to the sequence controller 1 at predetermined time intervals, and an internal control signal output from the sequence controller 1. Receives an address generator 3 for outputting an address signal of a memory cell to be tested, an internal control signal output from the sequence controller 1, and an output signal of the address generator 3. A signal generator 4 for outputting a test control signal t-cont, a test address signal t-add, and a test data signal t-data for the pattern, and output from the signal generator 4 Test control Signal t-cont, test address signal t-add, test data signal t-data and externally input control signal e-cont, address signal e-add, data signal e- a multiplexer 5 that receives data and selectively outputs the data, a memory unit 6 that receives an output signal of the multiplexer 5 and outputs data dout corresponding thereto, and the signal generator 4 And a comparator 7 for comparing the test data signal t-data, which is an output signal, with the output data dout of the memory unit 6, determining whether there is an abnormality of data, and detecting a memory defect.

The operation of the conventional semiconductor memory test circuit as described above is as follows.

First, the sequence controller 1 receives a test start signal (bist-en) and a clock signal (clock) from the outside to control the test start and proceeds the test with a set algorithm, and then ends the test at the end of the test ( bist-done).

In addition, during the test, an internal control signal required for the internal circuits is generated to control an address generation time, pattern data generation, and comparison detection time.

When the operation time of the test circuit exceeds the refresh period of the memory to be tested, the refresh counter 2 refreshes the refresh signal to the sequence controller 1 so that the refresh is automatically performed every predetermined time. Output

The address generator 3 receives an internal control signal for controlling the address generation time of the sequence controller 1 and generates an address signal so that the memory cells to be tested can be sequentially tested.

The signal generator 4 receives an internal control signal output from the sequence controller 1 and an address signal of the address generator 3 and a test control signal that matches the DRAM pattern for each sequence. (t-cont), the test address signal t-add, and the test data signal t-data are output.

The multiplexer 5 applies a test control signal t-cont, a test address signal t-add, and a test pattern signal t-data generated in an internal circuit during a memory test to the memory, and during normal operation. Outputs a control signal (e-cont), an address (e-add), and data (e-data) which are input signals of an external logic circuit.

Subsequently, the memory unit 6 receiving the output signal of the multiplexer 5 outputs the data dout corresponding thereto.

The comparison unit 7 compares the test data signal t-data, which is the output signal of the signal generator 4, and the output data dout of the memory unit 6, and determines whether there is an abnormality of data. Detect memory faults.

However, the conventional semiconductor memory test circuit as described above has the following problems.

For testing the memory, a large number of pins are used to apply addresses and data from the outside of the chip, which increases the package and greatly reduces the integration of the circuit.

In addition, complex processes are time consuming and efficient.

The present invention is to solve such a problem of the semiconductor memory test circuit of the prior art, and in determining whether the memory for storing and outputting data is abnormal, it is possible to report information indicating the position of the defective cell. It is an object of the present invention to provide a semiconductor memory test circuit that can improve test efficiency by adding a function and a function of determining whether a defective cell is repaired.

1 is a block diagram of a semiconductor memory test circuit of the prior art

2 is a block diagram of a semiconductor memory test circuit according to the present invention.

3 is a block diagram illustrating a result generator of a semiconductor memory test circuit according to the present invention.

Figure 4 is a graph showing the results of the test using the semiconductor memory test circuit according to the present invention

Explanation of symbols for the main parts of the drawings

21: sequence control unit 22: refresh counter unit

23: address generator 24: signal generator

25: multiplexer 26: memory unit

27: comparison unit 28: result generator

29: defect counter part 31, 41: low defect counter part

32, 42: column defect counter 33, 43: AND logic

The semiconductor memory test circuit according to the present invention for achieving the above object includes a sequence controller for outputting an internal control signal by an external input signal and a refresh signal, and an address signal of a memory cell to be tested by the sequence controller. An address generator for outputting, a signal generator for outputting a test control signal, a test address signal, and a test data signal by the internal control signal and the address signal, an output signal of the signal generator, and a control signal during normal operation A memory unit for outputting data corresponding thereto according to the output of the multiplexer outputted by the multiplexer; a comparison unit for detecting a memory defect by determining whether data is abnormal by comparing test data signals of the signal generator and output data of the memory unit; , The comparison unit and the address As a result of outputting the information value of the defective cell and the row and column addresses to the outside so as to determine the position of the memory cell in which the defect is detected by the output signal of the generator, the defective cell is received by receiving the output signal of the comparator. And a defect counter unit for feeding back a defect non-resistance signal to the sequence control unit when the countable capacity exceeds the rescueable capacity.

Hereinafter, a semiconductor memory test circuit of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram illustrating a semiconductor memory test circuit according to the present invention.

As shown in FIG. 2, the configuration of the semiconductor memory test circuit according to the present invention receives a test start signal (bist-en) and a clock signal (clock) from an external control signal and a test end signal (bist-done). A sequence control unit 21 for outputting a signal, a refresh counter unit 22 for automatically outputting a refresh signal to the sequence control unit 21 at a predetermined time, and the sequence An address generator 23 that receives an internal control signal output from the controller 21 and outputs an address signal of a memory cell to be tested, an internal control signal output from the sequence controller 21, and A signal generator 24 which receives the output signal of the address generator 23 and outputs a test control signal t-cont, a test address signal t-add, and a test data signal t-data; Remind signal The test control signal t-cont, the test address signal t-add, the test data signal t-data, the control signal e-cont and the address signal e that are output from the unit 24 -add), a multiplexer 25 for receiving and selectively outputting a data signal (e-data), a memory unit 26 for receiving an output signal of the multiplexer 25 and outputting data corresponding thereto; The comparison unit 27 which compares a test data signal t-data, which is an output signal of the signal generator 24, and an output data dout of the memory unit 26, determines whether there is an abnormality of data, and detects a memory defect. And an information signal of the defective cell so that the position of the memory cell where the defect is detected can be determined by receiving the output signal of the comparing unit 27 and the address signal of the address generating unit 23. Row and column addresses are external to the clock signal When the result generator 28 and the output signal of the comparator 27 are output, the defect cells are counted, and when the capacity for remedy is exceeded, the defect control signal is fed back to the sequence controller 21. The defect counter part 29 is comprised.

The result generator 28 may include a data register (not shown) that stores information of a defective cell (fail-io), and a row address register (not shown) that stores addresses separately for each row and column. And a plurality of defective cells by inputting a column address register (not shown), an output signal of the data register, an output signal of the row address register and the column address register, a fault signal, and a clock signal. It consists of a shift register (not shown) which serially outputs information.

The operation of the semiconductor memory test circuit according to the present invention as described above is as follows.

First, the sequence controller 21 receives a test start signal (bist-en) and a clock signal (clock) from the outside to control the test start, and proceeds the test with a set algorithm, and then ends the test at the end of the test ( bist-done).

In addition, during the test, an internal control signal required for the internal circuits is generated to control an address generation time, pattern data generation, and comparison detection time.

When the operation time of the test circuit exceeds the refresh period of the memory to be tested, the refresh counter 22 refreshes the refresh signal to the sequence controller 21 so as to automatically refresh every predetermined time. Output

The address generator 23 receives an internal control signal for controlling the address generation time of the sequence controller 21 and generates an address signal so that the memory cells to be tested can be sequentially tested.

The signal generator 24 receives an internal control signal output from the sequence controller 21 and an address signal of the address generator 23 and a test control signal that matches the DRAM pattern for each sequence. (t-cont), the test address signal t-add, and the test data signal t-data are output.

The multiplexer 25 applies a test control signal (t-cont), a test address signal (t-add), and a test pattern signal (t-data) generated in an internal circuit during a memory test to the memory, and during normal operation. Outputs a control signal (e-cont), an address (e-add), and data (e-data) which are input signals of an external logic circuit.

Subsequently, the memory unit 26 receiving the output signal of the multiplexer 25 outputs the data dout corresponding thereto.

The comparison unit 27 compares the test data signal t-data which is the output signal of the signal generator 24 and the output data dout of the memory unit 26 to determine whether there is an abnormality of data. A mutual comparison method is used to detect memory defects.

Here, when the comparison unit 27 proceeds with a normal test algorithm and encounters a defect bit of a defective cell, the comparison unit 27 feeds back a defect signal to the sequence controller 21 to test a normal pattern. Stop it.

In the result generator 28, when the defect signal is turned on, the clock signal is converted into the row and column addresses of the defective cells inputted in parallel and the fail-io information value of the defective cell. According to (clock), it outputs serially externally and determines the position of a defective cell.

In addition, the information of the combined cell output to the outside may be output in a number of bits depending on the external pin pad margin.

The defect counter unit 29 counts the number of defect cells generated and determines that the defect of the memory cannot be repaired when the capacity of the defective cell is exceeded. The defect counter signal is fed back to the sequence controller 21. To end the test.

3 is a block diagram illustrating a coupling counter unit of a semiconductor memory test circuit according to a first embodiment of the present invention, and FIG. 4 is a block diagram illustrating a coupling counter unit according to a second embodiment of the present invention.

As shown in FIG. 3, when the coupling counter unit 29 according to the first exemplary embodiment of the present invention receives a defect signal and calculates the number of defective cells in a row direction to exceed the retrievable capacity, A row defect counter unit 31 for outputting a low defect excess signal and a column for outputting a column defect excess signal when the number of defective cells in the column direction is calculated by receiving a defect signal (fail) as an input and exceeding a remedable capacity AND logic section 33 for receiving a fault counter 32, an output signal of the row fault counter 31 and an output signal of the column fault counter 32, combining the signals, and outputting a defect relief signal. It consists of.

Here, the row defect counter unit 31 and the column defect counter unit 32 have an initial value of 0, and when a defect signal is input, the row defect counter unit 31 starts to count the number of defective cells. do.

When the number of defective cells exceeds the capacity that can be remedied by the row defect counter unit 31, a row defect excess signal is output, and when a subsequent defect cell occurs, the column defect counter unit 32 operates. do.

The column defect counter unit 32 outputs a column defect excess signal when the number of defective cells exceeds a capacity that can be remedied.

In addition, the AND logic unit 33 which receives the row and column defect excess signals output from the row and column defect counter units 31 and 32, respectively, determines that the memory is impossible by combining the two signals. The sequence control unit 21 feeds back a defect incapacity signal to stop the test.

As shown in FIG. 4, the defect counter unit 29 according to the second embodiment of the present invention is for preventing the defective cells from being counted in duplicate for row and column addresses. The sequence controller 21 When the address is increased, the address increase signal indicating the address increase direction, the address signal in the row direction, and the defect signal (fail) are received as inputs, the number of defective cells in the row direction is calculated, A row defect counter 41 for outputting a defect excess signal, an address increment signal, an address signal in the column direction, and a defect signal can be received as inputs, and the number of defective cells in the column direction can be calculated and repaired. When the capacity is exceeded, the column defect counter unit 42 outputs a column defect excess signal, and the output signal and column defect counter unit 42 of the row defect counter unit 41. AND logic section 43 for receiving the output signal of the combination of the signals and outputs the defect relief impossibility signal.

In this case, when the row defect counter unit 41 operates, if the column address changes first, the defective cell is not counted more than once unless the row address changes.

In addition, when the column defect counter 42 operates, if the row address changes first, the defective cell is not counted more than once unless the column address is changed.

Therefore, it is possible to determine whether or not the relief by accurately counting the number of overlapping defective cells per row and column.

The semiconductor memory test circuit of the present invention as described above has the following effects.

By serially outputting information values and addresses of defective cells input in parallel using a result generator, it is possible to determine not only whether the memory cell is defective but also the position of the defective cell.

In addition, it is possible to determine whether the memory is to be rescued by using a defect counter unit that counts the number of defective cells.

Therefore, there is an effect of improving the test efficiency by simplifying the memory test process and saving time.

Claims (6)

A sequence controller which outputs an internal control signal by an external input signal and a refresh signal, An address generator for outputting an address signal of a memory cell to be tested by the sequence controller; A signal generator for outputting a test control signal, a test address signal, and a test data signal by the internal control signal and the address signal; A memory unit for outputting data corresponding to the output signal of the signal generator and a multiplexer for selectively outputting a control signal during normal operation; A comparison unit for comparing a test data signal of the signal generator and output data of the memory unit to determine whether there is an abnormality of data to detect a memory defect; A result generator which outputs the information value of the defective cell and the row and column addresses to the outside so as to determine the location of the memory cell where the defect is detected by the output signals of the comparator and the address generator; A row defect counter unit and a column defect counter unit for receiving a output signal of the comparator and counting defective cells in a row and a column direction and outputting a low defect over signal and a column defect over signal when the capacity for remedy is exceeded; And a fault counter section comprising an AND logic section for receiving the output signals of the fault counter section and the column fault counter section, combining the two signals, and outputting a non-resistance signal. The semiconductor memory test circuit of claim 1, wherein the sequence control unit stops the memory test when a defect repair impossible signal is fed back. delete The semiconductor memory test circuit according to claim 1, wherein the defect counter unit sequentially operates a row defect counter unit and a column defect counter unit to count defective cells. The method of claim 1, wherein the defect counter unit receives an address increase signal, an address signal, and a defect signal that are output signals of the sequence control unit, counts defect cells for each row and column, and exceeds the resolvable capacity. A row defect counter unit and a column defect counter unit for outputting a defect over-signal, respectively, and an AND logic unit for receiving the output signals of the row defect counter unit and the column defect counter unit, combining the signals, and outputting an irresistible signal; A semiconductor memory test circuit. 6. The method of claim 5, wherein the row defect counter unit and the column defect counter unit fail to count the defective cells more than once unless the input row and column addresses are changed so that the defective cells for the row and column addresses are not counted in duplicate. A semiconductor memory test circuit, characterized in that.