KR100365942B1 - Data output buffer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer, in particular buffering means for buffering the processed data inside a memory element so that the data has a voltage level sufficient to drive an external peripheral circuit, and an input for controlling the start of a read operation. A control means for controlling whether the substrate bias voltage of the pull-down transistor in the buffering means is variable by comparing the input data signal with the reference potential signal according to the enable signal, and receiving the output signal of the control means according to the signal value Data having stabilized circuit operation by reducing ringing of the output signal by providing substrate bias voltage supply means for selectively applying the first and second negative voltages having a constant potential to supply the substrate bias voltage of the pull-down transistor. It is about output buffer.

Description

Data output buffer

The present invention relates to a data output buffer, and more particularly, to a data output buffer which stabilizes circuit operation by reducing ringing of an output signal.

In general, a data output buffer is a device that buffers or amplifies data processed internally in a semiconductor integrated circuit so that the data has a voltage level sufficient to drive an external peripheral circuit.

Thus, a pull-up driver stage for amplifying the first logic of the data to have the power supply voltage Vcc and a pull-down amplifying the second logic of the data to have the ground voltage Vss. A driver stage may be provided, and the pull-up driver stage may include NMOS and PMOS transistors, and the pull-down driver stage may comprise NMOS transistors.

However, since the NMOS type pull-up driver stage limits the voltage on the output line to be smaller than the voltage on the input line due to a threshold voltage loss, the first logic value of the data in the input line is limited to the power supply voltage Vcc. A separate circuit for boosting to a larger voltage is required, which not only lowers the operation speed of the data output buffer but also causes a problem of increasing current consumption in the standby mode.

On the other hand, since the PMOS type pull-up driver stage does not require a separate boost circuit, it is possible to prevent the operation speed of the data output buffer and the current consumption in the standby mode.

For this reason, it is common for the pull-up driver stage to use a PMOS transistor.

1 is a circuit diagram illustrating a conventional data output buffer, in which a data signal (/ data) is shifted according to an address change under the control of a clock signal applied from the outside. The complementary potential value of the complementary signal) is one input signal, and the masking signal dqm input through the DQ pin is a second input signal. And an even number of inverters connected in series with the output terminals of the first NAND gates NAND1 and the second NAND gates NAND1 and NAND2 (simply shown as two inverters I2 and I3 in the same drawing), and The inductor L1 is connected between an odd number of inverters (in the figure, simply shown as one inverter I4) connected to an output terminal of the second NAND gate NAND2, and a power supply voltage Vcc and an output terminal out. Connected via the gate end of the inverter An NMOS connected between the PMOS transistor MP1 connected to the output terminal of I3 and the ground terminal Vss and the output terminal via an inductor L2, and a gate terminal thereof connected to the output terminal of the inverter I4. It consists of transistor MN1.

Here, the PMOS transistor MP1 performs a pull-up function, and the NMOS transistor MN1 performs a pull-down function.

In addition, the inductors L1 and L2 are connected to a power supply voltage Vcc applying terminal and a ground terminal Vss, respectively, in order to simulate bouncing noise caused by a ringing phenomenon generated at an output terminal.

According to the above configuration, in the conventional data output buffer, when the masking signal dqm is applied at the 'high' level, the signal inverted to the 'low' level via the inverter I1 is converted into the first and second NAND gates. Since it is input as one input signal of (NAND1, NAND2), the output signal of each of the NAND gates NAND1, NAND2 becomes a 'high' level signal regardless of the potential level of the data signal data.

Thus, the 'high' level NAND gate output signal is delayed for a predetermined time through an even number of inverters I2 and I3 and then transferred to the gate terminal of the PMOS transistor MP1.

At the same time, the 'high' level signal outputted through the lower NAND gate NAND2 is passed to the gate terminal of the NMOS transistor MN1 in an inverted state to a 'low' level through an odd number of inverters I4. Delivered.

Accordingly, since both the PMOS transistor MP1 and the NMOS transistor MN1 are turned off, the output terminal out becomes a high-impedance (Hi-Z) state.

In addition, in a situation where the masking signal dqm is applied at a 'low' level, the output signals of the two NAND gates NAND1 and NAND2 vary depending on the potential value of the data signal data, and consequently, the PMOS transistor. By the selective pull-up and pull-down operations of the MP1 and the NMOS transistor MN1, the inverted signal of the data signal data is output to the output terminal.

By the way, the conventional data output buffer that outputs the three-state signals (H, L, Hi-Z) by the above operation, as can be seen through the simulation result of FIG. When the transition from 'high' to 'low' level, the ringing phenomenon is greatly generated, which causes a problem of increasing bouncing noise as in the solid line waveform shown in (b).

The bouncing noise operates simultaneously on a multi-bit DRAM, but becomes larger when the number of output buffers increases, thereby failing to stabilize circuit operation during high-speed operation, thereby lowering the reliability of the device. .

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to stabilize the circuit operation at high speed by reducing the ringing phenomenon generated at the output stage by varying and supplying the substrate bias voltage of the pull-down transistor. To provide a data output buffer that realizes this.

In order to achieve the above object, the present invention provides a data output buffer having a pull-up and a pull-down transistor,

Control means for generating a control signal for controlling whether the substrate bias voltage of the pull-down transistor is varied by comparing an input data signal with a reference potential signal according to an enable signal for controlling the start of a read operation;

And a substrate bias voltage supply means for selectively applying a first negative voltage and a second negative voltage lower than the first negative voltage in response to the control signal to supply the substrate bias voltage of the pull-down transistor.

1 is a circuit diagram showing a conventional data output buffer

2 is a block diagram of a data output buffer according to the present invention.

3 is a circuit diagram showing the control means shown in FIG.

4 is a configuration diagram showing the substrate bias voltage supply means shown in FIG.

5 is a detailed circuit diagram of the level shifter shown in FIG.

Figure 6 is a comparison of the simulation results showing the operating characteristics of the conventional data output buffer according to the present invention

<Description of the symbols for the main parts of the drawings>

1: differential amplifier 2: inverter

10, 20: level shifter 100: control means

200: substrate bias voltage supply means 300: buffering means

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a data output buffer according to the present invention. In order to buffer data processed inside a memory device so that the data has a voltage level sufficient to drive an external peripheral circuit, a pull-up is shown. And an input data signal Vin and a reference potential signal Vref according to a buffering means 300 having a pull-down transistor and a pipeline out count (pocnt) for controlling the start of operation of the buffering means 300. Control means (100) for comparing whether the pull-down transistor (not shown) varies the substrate bias voltage (Vbb); The output signal ctrl of the control means 100 is input, and first and second negative voltages Vbb1 and Vbb2 are selectively applied to the substrate bias voltage Vbb of the pull-down transistor according to the signal value. It comprises a substrate bias voltage supply means 200 for supplying.

According to the above configuration, the present invention can apply the substrate bias voltage Vbb of the pull-down transistor in the buffering means 300 according to the situation.

That is, when the data output buffer is not used, the first negative voltage Vbb1 is applied to the substrate bias voltage Vbb, and when the data output buffer is used, the first negative voltage Vbb1 is applied by a predetermined potential more than the first negative voltage Vbb1. By varying the voltage to the negative second negative voltage Vbb2, the threshold potential of the pull-down transistor in the buffering means 300 is increased, thereby reducing the pull-down capability. This reduces the ringing in the system.

As a result, bouncing noise at the output stage is reduced and the output is stabilized.

Hereinafter, the configuration and operation of the respective means constituting the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram showing the control means 100 shown in FIG. 2, in which an input voltage Vin and a reference voltage Vref ≒ Vdd / 2 are applied to each gate terminal, and a source terminal thereof is applied to the node N1. NMOS transistors MN1 and MN2 commonly connected to each other, and NMOS transistors connected between the node N1 and ground Vss and having a pipeline output counter control signal pocnt for controlling the start of a read operation to the gate stage. (MN3) and between the nodes (N2, N3) connected with the drain terminals of the NMOS transistors (MN1, MN2) and the supply voltage (Vcc), respectively, and the gate terminal thereof is commonly connected to the node (N3). The PMOS transistors MP1 and MP2, and the power supply voltage Vcc and the nodes N2 and N3, respectively, in parallel with the PMOS transistors MP1 and MP2, and the respective gate ends of the pipeline. PMOS transistors MP3 and MP4 to which the output counter control signal pocnt is applied .

In the case of the same figure, an output signal ctrl is generated through the node N2.

FIG. 4 is a block diagram illustrating the substrate bias voltage supplying means 200 shown in FIG. 2, and inversely adjusting the logic level of the output voltage according to the potential level of the output signal ctrl generated from the control means 100. First and second substrate biases selectively switched according to the first and second level shifters 10 and 20 and the output signals of the first and second level shifters 10 and 20 to have different negative potential values. First and second switching elements for supplying voltages Vbb1 and Vbb2 are provided.

In the case of the same figure, the first and second switching elements are implemented as NMOS transistors MN4 and MN5, respectively.

FIG. 5 is a detailed circuit diagram of the level shifters 10 and 20 shown in FIG. 4, in which a signal ctrl and a complementary signal output from the control means 100 are applied to the respective gate terminals, and the source is controlled. A terminal is connected between the NMOS transistors MN6 and MN7 commonly connected to the substrate bias voltage Vbb applying terminal, the power supply voltage Vcc and the drain terminals N4 and N5 of the NMOS transistors MN6 and MN7, respectively. The gate stage of the differential amplifier 1 of current-mirror structure consisting of PMOS transistors MP5 and MP6 connected in a cross-coupled structure; The potential of the output node N5 of the differential amplifier 1 is applied to each gate terminal, and is connected to the CMOS inverters MP7 and MN8 connected in series between the power supply voltage Vcc and the substrate bias voltage Vbb. And a reversal portion 2 made up.

The above configuration is equally applied to the first and second level shifters 10 and 20, and may be different from Vbb1 and Vbb2 only at the negative (-) potential level applied through the substrate bias voltage Vbb applying stage. It is only.

Hereinafter, the operation of the present invention having the above configuration will be described.

First, when the pipeline output counter control signal pocnt, which controls the start of the read operation, is 'low', a data output buffer is not used. In this case, the pipeline output of the 'low' level to the gate stage is performed. The PMOS transistors MP3 and MP4 to which the counter control signal pocnt is applied are turned on so that the signal ctrl output through the output node N2 becomes a 'high' level signal.

Then, the 'high' level signal ctrl is normally input to the first level shifter 10 having the configuration shown in FIG. 5 and inverted to the 'low' level with the second level shifter 20 having the same configuration. Is entered.

At this time, the first level shifter 10 first turns on the potential of the node N4 while the NMOS transistor MN6 is turned on, thereby turning on the PMOS transistor MP6 and turning on the differential amplifier unit (6). The power supply voltage Vcc is supplied to the output node N5 of 1). As a result, the potential of the node N5 is at a high level, which is applied to the output terminal out through the inverting unit 2 composed of the CMOS inverters MP7 and MN8 in the rear stage. A predetermined negative voltage applied through the output is output.

In the case of the figure, the negative voltage becomes a substrate bias voltage of -2V to -3V which is commonly used.

On the contrary, the second level shifter 20 receiving the signal in which the 'high' level output signal ctrl of the control means 100 is inverted to the 'low' level through the inverter I1 receives the NMOS transistor MN7. Since the potential of the output node N5 of the differential amplifier 1 is turned to a low level by being turned on, a high level signal is output to the output terminal through the rear inverter 2. do.

Thus, when the control signal ctrl output from the control means 100 is a 'high' level signal, the switching element MN4 connected to the first level shifter 10 is turned off and at the same time the second level. The switching element MN5 connected to the shifter 20 is turned on and is connected to the substrate bias voltage Vbb of the pull-down transistor in the buffering means 300 via the turned-on switching element MN5 to the first negative voltage. Vbb1) is supplied.

Next, when the pipeline output counter control signal pocnt for controlling the start of the read operation is a 'high' level signal, that is, when the data output buffer is used, the control means shown in FIG. Operation is started when the NMOS transistor MN3 in the control circuit 100 is turned on, and according to the potential level of the input voltage Vin, which becomes the gate voltage of the pull-down transistor in the buffering means 300, of the final output signal ctrl. The potential level is different.

For example, when the input voltage Vin is lower than the reference potential Vref, the NMOS transistor MN2 is turned on and the potential of the node N3 drops to low, so the PMOS transistor MP1 is turned on. The output signal ctrl is turned on to output a 'high' level signal as in the case where the data output buffer is not used.

Thus, the substrate bias voltage supplying means 200 connected to the rear stage is formed by the 'high' level signal output from the second level shifter 20 as in the case where the pipeline output counter control signal pocnt is 'low'. The NMOS transistor MN5, which is a second switching element, is turned on to supply the first negative voltage Vbb1 to the substrate bias voltage Vbb of the pull-down transistor in the buffering means 300.

However, when the input voltage Vin is higher than the reference potential Vref, the NMOS transistor MN1 to which the input voltage Vin is applied to the gate terminal is turned on so that the output signal ctrl of the control means 100 is turned on. ) Outputs a 'low' level signal.

The output signal ctrl of the control means 100 having the 'low' level is input to the substrate bias voltage supply means 200 shown in FIG. 4, and the first and second levels having the configuration shown in FIG. 5. The shifters 10 and 20 output signals of 'high' and 'low' to respective output terminals.

Thus, the NMOS transistor MN4 connected to the first level shifter 10 for outputting the 'high' level signal is turned on, so that the second negative voltage having a more negative value than the first negative voltage Vbb1 is provided. The voltage Vbb2 is supplied and supplied as the substrate bias voltage of the pull-down transistor in the buffering means 300.

By this operation, a negative value of a constant potential is more negative than a normal substrate bias voltage (here, Vbb1 having a potential value of -2 V to -3 V) only when the data output buffer outputs a 'low' level signal to the output terminal. The second negative voltage Vbb2 is controlled to supply the substrate bias voltage of the pull-down transistor.

Thus, by reducing the pull-down function by increasing the threshold potential of the pull-down transistor, it is possible to reduce the ringing phenomenon at the output terminal.

6 is a comparison of simulation results showing the operation characteristics of the data output buffer according to the prior art and the present invention. The solid line shown in (a) shows the waveform of the signal input to the data output buffer, and (b) and (c) The two dotted lines shown in the figure represent the waveforms of the output signal according to the prior art and the present invention, respectively, and the solid line in (d) shows that the substrate bias voltage is varied from Vbb1 to more negative Vbb2.

Thus, the ringing phenomenon generated when the output signal transitions from 'high' to 'low' level is supplied by varying the substrate bias voltage to a more negative potential value Vbb2 as shown in (d). It can be seen from the signal waveform shown in (c) that it is significantly reduced than in the conventional output signal waveform shown in b).

As described above, according to the data output buffer according to the present invention, by supplying the substrate bias voltage of the pull-down transistor variably to adjust the threshold potential, the pull-down function is reduced to reduce the ringing at the output stage. It has a very good effect.

In addition, the ringing phenomenon can be suppressed to reduce the bounce noise at the output stage, thereby achieving an excellent effect of achieving stable operation during high-speed operation of a memory using multiple data output buffers.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (6)

A data output buffer with pull-up and pull-down transistors, Control means for generating a control signal for controlling whether the substrate bias voltage of the pull-down transistor is varied by comparing an input data signal with a reference potential signal according to an enable signal for controlling the start of a read operation; Substrate bias voltage supply means for selectively applying a first negative voltage and a second negative voltage lower than the first negative voltage in response to the control signal to supply the substrate bias voltage of the pull-down transistor in the data output buffer; Data output buffer comprising a. The method of claim 1, The first negative voltage is a voltage of -2V to -3V, and the second negative voltage is a constant potential lower voltage than the first negative voltage. The method of claim 1, The control means has an input voltage and a reference voltage applied to each gate terminal, and the first and second NMOS transistors having common source terminals thereof are connected between the first and second NMOS transistors, and the common source terminal and ground terminals of the first and second NMOS transistors. A third NMOS transistor to which a control signal for controlling the start of a read operation is applied to a gate end, and is connected between a drain end of the first and second NMOS transistors and a power supply voltage applying end, respectively, the gate end of which is connected to the second NMOS transistor; The first and second PMOS transistors commonly connected to the drain terminals of the first and second PMOS transistors, and the power supply voltage applying stages and the drain terminals of the first and second NMOS transistors, respectively, in parallel with the first and second PMOS transistors, respectively. And a third and a fourth PMOS transistor to which the control signal is applied at a gate end thereof. The method of claim 1, The substrate bias voltage supply means is selectively switched according to the first and second level shifters for controlling the logic level of its own output voltage opposite to each other according to the control signal, and the output signals of the first and second level shifters. And first and second switching elements for supplying the first and second negative voltages. The method of claim 4, wherein The first and second level shifters respectively receive an output signal of the control means and a complementary signal thereof, and a current amplifier having a current-mirror structure for differentially amplifying the two signals, and an output signal of the differential amplifier. And an inverting portion to make a data output buffer. The method of claim 4, wherein And said first and second switching elements comprise NMOS transistors.