KR100336770B1 - Capacitor forming method - Google Patents
Capacitor forming method Download PDFInfo
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- KR100336770B1 KR100336770B1 KR1019990049221A KR19990049221A KR100336770B1 KR 100336770 B1 KR100336770 B1 KR 100336770B1 KR 1019990049221 A KR1019990049221 A KR 1019990049221A KR 19990049221 A KR19990049221 A KR 19990049221A KR 100336770 B1 KR100336770 B1 KR 100336770B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
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Abstract
본 발명은 커패시터 형성방법에 관한 것으로, 종래 커패시터 형성방법은 각 커패시터 하부전극을 분리하기 위해서 절연막을 증착한 후 에치백하여 폴리실리콘의 상부가 드러나도록 해야하므로 공정상 난이도가 높고, 이 절연막과 하부전극을 둘러싸는 산화막의 식각비가 다를경우 절연막을 습식각등으로 제거한 후에 산화막을 제거해야 하므로 공정이 많고 복잡한 문제점이 있었다. 따라서 본 발명은 트랜치가 형성된 반도체기판 상에 일정한 거리로 이격되는 제 1~제 4게이트를 형성한 후, 상부전면에 제 1층간절연막을 형성하는 공정과; 상기 제 1~제 4게이트간 이격영역의 제 1층간절연막을 식각하고, 도전성물질을 채워 제 1~제 3플러그를 형성한 다음 상부전면에 제 2층간절연막을 형성하는 공정과; 상기 제 2플러그가 형성된 영역의 제 2층간절연막을 식각하고, 도전성물질을 채워 비트라인컨택을 형성한 다음 웨이퍼 상부전면에 도전막을 형성하고, 이를 패터닝하여 비트라인을 형성하는 공정과; 상기 구조물 상부전면에 제 3층간절연막을 형성하고, 상기 제 1,제 3플러그가 형성된 영역의 제 2,제 3층간절연막을 식각하고, 도전성물질을 채워 노드컨택을 형성하는 공정과; 상기 구조물 상부전면에 차례로 질화막, 산화막을 형성하고, 그 상부에 커패시터가 형성될 영역에 맞추어 패터닝 한 감광막을 형성하는 공정과; 상기 감광막으로 산화막 및 질화막을 식각하여 패터닝하고 상기 드러난 노드컨택을 이용하여 불순물을 포함한 에피층을 성장시키는 공정과; 상기 구조물 상부전면에 폴리실리콘을 증착하는 공정과; 상기 폴리실리콘을 이방성식각하여 상기 산화막의 상부가 드러나도록하는 공정과; 상기 공정으로 드러난 산화막을 제거하는 공정으로 이루어지는 커패시터 형성방법을 통해 각 커패시터 하부전극을 분리하기위해 절연막을 이용하지 않고, 커패시터 하부전극 역할을 하는 폴리실리콘 하부에 불순물이 포함된 에피층을 형성함으로써 단순한 이방성식각에 의해 각 커패시터 하부전극을 분리 할 수 있도록 하여 공정이 용이해 지는 효과가 있다.The present invention relates to a method of forming a capacitor, and the conventional method of forming a capacitor requires high deposition of an insulating film to etch back an insulating film in order to separate the lower electrodes of the capacitor. When the etching ratio of the oxide film surrounding the electrode is different, the oxide film must be removed after the insulating film is removed by wet etching. Therefore, the present invention provides a method of forming a first interlayer insulating film on an upper surface of a semiconductor device, the method comprising: forming first to fourth gates spaced at a predetermined distance on a semiconductor substrate on which a trench is formed; Etching the first interlayer insulating film in the spaced area between the first and fourth gates, filling the conductive material to form the first to third plugs, and then forming a second interlayer insulating film on an upper surface of the first interlayer insulating film; Etching the second interlayer insulating film in the region where the second plug is formed, forming a bit line contact by filling a conductive material, forming a conductive film on the entire upper surface of the wafer, and patterning the bit line to form a bit line; Forming a third interlayer insulating film on the upper surface of the structure, etching the second and third interlayer insulating films in the region where the first and third plugs are formed, and filling the conductive material to form a node contact; Forming a nitride film and an oxide film on the upper surface of the structure in turn, and forming a photosensitive film patterned according to a region where a capacitor is to be formed thereon; Etching and patterning an oxide film and a nitride film with the photosensitive film, and growing an epitaxial layer containing impurities using the exposed node contacts; Depositing polysilicon on the upper surface of the structure; Anisotropically etching the polysilicon to expose an upper portion of the oxide film; Through the capacitor forming method of removing the oxide film revealed by the above process, an epitaxial layer containing impurities is formed on the bottom of polysilicon that serves as the capacitor lower electrode, without using an insulating layer to separate each capacitor lower electrode. By anisotropic etching, the lower electrode of each capacitor can be separated, thereby facilitating the process.
Description
본 발명은 커패시터 형성방법에 관한 것으로, 특히 각 커패시터 하부전극을 분리하는 공정에서 절연막을 이용하지 않으면서도 각 하부전극을 용이하게 분리하기에 적당하도록 한 커패시터 형성방법에 관한 것이다.The present invention relates to a method of forming a capacitor, and more particularly, to a method of forming a capacitor suitable for easily separating each bottom electrode without using an insulating film in a process of separating each capacitor bottom electrode.
종래 커패시터 형성방법을 도 1a 내지 도 1c의 수순단면도를 참고로 하여 설명하면 다음과 같다.The conventional capacitor forming method will be described with reference to the procedure cross-sectional view of FIGS. 1A to 1C as follows.
먼저, 도 1a에 도시한 바와 같이 반도체기판(1)상에 트랜치(2)를 형성하여 액티브영역을 정의하고, 반도체기판(1) 및 트랜치(2)의 상부에 일정한 거리로 이격되는 게이트(3A~3D)를 형성한다.First, as shown in FIG. 1A, a trench 2 is formed on the semiconductor substrate 1 to define an active region, and the gate 3A is spaced at a predetermined distance from the upper portion of the semiconductor substrate 1 and the trench 2. ˜3D).
그리고, 상기 게이트(3A~3D)가 형성된 구조물 상에 층간절연막(4)을 형성하고, 액티브영역과 트랜치(2)상의 게이트(3A~3D)간 이격영역을 식각하여 컨택홀을 형성한 후, 도전성물질을 채워 플러그(5A~5C)를 형성한다.After forming the interlayer insulating film 4 on the structure where the gates 3A to 3D are formed, and forming a contact hole by etching a spaced area between the active region and the gates 3A to 3D on the trench 2, The conductive material is filled to form plugs 5A to 5C.
그리고, 상기 플러그(5A~5C)가 형성된 구조물 상에 층간절연막(6)을 형성하고, 상기 형성된 플러그(5B)의 일부가 드러나도록 컨택홀을 형성한 후 그 상부에 도전성물질을 증착하고 이를 평탄화하여 비트라인컨택(7)을 형성한다.In addition, an interlayer insulating film 6 is formed on the structure where the plugs 5A to 5C are formed, and a contact hole is formed to expose a part of the formed plug 5B, and then a conductive material is deposited on the planarized portion and planarized. The bit line contact 7 is formed.
그리고, 상기 구조물 상부에 도전막을 증착하고 패터닝하여 비트라인(8)을 형성 한 후 그 상부전면에 층간절연막(9)을 형성한다.The bit line 8 is formed by depositing and patterning a conductive layer on the structure, and then forming an interlayer insulating layer 9 on the upper surface thereof.
그리고, 상기 층간절연막(9)을 상기 플러그(5A,5C)가 형성된 영역이 드러나도록 식각하여 컨택홀을 형성한 다음 도전성물질로 컨택홀을 채워 노드컨택(10)을 형성한다.The interlayer insulating layer 9 is etched to expose the regions where the plugs 5A and 5C are formed to form contact holes, and then the node contacts 10 are formed by filling the contact holes with a conductive material.
그리고, 상기 구조물 상부전면에 차례로 질화막(11), 산화막(12)을 증착하고, 그 산화막(12) 상부에 감광막(PR1)을 도포한 후 커패시터 하부전극이 형성될 영역에 맞도록 이를 패터닝한다.The nitride film 11 and the oxide film 12 are sequentially deposited on the upper surface of the structure, and the photoresist film PR1 is coated on the oxide film 12, and then patterned to match the region where the capacitor lower electrode is to be formed.
이때, 상기 질화막(11)은 후속공정에서 이용하는 습식식각에 대한 배리어막의 역할을 한다.In this case, the nitride film 11 serves as a barrier film for wet etching used in a subsequent process.
그 다음, 도 1b에 도시한 바와 같이 상기 형성한 감광막(PR1) 패턴을 이용하여 산화막(12) 및 질화막(11)을 건식각하여 커패시터 하부전극을 위한 패턴을 형성한 다음 그 상부전면에 폴리실리콘(13)을 형성하고, 그 상부에 절연막(14)을 증착한 후 이를 에치백하여 상기 폴리실리콘(13)의 상부 일부가 드러나도록 한다.Next, as shown in FIG. 1B, the oxide film 12 and the nitride film 11 are dry-etched using the formed photoresist film PR1 pattern to form a pattern for the capacitor lower electrode, and then polysilicon is formed on the upper surface thereof. (13) is formed, and an insulating film 14 is deposited on the upper portion thereof, and then etched back so that a part of the upper portion of the polysilicon 13 is exposed.
그 다음, 도 1c에 도시한 바와 같이 상기 형성한 폴리실리콘(13)을 상기 절연막(12)이 드러날 때 까지 에치백하고, 상기과정을 통해 드러난 산화막(12)을 식각하여 제거한다.Next, as illustrated in FIG. 1C, the formed polysilicon 13 is etched back until the insulating layer 12 is exposed, and the oxide layer 12 exposed through the above process is etched and removed.
그러나, 상기한 바와같은 종래 커패시터 형성방법은 각 커패시터 하부전극을 분리하기 위해서 절연막을 증착한 후 에치백하여 폴리실리콘의 상부가 드러나도록 해야하므로 공정상 난이도가 높고, 이 절연막과 하부전극을 둘러싸는 산화막의 식각비가 다를경우 절연막을 습식각등으로 제거한 후에 산화막을 제거해야 하므로 공정이 많고 복잡한 문제점이 있었다.However, in the conventional capacitor formation method as described above, since the insulating film is deposited and then etched back so that the upper portion of the polysilicon is exposed, the process difficulty is high and surrounds the insulating film and the lower electrode. If the etching ratio of the oxide film is different, the oxide film must be removed after the insulating film is removed by wet etching, etc., there are many processes and complicated problems.
본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 절연막을 사용하지 않고서도 각 커패시터 하부전극을 분리할 수 있도록 하여 공정을 용이하게 할 수 있는 커패시터 형성방법을 제공하는데 있다.The present invention has been made to solve the conventional problems as described above, the object of the present invention is to provide a capacitor formation method that can facilitate the process by separating each capacitor lower electrode without using an insulating film To provide.
도 1은 종래 커패시터 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional capacitor forming method.
도 2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***
21 : 반도체기판 22 : 트랜치21: semiconductor substrate 22: trench
23A~23D : 게이트 24,26,29 : 층간절연막23A ~ 23D: Gate 24, 26, 29: Interlayer insulating film
25A~25C : 플러그 27 : 비트라인컨택25A ~ 25C: Plug 27: Bitline Contact
28 : 비트라인 30 : 노드컨택28: bit line 30: node contact
31 : 질화막 32 : 산화막31 nitride film 32 oxide film
33 : 에피층 34 : 폴리실리콘33: epi layer 34: polysilicon
PR2 : 감광막PR2: photosensitive film
상기한 바와같은 본 발명의 목적을 달성하기 위한 커패시터 형성방법은 트랜치가 형성된 반도체기판 상에 일정한 거리로 이격되는 제 1~제 4게이트를 형성한 후, 상부전면에 제 1층간절연막을 형성하는 공정과; 상기 제 1~제 4게이트간 이격영역의 제 1층간절연막을 식각하고, 도전성물질을 채워 제 1~제 3플러그를 형성한 다음 상부전면에 제 2층간절연막을 형성하는 공정과; 상기 제 2플러그가 형성된 영역의 제 2층간절연막을 식각하고, 도전성물질을 채워 비트라인컨택을 형성한 다음 웨이퍼 상부전면에 도전막을 형성하고, 이를 패터닝하여 비트라인을 형성하는 공정과; 상기 구조물 상부전면에 제 3층간절연막을 형성하고, 상기 제 1,제 3플러그가 형성된 영역의 제 2,제 3층간절연막을 식각하고, 도전성물질을 채워 노드컨택을 형성하는 공정과; 상기 구조물 상부전면에 차례로 질화막, 산화막을 형성하고, 그 상부에 커패시터가 형성될 영역에 맞추어 패터닝 한 감광막을 형성하는 공정과; 상기 감광막으로 산화막 및 질화막을 식각하여 패터닝하고 상기 드러난 노드컨택을 이용하여 불순물을 포함한 에피층을 성장시키는 공정과; 상기 구조물 상부전면에 폴리실리콘을 증착하는 공정과; 상기 폴리실리콘을 이방성식각하여 상기 산화막의 상부가 드러나도록 하는 공정과; 상기 공정으로 드러난 산화막을 제거하는 공정으로 이루어지는 것을 특징으로한다.A capacitor forming method for achieving the object of the present invention as described above is a step of forming a first interlayer insulating film on the upper surface after forming the first to fourth gates spaced at a predetermined distance on the semiconductor substrate formed with a trench and; Etching the first interlayer insulating film in the spaced area between the first and fourth gates, filling the conductive material to form the first to third plugs, and then forming a second interlayer insulating film on an upper surface of the first interlayer insulating film; Etching the second interlayer insulating film in the region where the second plug is formed, forming a bit line contact by filling a conductive material, forming a conductive film on the entire upper surface of the wafer, and patterning the bit line to form a bit line; Forming a third interlayer insulating film on the upper surface of the structure, etching the second and third interlayer insulating films in the region where the first and third plugs are formed, and filling the conductive material to form a node contact; Forming a nitride film and an oxide film on the upper surface of the structure in turn, and forming a photosensitive film patterned according to a region where a capacitor is to be formed thereon; Etching and patterning an oxide film and a nitride film with the photosensitive film, and growing an epitaxial layer containing impurities using the exposed node contacts; Depositing polysilicon on the upper surface of the structure; Anisotropically etching the polysilicon to expose an upper portion of the oxide film; It is characterized by consisting of a step of removing the oxide film revealed by the above process.
상기한 바와같은 본 발명에 의한 커패시터 형성방법을 첨부한 도 2a 내지 도 2e의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of the procedure shown in Figure 2a to 2e with the method of forming a capacitor according to the present invention as an embodiment in detail as follows.
먼저, 도 2a에 도시한 바와 같이 반도체기판(21)상에 트랜치(22)를 형성하여 액티브영역을 정의하고, 반도체기판(21) 및 트랜치(22)의 상부에 일정한 거리로 이격되는 게이트(23A~23D)를 형성한다.First, as shown in FIG. 2A, a trench 22 is formed on the semiconductor substrate 21 to define an active region, and the gate 23A is spaced apart from the semiconductor substrate 21 and the trench 22 by a predetermined distance. ˜23D).
그리고, 상기 게이트(23A~23D)가 형성된 구조물 상에 층간절연막(24)을 형성하고, 액티브영역과 트랜치(22)상의 게이트(23A~23D)간 이격영역을 식각하여 컨택홀을 형성한 후, 도전성물질을 채워 플러그(25A~25C)를 형성한다.After the interlayer insulating film 24 is formed on the structure on which the gates 23A to 23D are formed, a contact hole is formed by etching the spaced area between the active region and the gates 23A to 23D on the trench 22. The conductive material is filled to form plugs 25A to 25C.
그리고, 상기 플러그(25A~25C)가 형성된 구조물 상에 층간절연막(26)을 형성하고, 상기 형성된 플러그(25B)의 일부가 드러나도록 컨택홀을 형성한 후 그 상부에 도전성물질을 증착하고 이를 평탄화하여 비트라인컨택(27)을 형성한다.In addition, an interlayer insulating layer 26 is formed on the structure in which the plugs 25A to 25C are formed, a contact hole is formed to expose a part of the formed plug 25B, and then a conductive material is deposited on the planarized layer, and the planarization layer is formed thereon. The bit line contact 27 is formed.
그리고, 상기 구조물 상부에 도전막을 형성하고 이를 패터닝하여 비트라인(28)을 형성한 후 상기 비트라인(28)이 형성된 구조물 상에 층간절연막(29)을 형성하고, 상기 플러그(25A,25C)가 형성된 영역을 식각하여 컨택홀을 형성한 다음 도전성물질을 채우고 이를 평탄화 하여 노드컨택(30)을 형성한다.Then, a conductive film is formed on the structure and patterned to form a bit line 28, and then an interlayer insulating film 29 is formed on the structure on which the bit line 28 is formed, and the plugs 25A and 25C are formed. The formed region is etched to form a contact hole and then filled with a conductive material and planarized to form the node contact 30.
이때, 노드컨택(30)에 채워지는 도전성물질은 폴리실리콘을 사용한다.At this time, the conductive material filled in the node contact 30 uses polysilicon.
그리고, 상기 구조물의 상부에 차례로 질화막(31), 산화막(32)을 형성하고, 그 상부에 감광막(PR2)을 도포한 후 커패시터 하부전극이 형성될 영역에 맞도록 패터닝한다.In addition, the nitride film 31 and the oxide film 32 are sequentially formed on the structure, and the photoresist film PR2 is applied on the upper portion of the structure, and then patterned to match the region where the capacitor lower electrode is to be formed.
이때, 상기 질화막(31)은 후속공정에서 이용하는 습식식각에 대한 배리어막의 역할을 한다.In this case, the nitride film 31 serves as a barrier film for wet etching used in a subsequent process.
그 다음, 도 2b에 도시한 바와 같이 상기 형성한 감광막(PR2)을 이용하여 산화막(32) 및 질화막(31)을 건식각하여 커패시터 하부전극을 위한 패턴을 형성한다.Next, as illustrated in FIG. 2B, the oxide film 32 and the nitride film 31 are dry-etched using the formed photoresist film PR2 to form a pattern for the capacitor lower electrode.
그리고, 상기 과정에 의해 드러난 노드컨택(30)은 폴리실리콘으로 이루어져 있으므로 이를 선택적 에피성장방법으로 상기 형성한 패턴의 하부를 채울정도로 불순물을 포함한 에피층(33)을 성장시킨다.In addition, since the node contact 30 exposed by the above process is made of polysilicon, the epitaxial layer 33 including impurities is grown to fill the lower portion of the formed pattern by a selective epitaxial growth method.
이때, 에피층(33)의 가장 낮은 두께는 하부전극을 이루는 폴리실리콘(34)의 증착두께보다 두꺼워야한다.At this time, the lowest thickness of the epi layer 33 should be thicker than the deposition thickness of the polysilicon 34 forming the lower electrode.
그 다음, 도 2c에 도시한 바와 같이 상기 구조물 상부전면에 커패시터 하부전극으로 쓰일 폴리실리콘(34)을 증착한다.Next, as shown in FIG. 2C, polysilicon 34 to be used as a capacitor lower electrode is deposited on the upper surface of the structure.
그 다음, 도 2d에 도시한 바와 같이 상기 폴리실리콘(34)을 이방성식각 방식으로 상기 산화막(32)의 상부가 드러나도록 식각하면 산화막(32)패턴의 상부에 형성된 폴리실리콘(34)이 식각되는동안 에피층(33)의 상부에 형성된 폴리실리콘(34)이 식각되어, 불순물이 포함되어 도전성물질이 된 에피층(33)이 커패시터 하부전극의 바닥이 된다.Next, as illustrated in FIG. 2D, when the polysilicon 34 is etched to expose the upper portion of the oxide layer 32 in an anisotropic etching manner, the polysilicon 34 formed on the oxide layer 32 pattern is etched. The polysilicon 34 formed on the epitaxial layer 33 is etched, and the epitaxial layer 33, which contains impurities and becomes a conductive material, becomes the bottom of the capacitor lower electrode.
그 다음, 도 2e에 도시한 바와 같이 상기 공정을 통해 드러난 산화막(32)을 습식식각으로 제거한다.Next, as shown in FIG. 2E, the oxide film 32 exposed through the process is removed by wet etching.
상기한 바와 같이 본 발명 커패시터 형성방법은 각 커패시터 하부전극을 분리하기위해 절연막을 이용하지 않고, 커패시터 하부전극 역할을 하는 폴리실리콘 하부에 불순물이 포함된 에피층을 형성함으로써 단순한 이방성식각에 의해 각 커패시터 하부전극을 분리 할 수 있도록 하여 공정이 용이해 지는 효과가 있다.As described above, the capacitor forming method of the present invention does not use an insulating film to separate each capacitor lower electrode, and forms an epitaxial layer containing impurities under the polysilicon that serves as the capacitor lower electrode, thereby forming each capacitor by simple anisotropic etching. The lower electrode can be separated, thereby facilitating the process.
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