KR100327435B1 - Method for Fabricating of semiconductor Device - Google Patents
Method for Fabricating of semiconductor Device Download PDFInfo
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- KR100327435B1 KR100327435B1 KR1020000029029A KR20000029029A KR100327435B1 KR 100327435 B1 KR100327435 B1 KR 100327435B1 KR 1020000029029 A KR1020000029029 A KR 1020000029029A KR 20000029029 A KR20000029029 A KR 20000029029A KR 100327435 B1 KR100327435 B1 KR 100327435B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로서 기판상에 일정한 간격을 갖는 복수개의 게이트 전극 및 게이트 캡 절연막을 적층하여 형성하는 단계와, 상기 게이트 전극 및 게이트 캡 절연막의 양측면에 절연막 측벽을 형성하는 단계와, 상기 게이트 전극 양측의 기판 표면내에 소오소/드레인 불순물 영역을 형성하는 단계와, 상기 게이트 전극 사이의 노출된 기판상에 도전성 콘택을 형성하는 단계와, 상기 도전성 콘택의 표면에 고융점 살리사이드막을 형성하는 단계와, 상기 고융점 살리사이드막을 포함한 전면에 층간 절연막을 형성하는 단계와, 상기 고융점 살리사이드막의 표면이 노출되도록 상기 층간 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계와, 상기 콘택홀 내부에 도전성 플러그를 형성하는 단계를 포함하여 형성한다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a plurality of gate electrodes and a gate cap insulating film having a predetermined interval on a substrate, and forming insulating film sidewalls on both sides of the gate electrode and the gate cap insulating film. Forming a source / drain impurity region in the substrate surface on both sides of the gate electrode, forming a conductive contact on the exposed substrate between the gate electrode, and forming a high melting salicide on the surface of the conductive contact. Forming a film, forming an interlayer insulating film on the entire surface including the high melting salicide film, selectively removing the interlayer insulating film to expose a surface of the high melting salicide film, and forming a contact hole; And forming a conductive plug in the contact hole.
Description
본 발명은 반도체 소자에 관한 것으로 특히, 콘택과 플러그의 계면에 살리사이드(Salicide)를 형성하여 소자의 성능을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of improving the performance of a device by forming a salicide at an interface between a contact and a plug.
이하, 첨부된 도면을 참조하여 종래 기술의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래 기술의 반도체 소자의 제조 공정 단면도이다.1A to 1D are cross-sectional views of a manufacturing process of a semiconductor device of the prior art.
도 1a에 도시된 바와 같이, STI(Shallow Trench Isolation) 공정을 이용하여 기판(11)에 필드 산화막(11a)을 형성하여 활성 영역을 정의한다.As shown in FIG. 1A, a field oxide layer 11a is formed on a substrate 11 using a shallow trench isolation (STI) process to define an active region.
그리고, 상기 정의된 활성 영역의 기판(11)상에 게이트 산화막(도면에는 도시하지 않았음)을 형성하고, 상기 게이트 산화막상에 폴리 실리콘막(12a)과 텅스텐 나이트라이드막(12b)과 텅스텐막(12c)과 티타늄 나이트라이드막(12d)을 차례로 적층하여 형성한다. 이어, 포토 및 식각 공정으로 상기 티타늄 나이트라이드막(12d)과 텅스텐막(12c)과 텅스텐 나이트라이드막(12b)과 폴리 실리콘막(12a)을 선택적으로 제거하여 상기 기판(11)상에 복수개의 스택 게이트(12)를 형성한다.A gate oxide film (not shown) is formed on the substrate 11 in the active region defined above, and the polysilicon film 12a, the tungsten nitride film 12b, and the tungsten film are formed on the gate oxide film. (12c) and the titanium nitride film (12d) are formed by laminating them in sequence. Subsequently, the titanium nitride film 12d, the tungsten film 12c, the tungsten nitride film 12b, and the polysilicon film 12a are selectively removed by a photo and etching process. The stack gate 12 is formed.
그리고, 상기 게이트(12)의 양측 상기 기판(11)내에 불순물 이온을 주입하여 소오스/드레인 영역(도면에는 도시하지 않았음)을 형성한다.Impurity ions are implanted into the substrate 11 on both sides of the gate 12 to form a source / drain region (not shown).
그리고, 도 1b에 도시된 바와 같이, 상기 게이트(12)를 포함한 상기 기판(11)의 전면에 절연막을 증착하고 상기 게이트(12)의 양측면에 남도록 상기 절연막을 에치백(Each-Back)하여 절연측벽(13)을 형성한다.As illustrated in FIG. 1B, an insulating film is deposited on the entire surface of the substrate 11 including the gate 12, and the insulating film is etched back to remain on both sides of the gate 12. The side wall 13 is formed.
이후, 선택적인 에피택셜 성장(Selective Epitaxial Growth)으로 도 1c에 도시된 바와 같이 상기 절연측벽(13) 사이의 공간이 매립되도록 실리콘을 성장시키어 상기 기판(11)상에 복수개의 콘택(14)을 형성한다.Afterwards, a plurality of contacts 14 are formed on the substrate 11 by growing silicon such that the space between the insulating side walls 13 is filled with selective epitaxial growth. Form.
그리고, 도 1d에 도시된 바와 같이, 상기 게이트(12) 및 상기 콘택(14)의표면상에 층간 절연막(15)을 형성하고 포토 및 식각 공정으로 상기 콘택(14)들 중 일부개의 표면이 노출되도록 상기 층간 절연막(15)을 선택적으로 제거한다.As shown in FIG. 1D, an interlayer insulating film 15 is formed on surfaces of the gate 12 and the contact 14, and the surfaces of some of the contacts 14 are exposed by photo and etching processes. The interlayer insulating film 15 is selectively removed.
그리고, 상기 층간 절연막(15) 및 상기 노출된 콘택(14)의 표면을 따라서 베리어 금속막(16)과 비트라인용 금속막을 차례로 증착한 후 포토 및 식각 공정으로 상기 비트라인용 금속막을 패터닝하여 비트라인(17)을 형성한다.The barrier metal layer 16 and the bit line metal layer are sequentially deposited along the surfaces of the interlayer insulating layer 15 and the exposed contact 14, and then the bit line metal layer is patterned by photo and etching processes. Line 17 is formed.
그리고, 상기 비트라인(17)상에 비트라인 캡 산화막(18)을 증착하고 포토 및 식각 공정으로 상기 콘택(14)의 표면이 노출되도록 상기 비트라인 캡 산화막(18)과 비트라인(17)과 베리어 금속막(16)을 선택적으로 제거하여 콘택홀을 형성한다.The bit line cap oxide layer 18 and the bit line 17 may be deposited on the bit line 17 to expose the surface of the contact 14 by photo and etching. The barrier metal film 16 is selectively removed to form a contact hole.
그리고, 상기 콘택홀이 매립되도록 상기 콘택홀을 포함한 상기 비트라인 캡 산화막(18)상에 폴리 실리콘을 증착한 후 포토 및 식각 공정으로 상기 비트라인 캡 산화막(18)상의 폴리 실리콘을 제거하여 상기 콘택(14)과 전기적으로 연결되는 폴리 플러그(19)를 형성하므로써 종래 기술의 반도체 소자의 제조방법을 완성한다.Then, the silicon is deposited on the bit line cap oxide layer 18 including the contact hole so that the contact hole is filled, and then the poly silicon on the bit line cap oxide layer 18 is removed by photo and etching. By forming the poly plug 19 which is electrically connected with the 14, the manufacturing method of the semiconductor element of the prior art is completed.
그러나, 상기와 같은 종래의 반도체 소자의 제조방법은 메모리 소자의 집적도가 증가됨에 따라서 콘택과 폴리 플러그의 계면에서의 저항이 증가됨으로 인하여 RC 지연시간이 증가되어 소자의 성능을 저하시키는 문제점이 있다.However, the conventional method of manufacturing a semiconductor device as described above has a problem in that the RC delay time is increased due to the increase in resistance at the interface between the contact and the poly plug as the degree of integration of the memory device is increased, thereby degrading the performance of the device.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 콘택과 폴리 플러그의 계면에 살리사이드를 형성하므로써 계면저항을 줄일 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the interface resistance by forming a salicide at the interface between the contact and the poly plug to solve the above problems.
도 1a 내지 도 1d는 종래의 반도체 소자의 제조공정 단면도1A to 1D are cross-sectional views of a manufacturing process of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 제조공정 단면도2A through 2E are cross-sectional views illustrating a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요 부분에 대한 부호설명Explanation of Signs of Major Parts of Drawings
21 : 기판 21a : 필드 산화막21 substrate 21a field oxide film
22 : 게이트 23 : 절연측벽22: gate 23: insulated side wall
24 : 콘택 24a : 티타늄 살리사이드막24 contact 24a titanium salicide film
25 : 층간 절연막 26 : 베리어 금속막25 interlayer insulating film 26 barrier metal film
27 : 비트라인 28 : 비트라인 캡 산화막27: bit line 28: bit line cap oxide film
39 : 폴리 플러그39: poly plug
상기와 같은 목적을 달성하기 위한 본발명의 반도체 소자의 제조방법은 기판상에 일정한 간격을 갖는 복수개의 게이트 전극 및 게이트 캡 절연막을 적층하여 형성하는 단계와, 상기 게이트 전극 및 게이트 캡 절연막의 양측면에 절연막 측벽을 형성하는 단계와, 상기 게이트 전극 양측의 기판 표면내에 소오소/드레인 불순물 영역을 형성하는 단계와, 상기 게이트 전극 사이의 노출된 기판상에 도전성 콘택을 형성하는 단계와, 상기 도전성 콘택의 표면에 고융점 살리사이드막을 형성하는 단계와, 상기 고융점 살리사이드막을 포함한 전면에 층간 절연막을 형성하는 단계와, 상기 고융점 살리사이드막의 표면이 노출되도록 상기 층간 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계와, 상기 콘택홀 내부에 도전성 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 한다A method of manufacturing a semiconductor device of the present invention for achieving the above object is formed by stacking a plurality of gate electrodes and a gate cap insulating film having a predetermined interval on a substrate, and on both sides of the gate electrode and the gate cap insulating film Forming an insulating film sidewall, forming a source / drain impurity region in the substrate surface on both sides of the gate electrode, forming a conductive contact on the exposed substrate between the gate electrode, Forming a high melting salicide film on a surface, forming an interlayer insulating film on the entire surface including the high melting salicide film, and selectively removing the interlayer insulating film so that the surface of the high melting salicide film is exposed. Forming a conductive plug in the contact hole; Characterized in that the open forming
이하, 첨부된 도면을 참조하여 본 발명에 의한 반도체 소자의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본발명의 실시예에 따른 반도체 소자의 제조공정 단면도이다.2A through 2E are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 2a에 도시된 바와 같이, STI(Shallow Trench Isolation) 공정을 이용하여 기판(21)에 필드 산화막(21a)을 형성하여 활성 영역을 정의한다.As shown in FIG. 2A, a field oxide layer 21a is formed on the substrate 21 using a shallow trench isolation (STI) process to define an active region.
그리고, 상기 정의된 활성 영역의 기판(11)상에 게이트 산화막(도면에는 도시하지 않았음)을 형성하고, 상기 게이트 산화막상에 폴리 실리콘막(22a)과, 텅스텐 나이트라이드막(22b)과 텅스텐막(22c)과, 티타늄 나이트라이드막(22d)을 차례로 적층하여 형성한다. 이어, 포토 및 식각 공정으로 상기 티타늄나이트라이드막(22d)과 텅스텐막(22c)과 텅스텐 나이트라이드막(22b)과 폴리 실리콘막(22a)을 선택적으로 제거하여 상기 기판(21)상에 복수개의 스택 게이트(22)를 형성한다.A gate oxide film (not shown) is formed on the substrate 11 in the active region defined above, and a polysilicon film 22a, a tungsten nitride film 22b, and tungsten are formed on the gate oxide film. The film 22c and the titanium nitride film 22d are laminated in this order. Subsequently, the titanium nitride film 22d, the tungsten film 22c, the tungsten nitride film 22b, and the polysilicon film 22a are selectively removed by a photo and etching process. The stack gate 22 is formed.
그리고, 상기 게이트(22)의 양측 상기 기판(21)내에 불순물 이온을 주입하여 소오스/드레인 영역(도면에는 도시하지 않았음)을 형성한다.Impurity ions are implanted into the substrate 21 on both sides of the gate 22 to form a source / drain region (not shown).
그리고, 도 2b에 도시된 바와 같이, 상기 게이트(22)를 포함한 상기 기판(21)의 전면에 절연막을 증착하고 상기 게이트(22)의 양측면에 남도록 상기 절연막을 에치백(Each-Back)하여 절연측벽(23)을 형성한다.As shown in FIG. 2B, an insulating film is deposited on the entire surface of the substrate 21 including the gate 22, and the insulating film is etched back so as to remain on both sides of the gate 22. The side wall 23 is formed.
이후, 선택적인 에피택셜 성장(Selective Epitaxial Growth)으로 도 2c에 도시된 바와 같이 상기 절연측벽(23) 사이의 공간이 메워지도록 실리콘을 성장시키어 상기 기판(21)상에 복수개의 콘택(24)을 형성한다.Then, a plurality of contacts 24 are formed on the substrate 21 by growing silicon to fill the space between the insulating side walls 23 as shown in FIG. 2C with Selective Epitaxial Growth. Form.
그리고, 도 2d에 도시된 바와 같이 상기 콘택(24)을 포함한 기판(21)의 전면에 티타늄(Ti)을 증착하고 열처리하여 상기 콘택(24) 표면에 티타늄 살리사이드(Salicide)막(24a)을 형성한다.As shown in FIG. 2D, titanium (Ti) is deposited on the entire surface of the substrate 21 including the contact 24 and heat-treated to form a titanium salicide layer 24a on the surface of the contact 24. Form.
여기에서 상기 티타늄(Ti) 이외에 코발트(Co), 텅스텐(W), 몰리브덴(Mo)등의 고융점 금속 중 어느 하나를 사용하여 형성할 수 있다.In addition to the titanium (Ti) it may be formed using any one of a high melting point metal such as cobalt (Co), tungsten (W), molybdenum (Mo).
또한, 상기 티타늄 살리사이드막(24a)은 상기 콘택(24)의 실리콘과 상기 티타늄(Ti)이 반응하여 형성된 물질이다.In addition, the titanium salicide layer 24a is a material formed by reacting silicon of the contact 24 with the titanium (Ti).
이어, 잔존하는 상기 티타늄(Ti)을 제거한다.Then, the remaining titanium (Ti) is removed.
그리고, 도 2e에 도시된 바와 같이, 상기 게이트(22) 및 상기 티타늄 살리사이드막(24a)상에 층간 절연막(25)을 증착하고 포토 및 식각 공정으로 상기 복수개의 콘택(24)상의 티타늄 살리사이드막(24a) 중 일부개의 표면이 노출되도록 상기 층간 절연막(25)을 선택적으로 제거한다.As shown in FIG. 2E, an interlayer insulating film 25 is deposited on the gate 22 and the titanium salicide layer 24a, and the titanium salicide on the plurality of contacts 24 is formed by photo and etching processes. The interlayer insulating film 25 is selectively removed so that the surface of a portion of the film 24a is exposed.
그리고, 상기 층간 절연막(25) 및 상기 노출된 티타늄 살리사이드막(24a)의 표면을 따라서 베리어 금속막(26)과 비트라인용 금속막을 차례로 증착하고 포토 및 식각 공정으로 상기 비트라인용 금속막을 패터닝하여 비트라인(27)을 형성한다.The barrier metal layer 26 and the bit line metal layer are sequentially deposited along the surfaces of the interlayer insulating layer 25 and the exposed titanium salicide layer 24a, and the bit line metal layer is patterned by photo and etching processes. The bit line 27 is formed.
그리고, 상기 비트라인(27)상에 비트라인 캡 산화막(28)을 증착하고 상기 티타늄 살리사이드막(24a)의 표면이 노출되도록 포토 및 식각 공정으로 상기 비트라인 캡 산화막(28)과 비트라인(27)과 베리어 금속막(26)을 선택적으로 제거하여 콘택홀을 형성한다.The bit line cap oxide layer 28 and the bit line may be deposited by a photo and etching process so as to deposit the bit line cap oxide layer 28 on the bit line 27 and expose the surface of the titanium salicide layer 24a. 27) and the barrier metal film 26 are selectively removed to form contact holes.
그리고, 상기 콘택홀이 매립되도록 상기 콘택홀을 포함한 상기 비트라인 캡 산화막(28)상에 폴리실리콘을 증착한 후, 포토 및 식각 공정으로 상기 비트라인 캡 산화막(28)상의 폴리실리콘을 제거하여 상기 콘택(24)과 전기적으로 연결되는 폴리 플러그(29)를 형성하여 본발명의 실시예에 따른 반도체 소자의 제조방법을 완성한다.After depositing polysilicon on the bit line cap oxide layer 28 including the contact hole to fill the contact hole, polysilicon on the bit line cap oxide layer 28 is removed by photo and etching. A poly plug 29 is formed to be electrically connected to the contact 24 to complete a method of manufacturing a semiconductor device according to an embodiment of the present invention.
상기와 같은 본 발명의 반도체 소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing a semiconductor device of the present invention as described above has the following effects.
첫째, 상기 콘택과 상기 플러그의 계면 저항을 줄이여 지연시간을 감소시킬 수 있으므로 소자의 성능을 향상시킬 수 있다.First, since the delay time can be reduced by reducing the interface resistance between the contact and the plug, the performance of the device can be improved.
둘째, 고집적화됨에 따라 증가되는 저항값을 효과적으로 줄일 수 있으므로소자를 고집적화 시킬 수 있다.Second, since the resistance value increased as it is highly integrated, the device can be highly integrated.
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