KR100324325B1 - Manufacturing method for mostransistor for electro static discharge - Google Patents

Abstract

The present invention relates to a MOS transistor manufacturing method of the electrostatic discharge prevention circuit, in the conventional MOS transistor of the electrostatic discharge prevention circuit, the separation distance between the drain electrode and the gate compared to the separation distance between the source electrode and the gate to prevent the gate oxide insulation breakdown. By forming it long, the breakdown rate of the gate oxide film can be reduced by increasing the resistance of the drain, but since the drain must be formed relatively large, there is a problem in that the degree of integration decreases. In view of the above problems, the present invention sequentially deposits a gate oxide film, a polysilicon layer, and a nitride film on the substrate, forms the gate by patterning the deposited film, and then implants impurity ions into the side substrate of the gate to drain. And a MOS transistor manufacturing step of forming a source; Applying a photoresist on the upper surface of the structure, forming a pattern to expose a portion of the drain adjacent to the side of the gate, and then drain the exposed drain region to a predetermined depth to expand the drain surface area Steps; A current path expansion step of lengthening a current path through the drain by injecting impurities of the same conductivity type as the drain into the etched region of the exposed drain; A sidewall forming step of removing the photoresist, depositing a nitride film on the gate, the drain and the source, and dry etching the nitride film to form a gate sidewall; Depositing an insulating film on top of the structure and forming a contact hole to expose a portion of the source and drain, and then forming a source and drain electrode in the contact hole. Since the current path can be maintained, the gate oxide film is prevented from being destroyed when an abnormal high voltage is applied, and the degree of integration of the device is improved.

Description

Manufacturing method of MOS transistor for prevention of electrostatic discharge {MANUFACTURING METHOD FOR MOSTRANSISTOR FOR ELECTRO STATIC DISCHARGE}

The present invention relates to a method of manufacturing a MOS transistor for preventing electrostatic discharge, and in particular, to increase the resistance component of the drain to prevent the gate oxide film from being destroyed when static electricity is applied, and to reduce the size of the drain so as to be suitable for improving the integration density of the MOS transistor. An electrostatic discharge prevention MOS transistor manufacturing method.

In general, a semiconductor circuit includes a means for flowing an abnormal high voltage applied from the outside to the ground for protection of an integrated circuit which is vulnerable to static electricity, and a switching device such as a MOS transistor or a bipolar transistor is used. The MOS transistor or the bipolar transistor may be destroyed by the abnormally applied high voltage, and in particular, the MOS transistor is susceptible to dielectric breakdown of the gate oxide film, thereby reducing the reliability of the entire circuit. When described in detail with reference to the accompanying drawings as follows.

1 is a cross-sectional view of a conventional electrostatic discharge prevention MOS transistor, as shown therein; A gate (2) positioned at an upper portion of the substrate (1); A drain 3 positioned below the one side substrate 1 of the gate and having an exposed surface long in the gate direction to increase resistance thereof; And a source 4 formed under the other side substrate 1 of the gate 2.

In the above structure, a high voltage is applied to the drain side 3 of the NMOS transistor so that the voltage is applied to the gate oxide film of the gate 2 to prevent the gate oxide film from being destroyed. In order to be able to form the drain electrode 5 in a large position, the length of the drain 3 is formed long.

In the MOS transistor, the gate oxide film, the polycrystalline silicon, and the nitride film are sequentially deposited on the substrate 1 in the same manner as in the manufacturing method of the general MOS transistor, and the gate ions are formed by patterning them by a photolithography process and implanting impurity ions The source 4 and the drain 3 are formed through the sidewalls, sidewalls 6 are formed on the side surfaces of the gate 2, the insulating layer 7 is deposited on the upper surface of the structure, and then contact holes are formed. To expose a portion of the source 4 and drain 3.

At this time, in order to increase the resistance of the drain 3, the drain 3 of the position where the separation distance from the gate 2 is relatively larger than that of the source 4 is exposed, and the drain electrode 5 and The source electrode 8 is formed.

As described above, in the conventional method of manufacturing a MOS transistor for preventing an electrostatic discharge, the gap between the drain electrode and the gate should be formed longer than the distance between the source electrode and the gate to prevent the gate oxide film insulation breakdown of the MOS transistor. Although the breakdown rate of the gate oxide film can be reduced by increasing the amount of components, there is a problem that the degree of integration decreases because the drain must be relatively large.

It is an object of the present invention to provide a method of manufacturing a MOS transistor for preventing static discharge, which can increase the resistance of the drain without forming a large drain.

1 is a cross-sectional view of a conventional electrostatic discharge prevention MOS transistor.

Figure 2a to 2e is a cross-sectional view of the manufacturing process of the MOS transistor for preventing electrostatic discharge of the present invention.

*** Description of the symbols for the main parts of the drawings ***

1: Substrate 2: Gate

3: Drain 4: Source

5: Nitride film (side wall) 6: Insulation film

7: plug

The above object is to sequentially deposit a gate oxide film, a polysilicon, and a nitride film on top of the substrate, pattern the deposited film to form a gate, and ion implant the impurity ions into the side substrate of the gate to form a drain and a source. Forming a MOS transistor; Applying a photoresist on the upper surface of the structure, forming a pattern to expose a portion of the drain adjacent to the side of the gate, and then drain the exposed drain region to a predetermined depth to expand the drain surface area Steps; A current path expansion step of lengthening a current path through the drain by injecting impurities of the same conductivity type as the drain into the etched region of the exposed drain; A sidewall forming step of removing the photoresist, depositing a nitride film on the gate, the drain and the source, and dry etching the nitride film to form a gate sidewall; It is achieved by depositing an insulating film on top of the structure, forming a contact hole to expose a portion of the source and drain, and then forming a source and drain electrode in the contact hole, thereby forming a curved drain. When described in detail with reference to the accompanying drawings, the present invention as follows.

2A to 2E are cross-sectional views of a manufacturing process of the MOS transistor for preventing electrostatic discharge of the present invention. As shown in this figure, a gate oxide film, a polycrystalline silicon, and a nitride film are sequentially deposited on the substrate 1, and a photolithography process is performed. Part of the nitride film, polysilicon, and gate oxide film is etched to form a gate 2, and then ion 3 is implanted with impurity ions into the side substrate 1 of the gate 2 to drain the drain 3 and the source 4, respectively. Forming step (FIG. 2A); The photoresist PR1 is applied to the upper surface of the structure, exposed and developed to expose a partial region of the drain 3 adjacent to the side of the gate 2, and the exposed region is etched to a predetermined depth to drain Expanding the surface area of (3) (FIG. 2B); Injecting impurities of the same conductivity type as the drain (3) at low concentration into the etched region of the exposed drain (3); Removing the photoresist (PR1) and depositing a nitride film (5) on top of the gate (2), drain (3) and source (4); Dry etching the nitride film 5 to form sidewalls 5 located at the upper side of the etching region of the drain 3 and the side surface of the gate 2, depositing an insulating film 6 on the upper surface of the contact, After forming a hole to expose a part of the source 4 and the drain 3, a plug 7 is formed in the contact hole (Fig. 1e).

Hereinafter, the present invention as described above will be described in more detail.

First, as shown in FIG. 2A, a gate oxide film, a polysilicon, and a nitride film are sequentially deposited on the upper surface of the substrate 1, and then a photoresist is applied on the nitride film, followed by exposure and development to form a gate pattern. In addition, the gate 2 is formed by sequentially etching the nitride film, the polysilicon, and the gate oxide film by an etching process using the photoresist having the gate pattern formed as an etching mask.

Next, an ion implantation process of removing the photoresist pattern on the gate 2 and using the nitride film as an ion implantation mask, wherein the drain 3 and the source under the side substrate 1 of the gate 2 are removed. (4) is formed.

Next, as shown in FIG. 2B, photoresist PR1 is applied to the upper surfaces of the gate 2, the source 4, and the drain 3, and is exposed and developed to the side surfaces of the gate 2. A portion of the adjacent drain 3 is exposed to a predetermined area.

Next, a portion of the exposed drain 3 is etched to form a step in the drain 3. This results in expanding the surface area of the drain 3.

Next, as shown in FIG. 2C, impurity ions are implanted into the substrate 1 under the etching region of the drain 3. By the ion implantation, the drain 3 is formed to be bent, so that the drain electrode is formed in a region relatively close to the gate 2 in a plane relatively similar to the conventional drain resistance.

Next, as shown in FIG. 2D, the photoresist PR1 is removed and a nitride film 5 is deposited on the upper surface of the structure.

Next, as shown in FIG. 2E, the nitride film 5 is dry-etched to form sidewalls 5 on the side surfaces of the gate 2. At this time, the side wall 5 is formed so that the upper side of the etching region of the drain 3 is not exposed.

If the etching region of the drain 3 is exposed and the drain electrode is formed on the etching region of the drain 3, the drain 3 is formed to bend to substantially extend the length of the drain 3. Will disappear.

Then, an insulating film 6 is deposited on the upper surface of the structure, a photoresist is applied on the insulating film 6, and a pattern for exposing a part of the insulating film 6 is formed. In the etching process using the formed photoresist as an etching mask, the exposed insulating layer 6 is etched to expose portions of the source 4 and the drain 3.

The photoresist is then removed, and the metal is deposited and planarized to form a plug 7, which is an electrode connected to the exposed source 4 and drain 3.

In the present invention, the shape of the drain 3 is converted to bend so that a distance from the gate becomes relatively short when viewed in plan view, but a path through which a current passes substantially is maintained according to the degree of bending of the drain 3. It is possible to prevent the gate oxide film from dielectric breakdown by applying abnormal high voltage.

As described above, the method of manufacturing the MOS transistor for preventing electrostatic discharge can maintain a long current path in a narrow area by forming a curved drain of the MOS transistor, thereby preventing insulation of the gate oxide film when an abnormal high voltage is applied. There is an effect of improving the degree of integration of the device.

Claims (2)

A MOS transistor is fabricated by sequentially depositing a gate oxide film, polysilicon, and nitride film on the substrate, patterning the deposited film to form a gate, and ion implanting impurity ions into the side substrate of the gate to form a drain and a source. Steps; Applying a photoresist to the upper surface of the structure, forming a pattern to expose a portion of the drain, and then etching the exposed drain region to a predetermined depth to expand the drain surface area; A current path expansion step of lengthening a current path through the drain by injecting impurities of the same conductivity type as that of the drain into the etched region of the exposed drain; A sidewall forming step of removing the photoresist, depositing a nitride film on the gate, the drain and the source, and dry etching the nitride film to form a gate sidewall; And depositing an insulating film on top of the structure, forming a contact hole to expose a portion of the source and drain, and then forming source and drain electrodes in the contact hole. The method of claim 1, wherein the drain electrode is formed to be in contact with an upper portion of an unetched drain on an outer side of an etching region of the drain.