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KR100291181B1 - Method for forming FeRAM - Google Patents

Method for forming FeRAM Download PDF

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KR100291181B1
KR100291181B1 KR1019970075075A KR19970075075A KR100291181B1 KR 100291181 B1 KR100291181 B1 KR 100291181B1 KR 1019970075075 A KR1019970075075 A KR 1019970075075A KR 19970075075 A KR19970075075 A KR 19970075075A KR 100291181 B1 KR100291181 B1 KR 100291181B1
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ferroelectric
film
thin film
capacitor
forming
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KR19990055163A (en
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김남경
유인규
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박종섭
현대전자산업주식회사
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/60Capacitors
    • H10D1/68Capacitors having no potential barriers
    • H10D1/682Capacitors having no potential barriers having dielectrics comprising perovskite structures

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Abstract

PURPOSE: A fabrication method of ferroelectric memory devices is provided to improve a characteristic of a ferroelectric capacitor by keeping a regular residual polarization on a ferroelectric thin film for a comparatively long time. CONSTITUTION: Contact holes are formed by selectively etching the interlayer dielectrics(34,36) formed on a substrate(30). Polysilicon plugs(37) are formed and connected to the substrate(30) through the contact holes. A titanium layer(38), a titanium nitride(39), a platinum layer(40) for forming lower electrodes and a thin film(41) made of PbBi2Ta2O9 are sequentially formed on the entire surface of the resultant structure. Then, the thin film(41), the platinum layer(40), the titanium nitride(39) and the titanium layer(38) are sequentially and partially etched to form a pattern. A protection layer(42) made of SrBi2-xTa2O9-x formed by annealing at the temperature of 500-700 deg.C is formed on the resultant structure to prevent diffusion of hydrogen ions to the thin film(41), thereby keeping a regular residual polarization on the thin film(41) for a comparatively long time. A protection oxide(43) is formed on the protection layer(42). The protection oxide(43) and the protection layer(42) are partially etched to expose the thin film(41). Upper electrodes are formed by the steps of depositing and etching a platinum layer(44).

Description

강유전체 메모리 소자 제조 방법{Method for forming FeRAM}Ferroelectric memory device manufacturing method {Method for forming FeRAM}

본 발명은 반도체 장치 제조 방법에 관한 것으로, 특히 강유전체 메모리 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a ferroelectric memory device.

강유전체는 상온에서 유전상수가 크고, 안정한 잔류분극(remanent polarization) 특성이 있어, 강유전체를 박막화하여 비휘발성(nonviolation) 메모리 소자로의 응용이 실현되고 있다. 강유전체 박막을 비휘발성 메모리 소자로 사용하는 경우 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고, 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호(digital) 1과 0을 저장하게 되는 원리를 이용하는 것이다.Ferroelectrics have a large dielectric constant at room temperature and have stable residual polarization characteristics. Applications of the ferroelectrics have been realized by making the ferroelectrics thin and non-volatile memory devices. When using a ferroelectric thin film as a nonvolatile memory device, the signal is input by adjusting the direction of polarization in the direction of an electric field applied to the ferroelectric thin film, and the digital signals 1 and 0 are determined by the direction of residual polarization remaining when the electric field is removed. Is to use the principle of storage.

이하, 종래 기술에 따른 강유전체 메모리 소자 제조 공정 단면도인 도 1을 참조하여 종래 기술을 설명한다.Hereinafter, a conventional technology will be described with reference to FIG. 1, which is a cross-sectional view of a ferroelectric memory device manufacturing process according to the related art.

도 1에 도시한 바와 같이 반도체 기판(10) 상에 형성된 층간절연막(14, 16)을 선택적으로 식각하여 콘택홀을 형성하고, 콘택홀을 통하여 반도체 기판(10)과 연결되는 폴리실리콘 플러그(17)를 형성한 후, 장벽금속막으로 티타늄막(18) 및 티타늄 나이트라이드막(19)을 형성한 다음, 하부전극을 형성하기 위하여 백금(Pt)막(20)을 형성하고, 백금(Pt)막(20), 티타늄 나이트라이드막(19) 및 티타늄막(18)을 선택적으로 식각하여 하부전극 패턴을 형성한다. 이어서, 하부전극 상에 강유전체 박막(21)을 형성하고 선택적으로 식각하여 패턴을 형성한 후, 보호산화막(22,23)을 형성하고 선택적으로 식각하여 강유전체 박막(21)을 노출시킨다. 다음으로, 백금막(24)을 형성하고 선택적으로 식각하여 노출된 강유전체막(21)과 접하는 상부전극을 형성한다. 이후 층간절연막을 형성하여 평탄화시킨다. 도1에서 미설명 도면부호‘11'은 필드산화막,‘12'는 게이트 산화막, '13'은 게이트 전극, ‘15'는 비트라인을 각각 나타낸다.As shown in FIG. 1, the interlayer insulating layers 14 and 16 formed on the semiconductor substrate 10 are selectively etched to form contact holes, and the polysilicon plugs 17 connected to the semiconductor substrate 10 through the contact holes. ), Then a titanium film 18 and a titanium nitride film 19 are formed of a barrier metal film, and then a platinum (Pt) film 20 is formed to form a lower electrode, and platinum (Pt) The film 20, the titanium nitride film 19, and the titanium film 18 are selectively etched to form a lower electrode pattern. Subsequently, after the ferroelectric thin film 21 is formed on the lower electrode and selectively etched to form a pattern, the protective oxide films 22 and 23 are formed and selectively etched to expose the ferroelectric thin film 21. Next, the platinum film 24 is formed and selectively etched to form an upper electrode in contact with the exposed ferroelectric film 21. An interlayer insulating film is then formed and planarized. In FIG. 1, reference numeral '11' denotes a field oxide film, '12' denotes a gate oxide layer, '13' denotes a gate electrode, and '15' denotes a bit line.

상기와 같이 이루어지는 종래의 강유전체 캐패시터 형성 공정은, 이후에 층간절연막을 형성하여 평탄화시키는 공정에서 발생하는 수소가 강유전 박막의 표면에 흡입되어 H2O를 형성함으로써 강유전체 박막의 조성이 변화되어 화학정량(stoichiometric)을 만족하지 못하게 된다. 따라서, 유전막에 전기적인 펄스(pulse)를 인가하여 캐패시터가 일정한 잔류분극 값을 유지하지 못하는 등의 특성의 저하가 일어나는 문제점이 있다.In the conventional ferroelectric capacitor forming process as described above, hydrogen generated in the process of forming and planarizing the interlayer insulating film is sucked into the surface of the ferroelectric thin film to form H 2 O to change the composition of the ferroelectric thin film so that the chemical The stoichiometric is not satisfied. Therefore, there is a problem in that the deterioration of the characteristics such as the capacitor does not maintain a constant residual polarization value by applying an electrical pulse (pulse) to the dielectric film.

상기와 같은 문제점을 해결하기 위한 본 발명은 층간절연막 형성시 발생하는 수소가 강유전체 박막으로 흡입되는 것을 방지하여 강유전 특성 저하를 방지할 수 있는 강유전체 캐패시터 형성 방법을 제공하는데 그 목적이 있다.An object of the present invention to solve the above problems is to provide a method of forming a ferroelectric capacitor that can prevent the hydrogen generated when forming the interlayer insulating film is sucked into the ferroelectric thin film to prevent degradation of the ferroelectric properties.

도 1은 종래 기술에 따른 강유전체 메모리 소자 제조 공정 단면도,1 is a cross-sectional view of a ferroelectric memory device manufacturing process according to the prior art;

도 2a 내지 도 2c는 본 발명의 일실시예에 따른 강유전체 메모리 소자 제조 공정 단면도.2A to 2C are cross-sectional views of a ferroelectric memory device fabrication process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing

30: 반도체 기판 31: 필드산화막30: semiconductor substrate 31: field oxide film

32: 게이트 산화막 33: 게이트 전극32: gate oxide film 33: gate electrode

34, 36: 층간절연막 37: 폴리실리콘 플러그34, 36: interlayer insulating film 37: polysilicon plug

38: 티타늄막 39: 티타늄 나이트라이드막38: titanium film 39: titanium nitride film

40, 44: 백금막 41: PbBi2Ta2O940, 44: platinum film 41: PbBi 2 Ta 2 O 9 film

42: SrBi2-xTa2O9-x막 43: 보호산화막42: SrBi 2-x Ta 2 O 9-x film 43: protective oxide film

상기 목적을 달성하기 위한 본 발명은, 반도체 기판 상부에 캐패시터 하부전극을 형성하는 단계; 상기 하부전극 상에 PbBi2Ta2O9캐패시터 강유전체막을 형성하는 단계; 캐패시터 상부전극과 접하지 않는 상기 PbBi2Ta2O9캐패시터 강유전체막 표면 및 측면을 덮는 강유전체 보호막을 형성하되, 상기 강유전체 보호막을 500 ℃ 내지 700 ℃ 온도에서 열처리하여 형성하는 단계; 및 상기 PbBi2Ta2O9캐패시터 강유전체막과 접하는 캐패시터 상부전극을 형성하는 단계를 포함하는 강유전체 메모리 소자 제조 방법을 제공한다.The present invention for achieving the above object, the step of forming a capacitor lower electrode on the semiconductor substrate; Forming a PbBi 2 Ta 2 O 9 capacitor ferroelectric film on the lower electrode; Forming a ferroelectric protective film covering the surface and side surfaces of the PbBi 2 Ta 2 O 9 capacitor ferroelectric film which is not in contact with the capacitor upper electrode, wherein the ferroelectric protective film is formed by heat treatment at a temperature of 500 ° C. to 700 ° C .; And forming a capacitor upper electrode in contact with the PbBi 2 Ta 2 O 9 capacitor ferroelectric layer.

본 발명은 강유전체막을 SrBi2-xTa2O9-x(x는, 0 < x < 2)막으로 보호하여 층간절연막 형성 공정시 발생하는 수소가 강유전체막으로 흡입되는 것을 방지하는 방법이다.The present invention is a method of protecting a ferroelectric film with an SrBi 2-x Ta 2 O 9-x (x is 0 <x <2) film to prevent hydrogen generated during the interlayer insulating film forming process from being sucked into the ferroelectric film.

이하, 본 발명의 일실시예에 따른 강유전체 메모리 소자 제조 공정 단면도인 도 2a 내지 도 2c를 참조하여 본 발명의 일실시예를 설명한다.Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 2A to 2C which are cross-sectional views of a ferroelectric memory device manufacturing process according to an embodiment of the present invention.

먼저, 도 2a에 도시한 바와 같이 반도체 기판(30) 상에 형성된 층간절연막(34, 36)을 선택적으로 식각하여 콘택홀을 형성하고, 폴리실리콘막을 형성한 후 화학기계적연마(chemical mechanical polishing)를 실시하여, 콘택홀을 통하여 반도체 기판(30)과 연결되는 폴리실리콘 플러그(37)를 형성한 후, 장벽금속막으로 티타늄막(38) 및 티타늄 나이트라이드막(39)을 형성한다. 이어서, 하부전극을 형성하기 위하여 백금(Pt)막(40)을 형성하고, 반도체 기판(10) 상에 스핀 코팅(spin coating), 유기금속화학기상증착법, 스퍼터링(sputtering) 방법 또는 LSMCD(liquid source mixed chemical deposition) 방법으로 1000 Å 내지 2000 Å 두께의 PbBi2Ta2O9박막(41)을 형성한 후, PbBi2Ta2O9박막(41), 백금(Pt)막(40), 티타늄 나이트라이드막(39) 및 티타늄막(38)을 선택적으로 식각하여 패턴을 형성한다.First, as shown in FIG. 2A, contact holes are formed by selectively etching the interlayer insulating films 34 and 36 formed on the semiconductor substrate 30, a polysilicon film is formed, and then chemical mechanical polishing is performed. After forming the polysilicon plug 37 connected to the semiconductor substrate 30 through the contact hole, the titanium film 38 and the titanium nitride film 39 are formed of the barrier metal film. Next, a platinum (Pt) film 40 is formed to form a lower electrode, and spin coating, organometallic chemical vapor deposition, sputtering, or liquid source (SMDCD) is formed on the semiconductor substrate 10. mixed chemical deposition) method, after forming the PbBi 2 Ta 2 O 9 thin film 41 of 1000 Å to 2000 Å thick, PbBi 2 Ta 2 O 9 thin film 41, platinum (Pt) film 40, a titanium nitride The ride layer 39 and the titanium layer 38 are selectively etched to form a pattern.

다음으로, 도 2b에 도시한 바와 같이, 캐패시터 형성이 완료된 후 층간절연막을 형성하여 평탄화하는 과정에서 PbBi2Ta2O9막(41)으로 수소가 침투하는 것을 방지하기 위하여, 반도체 기판(30)상에 졸겔(sol-gel), 유기금속화학기상증착법, 또는 LSMCD 방법으로 SrBi2-xTa2O9-x막(42)을 500 Å 내지 1000 Å 두께로 형성하여 PbBi2Ta2O9박막(41)을 감싸도록 한다. SrBi2-xTa2O9-x막 형성시 열처리(annealing) 온도는 500 ℃ 내지 700 ℃가 되도록하여 PbBi2Ta2O9막이 휘발되는 것을 방지한다. 상기 온도 범위에서 SrBi2-xTa2O9-x막을 열처리하면 SrBi2-xTa2O9-x막은 완전히 결정화되지 않고 비정질과 결정질이 함께 있는 상태가 된다.Next, as shown in FIG. 2B, in order to prevent hydrogen from penetrating into the PbBi 2 Ta 2 O 9 film 41 in the process of forming and planarizing the interlayer insulating film after the capacitor formation is completed, the semiconductor substrate 30 is formed. PbBi 2 Ta 2 O 9 thin film by sol-gel, organometallic chemical vapor deposition, or LSMCD method to form a SrBi 2-x Ta 2 O 9-x film 42 to a thickness of 500 1000 to 1000 Å Enclose (41). In forming the SrBi 2-x Ta 2 O 9-x film, the annealing temperature is set to 500 ° C. to 700 ° C. to prevent volatilization of the PbBi 2 Ta 2 O 9 film. When heat-treated 2-x Ta 2 O 9- x film is SrBi at this temperature range is in a state with which the crystallization is not completely amorphous and crystalline SrBi 2-x Ta 2 O 9- x film.

다음으로, 도 2c에 도시한 바와 같이 SrBi2-xTa2O9-x막(42) 상에 보호산화막(43)을 형성하고, 보호산화막(43) 및 SrBi2-xTa2O9-x막(42)을 식각하여 PbBi2Ta2O9박막(41)을 노출시킨다. 다음으로, 백금막(44)을 형성하고 선택적으로 식각하여 노출된 PbBi2Ta2O9박막(41)과 접하는 상부전극을 형성한다. 도2a 내지 도2b에서 미설명 도면부호‘31'은 필드산화막,‘32'는 게이트 산화막, '33'은 게이트 전극, '35'는 비트라인을 각각 나타낸다.Next, as shown in FIG. 2C, a protective oxide film 43 is formed on the SrBi 2-x Ta 2 O 9-x film 42, and the protective oxide film 43 and the SrBi 2-x Ta 2 O 9-are formed. The film 42 is etched to expose the PbBi 2 Ta 2 O 9 thin film 41. Next, the platinum film 44 is formed and selectively etched to form an upper electrode in contact with the exposed PbBi 2 Ta 2 O 9 thin film 41. 2A to 2B, reference numeral 31 denotes a field oxide film, 32 a gate oxide film, 33 a gate electrode, and 35 a bit line.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 강유전체막을 SrBi2-xTa2O9-x막으로 보호함으로써, 층간절연막 형성 공정시 발생하는 수소가 캐패시터의 강유전체막으로 흡입되는 것을 방지하는 방법으로, 강유전체 박막이 일정한 잔류분극을 비교적 장시간 유지할 수 있도록하여 강유전체 캐패시터의 특성을 향상시키는 것이 가능하다.The present invention made as described above is a method of protecting the ferroelectric film with the SrBi 2-x Ta 2 O 9-x film to prevent hydrogen generated during the interlayer insulating film forming process from being sucked into the ferroelectric film of the capacitor. It is possible to improve the characteristics of the ferroelectric capacitor by allowing the residual polarization to be maintained for a relatively long time.

Claims (7)

반도체 기판 상부에 캐패시터 하부전극을 형성하는 단계;Forming a capacitor lower electrode on the semiconductor substrate; 상기 하부전극 상에 PbBi2Ta2O9캐패시터 강유전체막을 형성하는 단계;Forming a PbBi 2 Ta 2 O 9 capacitor ferroelectric film on the lower electrode; 캐패시터 상부전극과 접하지 않는 상기 PbBi2Ta2O9캐패시터 강유전체막 표면 및 측면을 덮는 강유전체 보호막을 형성하되, 상기 강유전체 보호막을 500 ℃ 내지 700 ℃ 온도에서 열처리하여 형성하는 단계; 및Forming a ferroelectric protective film covering the surface and side surfaces of the PbBi 2 Ta 2 O 9 capacitor ferroelectric film which is not in contact with the capacitor upper electrode, wherein the ferroelectric protective film is formed by heat treatment at a temperature of 500 ° C. to 700 ° C .; And 상기 PbBi2Ta2O9캐패시터 강유전체막과 접하는 캐패시터 상부전극을 형성하는 단계Forming a capacitor upper electrode in contact with the PbBi 2 Ta 2 O 9 capacitor ferroelectric layer 를 포함하는 강유전체 메모리 소자 제조 방법.Ferroelectric memory device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 강유전체 보호막을,The ferroelectric protective film, SrBi2-xTa2O9-x(x는, 0 < x < 2)로 형성하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.SrBi 2-x Ta 2 O 9-x (x is 0 <x <2). 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 SrBi2-xTa2O9-x막 상에 산화막을 형성하는 단계를 더 포함하는 강유전체 메모리 소자 제조 방법.And forming an oxide film on the SrBi 2-x Ta 2 O 9-x film. 제 1 항에 있어서,The method of claim 1, 상기 캐패시터 강유전체막은,The capacitor ferroelectric film, 스핀 코팅(spin coating), 유기금속화학기상증착법, 스퍼터링 방법 또는 LSMCD(liquid source mixed chemical deposition) 방법으로 형성하는 강유전체 메모리 소자 제조 방법.A method of manufacturing a ferroelectric memory device formed by spin coating, organometallic chemical vapor deposition, sputtering, or liquid source mixed chemical deposition (LSMCD). 제 1 항 또는 제 4 항에 있어서,The method according to claim 1 or 4, 상기 캐패시터 강유전체막은,The capacitor ferroelectric film, 1000 Å 내지 2000 Å 두께로 형성하는 강유전체 메모리 소자 제조 방법.A method of manufacturing a ferroelectric memory device, which is formed to a thickness of 1000 GPa to 2000 GPa. 제 2 항에 있어서,The method of claim 2, 상기 강유전체 보호막은,The ferroelectric protective film, 졸겔(sol-gel), 유기금속화학기상증착법, 또는 LSMCD(liquid source mixedchemical deposition) 방법 형성하는 강유전체 메모리 소자 제조 방법.A method of manufacturing a ferroelectric memory device which is formed by a sol-gel, an organometallic chemical vapor deposition method, or a liquid source mixed chemical deposition (LSMCD) method. 제 6 항에 있어서,The method of claim 6, 상기 강유전체 보호막은,The ferroelectric protective film, 500 Å 내지 1000 Å 두께로 형성하는 강유전체 메모리 소자 제조 방법.A ferroelectric memory device manufacturing method to form a thickness of 500 kHz to 1000 kHz.
KR1019970075075A 1997-12-27 1997-12-27 Method for forming FeRAM Expired - Fee Related KR100291181B1 (en)

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