KR100298445B1 - Oscillator circuit - Google Patents

Abstract

According to the present invention, when the power save mode is released in an IC having a power save mode, such as using an oscillator and reducing power consumption, the time required for the normal operation to be shortened by shortening the time required for normal operation and accordingly the power consumption is reduced. A oscillator circuit designed to reduce the oscillator, comprising: a crystal oscillator for oscillation, a first inverter for receiving and amplifying a fine sine wave oscillated from the crystal oscillator, and an input and an output of the first inverter for amplifying the first inverter A first transmission gate, a second inverter applying an inverted signal of the stop mode signal to the first transmission gate, a third inverter converting the signal amplified by the first inverter into a square wave and outputting the square wave to an internal circuit; Receives a stop mode signal to stop oscillation of the crystal oscillator A transistor, an edge detection circuit that detects that the stop mode signal is relayed, a ring oscillator that receives the output of the edge detection circuit and starts oscillation, and a fourth inverter that inverts the output of the ring oscillator and inputs it to an input terminal. And a second transmission gate separating the output of the fourth inverter and the input terminal of the fourth inverter.

Description

Oscillator Circuitry {OSCILLATOR CIRCUIT}

TECHNICAL FIELD The present invention relates to an oscillator circuit, and more particularly, to an oscillator circuit suitable for reducing power consumption and increasing operating speed.

Hereinafter, an oscillator circuit of the related art will be described with reference to the accompanying drawings.

1 is a circuit diagram showing a conventional oscillator circuit.

As shown in FIG. 1, a crystal oscillator 11 for oscillation outside the IC and a frequency oscillated by the crystal oscillator 11 are input to an input terminal Xin inside the IC and an amplifier for amplifying the same. The first inverter X1 to be used as an amp, the transmission gate 12 for allowing the first inverter X1 to have an amplifier function, and the output signal of the first inverter X1 are stable pulses. Second inverter (X2) which is formed in the internal circuit and output to the internal circuit, the third inverter (X3) which controls the gates of the NMOS and PMOS transistors constituting the transmission gate (12), and in the stop mode (power mode) Save Mode Signal) The pull-down NMOS transistor 13 which makes the signal coming into the input terminal Xin at the "L" level, and the first and second capacitors C1 and C2 for resonance of the crystal resonator 11 are connected. It is configured to include.

The pull-down NMOS transistor 13 has a source connected to the ground terminal Vss, a drain connected to the input terminal Xin, and a stop mode signal Stop_signal_IN connected to the gate in the IC in the stop mode.

The operation of the oscillator circuit configured as described above is as follows.

That is, when the crystal oscillator 11 and the first and second capacitors C1 and C2 for resonance are applied to the outside of the IC and the power supply voltage Vcc is applied to the IC, the crystal oscillator 11 receives an initial stage from the crystal oscillator 11 to the input terminal Xin. Minute sine waves

First, when the stop mode signal is "L", the input and output of the first inverter X1 are shorted to the transmission gate 12 by the fine sine wave input to the input terminal Xin.

Here, the transmission gate 12 is made to have a resistance of about IMΩ, and when the stop mode signal is "L", the transmission gate 12 is turned "ON".

Subsequently, since the input and the output of the first inverter X1 are connected to the transmission gate 12, the first inverter X1 operates as an amplifier to amplify the fine sine wave oscillated by the crystal oscillator 11.

At this time, the transmit TUS gate 12 is "ON" so that the output amplified by the first inverter X1 can be fed back to the input of the first inverter X1.

Since the output of the first inverter X1 comes out as a sine wave, the square wave comes out through the second inverter X2 for writing to a logic element.

Here, the pull-down NMOS transistor 13 is in the "OFF" state.

On the other hand, when the stop mode signal is "H", the transmission gate 12 is "OFF" and the pull-down NMOS transistor 13 is "ON".

That is, the pull-down NMOS transistor is turned off so that the fine sine wave entering the input terminal Xin cannot be amplified by the first inverter X1 and the fine sine wave entering the input terminal Xin is forced to L. (13) is operated.

Therefore, the output of the 2nd inverter X2 becomes "L".

2 is a timing for input and output when using a conventional oscillator circuit.

As shown in FIG. 2, the time required for normal operation of the oscillator becomes long when exiting the power save mode.

However, there have been the following problems in such a prior art oscillator circuit.

That is, for the oscillator to operate normally, the oscillator operates normally when the fine sine wave input to the input terminal passes through the inverter and the amplified signal is fed back to input the input terminal infinitely. It takes tens of seconds to stabilize the oscillation.

Because of this, in ICs with a power save mode, such as an MCU, the oscillator takes a long time to exit from the power save mode. Until then, the IC does not operate until the chip operates when the oscillator operates normally. Consumption and speed decrease.

Therefore, the present invention has been made to solve the above problems, and when the power save mode is released in the IC with the power save mode to reduce the power consumption by using an oscillator such as an MCU, the oscillator should operate normally to speed up the normal operation. The object is to provide an oscillator circuit that shortens the time taken for operation and thus reduces power consumption.

1 is a circuit diagram showing a conventional oscillator circuit

2 is a timing diagram showing an input and an output when using a conventional oscillator circuit.

3 is a circuit diagram showing an oscillator circuit according to the present invention.

4 is a timing diagram showing an input and an output when using an oscillator circuit according to the present invention.

Explanation of symbols for main parts of the drawings

21: crystal oscillator 22: first transmission gate

23: first NMOS transistor 24: edge detection circuit

25 ring oscillator 26 third transmission gate

An oscillator circuit according to the present invention for achieving the above object is a crystal oscillator for oscillation, a first inverter for receiving and amplifying a fine sine wave oscillated from the crystal oscillator, and a first inverter for amplifying the first inverter A first transmission gate connecting an input and an output of the first transmission gate, a second inverter applying an inverted signal of a stop mode signal to the first transmission gate, and converting the signal amplified by the first inverter into a square wave to an internal circuit. A third inverter for outputting, a first NMOS transistor receiving a stop mode signal to stop oscillation of the crystal oscillator, an edge detection circuit for detecting that the stop mode signal is relayed, and an oscillation in response to the output of the edge detection circuit. The ring oscillator and the output of the ring oscillator are inverted and input to the input terminal. It characterized in that the fourth inverter and an output of said edge detection circuit comprises a second transmission gate for high when separating the output and input terminal of the fourth inverter.

Hereinafter, an oscillator circuit according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram showing an oscillator circuit according to the present invention.

As shown in FIG. 3, the crystal oscillator 21 for oscillation, the first and second capacitors C1 and C2 for resonance of the crystal oscillator 21, and the fine sine wave oscillated in the crystal oscillator 21. A first inverter (X1) for receiving and amplifying, a first transmission gate (22) connecting an input and an output of the first inverter (X1) for amplifying the first inverter (X1), and the first transmission gate A second inverter (X2) for applying an inverted signal of the stop mode signal to the gates of the NMOS and PMOS transistors constituting the (22), and the signal amplified by the first inverter (X1) is converted into a square wave to an internal circuit; A third inverter (X3) to output, the first NMOS transistor 23 to stop the oscillation of the crystal oscillator 21 when the stop mode signal is "H", and to detect that the stop mode signal is relayed (Release) Edge detection circuit 24 and exit of the edge detection circuit 24 And a fourth oscillator (X4) for inverting the output of the ring oscillator (25) and inputting it to the input terminal (Xin).

Here, the ring oscillator 25 receives a second transmission gate 25a connecting the feedback loop of the ring oscillator 25 and an output of the second transmission gate 25a when the stop mode signal is “L”. Of the fifth inverter X5 inverted and outputted, the first and second RC delay units 25b and 25c for RC delaying the output of the fifth inverter X5, and the second RC delay unit 25c. A sixth inverter (X6) for receiving and feeding back an output, a fourth inverter (X4) for receiving an output of the ring oscillator (25) and an inverted signal to an input terminal (Xin), and the edge detection circuit (24). Is composed of a second NMOS transistor 25d which prevents the output of the fifth inverter X5 from floating when its output is " H ".

In addition, when the output of the edge detection circuit 24 is " H ", the output of the fourth inverter X4 is composed of a third transmission gate 26 that separates the input terminal Xin.

Meanwhile, the first and second RC delay units 25b and 25c each include one resistor R1 and R2 and one capacitor C3 and C4.

In addition, the inverter X7, which is not described herein, controls the operation of the second transmission gate 25a together with the output signal of the edge detection circuit 24, and the inverter X8 inverts the first RC delay unit 25b signal to invert the second RC delay. It outputs to the part 25c.

Referring to the operation of the oscillator circuit according to the present invention configured as described above as follows.

When the power supply voltage Vcc is applied to the IC circuit, a voltage is applied to the input terminal Xin and the output terminal Xout to start the oscillation by the crystal oscillator 21 and the first and second capacitors C1 and C2. The output of the fine oscillator is applied to the input terminal Xin.

First, when the stop mode signal is "L", the oscillator output (sine wave) applied to the input terminal Xin has a first inverter ("ON") in which the first transmission gate 22 is "ON" and the input and output are tied together to operate as an amplifier. The waveform amplified and input to X1) is output to the output terminal Xout, and the sine wave output is applied to the crystal oscillator 21 so that it can be continuously oscillated, and the output of the crystal oscillator 21 is again input terminal ( The peak voltage is increased at the peak of the oscillating sine wave until the oscillation becomes similar to the supply voltage while passing through a closed circuit applied to Xin and amplified by the first inverter X1 and applied to the crystal oscillator 21, and then at the supply voltage. It is fixed.

On the other hand, the edge detection circuit 24 continuously outputs the "H" state because no pulse is generated at the time of "L", and this output and the output of the inverter X7 of the ring oscillator 25 produce a second transmission gate ( 25a) becomes the " OFF " state, and the second NMOS transistor 25d is " ON " so that " L " is applied to the input of the fifth inverter X5 so that the ring oscillator 25 does not operate and the fourth The third transmission gate 26 is “OFF” such that the output of the inverter X4 is not transmitted to the input terminal Xin.

When the stop mode signal is "H", the first NMOS transistor 23 is "ON", the first transmission gate 22 is "OFF", and the input terminal Xin is fixed to "L" and fed back. Since the one transmission gate 22 is "OFF", the oscillation is stopped.

At this time, since the output of the edge detection circuit 24 becomes "H", the feedback path for oscillation of the ring oscillate 25 is "OFF", so that the second transmission gate 25a and the third transmission gate 26 are also "OFF". "do.

When the stop mode signal changes from "H" to "L", the edge detection circuit 24 outputs the "L" signal, and the second transmission gate 25a is "ON" during the "L" period, and the ring oscillator Since the second NMOS transistor 25d of (25) is " OFF ", the ring oscillator 25 starts oscillation.

At this time, since the third transition gate 26 that connects the output of the ring oscillator 25 to the input terminal Xin is “ON”, the oscillation of the ring oscillator 25 is transmitted to the input terminal Xin, and the initial crystal is transmitted. The oscillator 21 increases the voltage at which oscillation starts, so that oscillation is normal within a short time, and after a predetermined time (until the output of the negative edge detection becomes from "L" to "H"), the third transmission gate 26 ) Is " OFF " by inverter X7 so that only oscillation by crystal oscillator 21 is performed.

4 is a timing diagram showing an input and an output when using the oscillator circuit according to the present invention.

As shown in FIG. 4, in the power down mode, oscillation of the oscillator may be stopped to reduce power consumption of the IC, and the time taken to start the oscillator may be shortened during the power down mode relay.

As described above, in the power down mode in the oscillator circuit according to the present invention, the oscillation of the oscillator can be stopped to reduce the power consumption of the IC, and the power down mode relay can shorten the time taken to start the oscillator again. As the time is shorter, power consumption is reduced, which is advantageous in the device using the battery as a power source, and the operation start time is short, which is advantageous in high speed operation.

Claims (3)

A crystal oscillator which oscillates by applying a power voltage to an input terminal and an output terminal, A first inverter for receiving and amplifying a sine wave oscillated by the crystal oscillator; A first transmission gate connecting an input and an output of the first inverter to amplify the first inverter; A second inverter for applying an inverted signal of a stop mode signal to the first transmission gate; A third inverter converting the signal amplified by the first inverter into a square wave and outputting the converted signal to an internal circuit; A first NMOS transistor having a source connected to the input terminal, a drain connected to the ground terminal, and an external stop mode signal applied to a gate to stop oscillation of the crystal oscillator; An edge detection circuit for detecting that the stop mode signal is delayed; A ring oscillator for receiving the output of the edge detection circuit and starting oscillation; A fourth inverter for inverting the output of the ring oscillator and inputting it to an input terminal; And a second transmission gate separating the output of the fourth inverter and the input terminal when the output of the edge detection circuit is high. The ring oscillator of claim 1, wherein A third transmission gate connecting the feedback loop of the ring oscillator when the stop mode signal is "L", A fifth inverter for inverting and outputting the output of the third transmission gate to an input; First and second RC delay units configured to RC-delay the output of the fifth inverter; A sixth inverter configured to receive and feed back the output of the second RC delay unit; A source connected to the third transmission gate, a drain connected to a ground terminal, and a gate connected to the edge detection circuit to prevent the output of the fifth inverter from floating when the output of the edge detection circuit is “H”; An oscillator circuit comprising two NMOS transistors. The method of claim 2, And the first and second RC delay units comprise one resistor and one capacitor, respectively.