KR100281267B1 - Word Line Leakage Current Control Device for Semiconductor Memory Devices - Google Patents

Abstract

The present invention relates to a device for controlling word line leakage current of a semiconductor memory device, and reduces leakage current by using a well bias level (back bias voltage) as a word line bias, rather than a conventional ground level when off.

Description

Word Line Leakage Current Control Device for Semiconductor Memory Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for controlling word line leakage current of a semiconductor memory device, and more particularly, to a word line bias circuit which reduces leakage current by using a well bias as a word line bias when the word line is not grounded.

Conventionally, a method of supplying a ground level bias to a word line, which is an input line of several transistors, has been used.

However, ground level bias could not completely block the current flow of the transistor due to various factors such as external noise.

In addition, even if the complete ground level is supplied with word line bias, some leakage current is generated due to the transistor characteristics.

Moreover, as the size of transistors become smaller and more highly integrated, the number of transistors placed in a limited area has increased greatly. As the power supply voltage is lowered to reduce power consumption, the leakage current during off flowing through the transistor frame increases power consumption. This has caused the leakage of data stored on one node of the node.

In the case of DRAM, a large capacity cell capacitor is needed to improve the data retention time due to such a problem, which requires a lot of consideration in the process.

Accordingly, the present invention has been devised to solve the above-mentioned problem, and is a word for reducing leakage current flowing through a cell transistor by using a pickup bias supplied to a well below ground level by a bias of a word line, which is an input terminal of the cell transistor. The purpose is to provide a line bias circuit.

1 is a characteristic curve showing a relationship between a leakage current flowing through a cell transistor connected to a word line and a gate-source input voltage.

2 is a basic conceptual view of the present invention.

3A is a structural diagram of a typical cell block and word line driver.

3b is a structural diagram of a general main word line and a sub word line.

4 is a wordline bias circuit diagram in accordance with an embodiment of the present invention.

5 is a detailed circuit diagram of the level shifter of FIG.

<Explanation of symbols for main parts of drawing>

100: back bias voltage driver control unit 110: well bias control unit

120: delay block 130: level shifter

200: back bias voltage driver 210: sub-wordline pull-up driver

220: sub-wordline pulldown driver

The word line bias circuit of the present invention for achieving the above object is a well for receiving a block address and a word line selection address and supplying the turn-on voltage of the sub-word line cell transistor only when both the cell block and the main word line are selected. A bias control unit 110, a delay block 120 which receives an output signal of the well bias control unit and delays a predetermined time to prevent a current path, and an output signal of the well bias control unit is a low level potential A level shifter 130 for controlling a leakage current by outputting a high level potential and outputting a low level potential when the output signal is a high level potential, and being connected to an output terminal of the delay block to drive a sub-word line The NMOS transistor (MNI) receiving high voltage and the output signal of the NMOS transistor A sub-word line pull-up driver 210 for driving the word line to a high potential on the main word line, and a sub-word line pull-down for receiving the output signal of the level shifter to drive the sub-word line with a well bias voltage It characterized in that it comprises a driver (220).

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a characteristic curve showing a change in leakage current according to a change in bias applied between a gate, an input terminal of a transistor, and a source, an active terminal.

The vertical axis is a log scale, and it can be seen that the amount of leakage current decreases rapidly when the gate-source voltage of the horizontal axis is smaller than the threshold voltage.

Here, the following relation holds between the gate-source bias and the leakage current at a level lower than the threshold voltage.

Ids = {(U * Cox * W) / L} * (n-1) * Vt ² * exp [(Vgs-Vt) / n * Vt] * (1-e ^{-vds / vt} )

Where U is the mobility of electrons or holes, Cox is the capacitance of the transistor gate insulator, W is the width of the gate, L is the channel length, Vt is the threshold voltage, and n is the proportional constant.

That is, it can be seen that the leakage current is drastically reduced when a bias of a lower level is applied to the word line, which is the gate input of the transistor, when the transistor is turned off.

2 illustrates a basic configuration diagram of a circuit for supplying an off-well bias to a word line. The back bias voltage driver controller 100 receives a signal for turning on a word line and a signal for turning off a back bias voltage driver 200. The back bias voltage driver 200 receives the input and supplies the back bias voltage output from the well bias receiver to the word line.

3A is a general structural diagram of a wordline driver and a cell block.

For example, in the case of DRAM, the operation of selecting a word line first selects a block by using a decoded address (in this case, the block selection address is AD AB), and receives another address in the selected block. The word line is selected. One main word line has four word lines as shown in FIG. 3B. When the word lines are accessed, one word line is accessed by receiving an address (AD CD) again. A circuit that selects one word line and biases the selected word line is called a word line driver.

In FIG. 3B, when the main word line is turned on, the node n-boot is bootstrapped in order to drive the word line strongly.

When the main word line is turned off, the word line is brought to ground level to turn off the cell transistors belonging to the word line.

In order to supply back bias to the word line when off, supply a well bias level of power to the source terminal of transistor Q2 instead of the ground level, and swing the input AD CD to the same level to swing Q2 from the well bias level to the mains voltage level. Should be. For this purpose, the AD CD signal may be used as the input terminal of the transistor Q2 via the level shift 130.

4 is a word line bias circuit according to an exemplary embodiment of the present invention, which includes a back bias voltage driver controller 100 for receiving a block address and a word line selection address to supply turn-on voltages of a sub word line, and the back bias circuit. The back bias voltage driver 200 receives the output signal of the bias voltage controller and supplies a voltage on the main word line or a back bias voltage to the sub-word line.

The back bias voltage driver controller 100 receives the block address and the word line selection address and supplies a turn-on voltage of a sub-word line when both the cell block and the main word line are selected. And a delay block for receiving the output signal of the well bias control unit 110 and delaying it for a predetermined time, and a level shifter 130 for receiving the output signal of the well bias control unit 110 and outputting a lower potential. .

The well bias control unit 110 may include a first inverter for inverting a block address signal, a NAND gate receiving the first inverter output signal and a word line selection address, a second inverter receiving the output signal of the NAND gate, And an exclusive OR for receiving the second inverter output signal and a word line selection address.

The level shifter 130 is shown in FIG. 5.

It is used to connect high voltage paths to circuits using low voltage. That is, when a low level potential is received, a high level potential is output, and when a high level potential is received, a low level potential is output.

The back bias voltage driver 200 may be connected to an output terminal of the delay block 120 so as to apply a boost voltage (high voltage) to a gate terminal to strongly drive a sub-word line, and the first NMOS transistor; A sub-word line pull-up driver 210 for receiving the output signal of the 1 NMOS transistor and driving the sub-word line to a high potential on the main word line, and receiving the output signal of the level shifter 130 to receive the sub-word line. It consists of a sub-wordline pull-down driver 220 for driving the wordline with well bias.

First, if the block address and word line selection address are high, high is output to the exclusive or output terminal.

Accordingly, the sub-wordline pull-up driver 210 is turned on so that the high potential on the main wordline is transferred to the sub-wordline.

Meanwhile, the low signal inverted by the level shifter 130 is applied to the input terminal of the sub-word line pull-down driver 220 to be turned off.

Here, the delay block serves to prevent the current path from being formed by turning on the sub-wordline pull-up driver 210 and the server-wordline pull-down driver at the same time.

Second, when both the block address and the word line selection address are low, when the block address is high and when the word line selection address is low, when the block address is low and the word line selection address is high, the exclusive or output stage A low signal is always output to the sub-wordline pull-up driver 210 and the sub-wordline pull-down driver 220 is turned on and the well bias voltage is applied to the sub-wordline.

Therefore, by supplying a lower level voltage to the word line when off, the leakage current flowing through the transistor below the threshold voltage can be reduced.

Application of the present invention to the word line bias of the semiconductor memory device can reduce the leakage current, which is a problem in the memory device, which is miniaturized and compacted by lowering the word line bias level during off, reducing power consumption and reliability. There is an effect that can improve the yield by the present operation.

Claims (1)

A well bias control means for receiving a block address and a word line selection address and supplying a turn-on voltage of the sub-word line cell transistor only when both the cell block and the main word line are selected, and an output signal of the well bias control means. A delay block for receiving a delay for a predetermined time to prevent a current path, and a high level potential if the output signal of the well bias control means is a low level potential, and a low level potential if the output signal is a high level potential A level shifter for controlling a leakage current by controlling a leakage current, an NMOS transistor connected to an output terminal of the delay block to receive a high voltage to drive a sub-word line, and a gate to receive an output signal of the NMOS transistor To drive the sub-wordline to a high potential on the main wordline And a line pull-up driver and a sub-word line pull-down driver for receiving the output signal of the level shifter through a gate and driving the sub-word line to a well bias voltage connected to a source. Line leakage current controller.

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