KR100259039B1 - Capacitor maunfacturing method of semi-conductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to prevent the reduction of static capacitance by forming a tungsten silicide film on a peripheral portion of a lower electrode. CONSTITUTION: A lower electrode(26) is formed on a semiconductor substrate(10). A hemispherical grain is formed on a surface of the lower electrode(26). A tungsten film is formed on a whole face of the semiconductor substrate(10). The tungsten film is changed to a tungsten silicide film(29) by performing an annealing process for the tungsten film. The tungsten film is etched in order that the tungsten film remains on a peripheral portion of the lower electrode(26). A dielectric layer is formed by laminating dielectric material on the lower electrode(26) formed with the hemispherical grain. An annealing process for the dielectric layer is performed. An upper electrode is formed on the dielectric layer.

Description

Capacitor maunfacturing method of semi-conductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor manufacturing method of a semiconductor device. More specifically, a tungsten silicide film is formed around a lower electrode on which a hemispherical grain (HSG) is formed on a surface thereof. The present invention relates to a capacitor manufacturing method of a semiconductor device which prevents the capacitance of the capacitor from being reduced by forming a reactant layer around the lower electrode by heat treatment of the dielectric layer formed on the lower electrode.

Recently, as semiconductor devices have been highly integrated, semiconductor devices such as DRAMs have become more sophisticated and their sizes have become smaller.

Therefore, the planar area of the chip formed on the semiconductor substrate is smaller than the memory capacity, and the height of the structure of the chip is relatively increased to compensate for the functional problem caused by the reduction of the planar area. In this case, in order for a semiconductor device having a reduced area on a plane to function normally, a voltage or capacitance applied to the semiconductor device must be maintained at a constant value, so that a circuit having a more complicated configuration is realized on an assigned narrow plane of the semiconductor device. Should be.

In particular, the structure of the capacitor of a DRAM having a transistor for amplifying an electric signal and a capacitor for storing information has undergone many changes.

For example, a capacitor of 1M DRAM has a planar structure and adopts a silicon oxide film as a dielectric film, and a capacitor of 4M DRAM has a stacked structure, and a silicon oxide film and a silicon nitride film are alternately used as the dielectric film. The laminated ONO structure is adopted. In addition, the capacitor of 16M DRAM has a stack structure and adopts a NO structure in which a nitride film and an oxide film are stacked as the dielectric film, and the capacitor of 64MDRAM has a cylinder structure and adopts a NO structure as the dielectric film or a stacked structure. HSG was formed on the lower electrode to increase the surface area and adopt the NO structure as the dielectric film. In addition, the capacitor of the 256M DRAM or 1G DRAM of more than 64MDRAM is composed of a three-dimensional structure, such as a stack structure, a cylinder structure and a capacitor on bit line (COB) structure, and the hemispherical grain is formed on the lower electrode and inherently Adopted the entire floor.

However, even when the structure of the capacitor is developed, the capacitor basically has a structure in which a dielectric layer is inserted between two electrodes, and the capacitance of the capacitor depends on the dielectric constant of the dielectric layer, the area of the opposite electrode, and the spacing between the electrodes. The capacitance of the capacitor is proportional to the area of the opposite electrode and inversely proportional to the spacing between the electrodes.

In semiconductor manufacturing, what is mainly studied to maintain a proper capacity is a method of increasing the area of the opposite electrode. This trend was also focused on the changing trend of capacitors actually used in semiconductor devices.

One method of increasing the area of the electrode is to develop a three-dimensional lower electrode that increases the area by forming a three-dimensional high-level capacitor electrode of a conventional planar shape or giving structural bending. Stack structures, trench structures, cylinder structures, and COB structures are all examples of this.

The development of such a lower electrode is advantageous in terms of time, but it is generally required to go through a plurality of precise processing steps. Thus, in many cases there has been a skeptical assessment of the practical applicability due to the increased costs due to the complexity of the process and the limitations of the Design Rule. In addition, in the highly integrated semiconductor device, there is a problem that it is difficult to secure sufficient and stable capacitance even when using these three-dimensional structures.

Another method for increasing the electrode area of a capacitor in a semiconductor device is to use the material's own properties such as HSG formation. The HSG formation process has been proposed by Watanabe et al. (Reference: SSDM '92, pp422-424, "Hemispherical Grained Silicon Formation on In-Situ Phorus Doped Amorphous-Si Using The Seeding Method", H. Watanabe. Et al.) It is a process using the phenomenon of forming a hemispherical shape in which the surface energy is the most stable form by the migration of silicon in the temperature range of the crystal and amorphous state of silicon. Therefore, the HSG forming process is characterized in that silicon-based gas (Si ₂ H ₆ , SiH ₄ ) with high surface reactivity or silicon in the film protrudes around each abnormal part by structural defects or some deposited particles on the wafer surface. It is used as a method of forming a rough surface having a plurality of protrusions in the formed film by using the property of forming a region having a shaped shape, and thus increasing the surface area to increase the capacitance of the capacitor of the semiconductor device.

However, the method using the HSG also has the following problems.

First, when the lower electrode of the capacitor is doped with an impurity, as the size of the HSG increases, there is not enough impurities diffused out of the lower electrode, thereby increasing the thickness of the intermediate dielectric layer and thus reducing the capacitance. In addition, in order to solve this problem, when the lower electrode is forcibly doped by POCl ₃ deposition, phosphorus pentoxide (P ₂ O ₅ ) film is formed and wet etching is required. In addition, wet etching reduces the area of HSG by partially reducing the surface area. Even when impurities are implanted by ion implantation, there is a problem in that protrusions are reduced by impact.

Second, after forming the base of the lower electrode on the wafer, when forming the HSG on the electrode surface, HSG is formed in the space between the lower electrodes in addition to the electrode surface to destroy the insulation between the electrodes. In order to prevent such breakdown, dry etching is performed to break the bridge of HSG silicon between the lower electrodes. At this time, since the HSG of the electrode surface is also etched, the area increase effect of the electrode is halved.

Third, in the HSG formation process using low pressure chemical vapor deposition (LPCVD) except the selective HSG formation process, HSG is formed to the back side of the wafer, so it is likely to act as a particle in the subsequent process, and the front coating, wet etching, and coating removal to remove it Such process should be added.

Fourth, the biggest problem in the HSG formation process is low process margin. That is, since HSG is formed in the transition temperature range from amorphous silicon to polysilicon, the HSG formed is highly sensitive to temperature control, and the size and density reproducibility between the wafer and the wafer or the run and the run are poor. .

On the other hand, in the short term, the dielectric layer materials that can be used in DRAM are somewhat limited, and the thickness of the dielectric layer is limited in the process technology. However, the dielectric layer between the capacitor upper electrode and the lower electrode has an important effect on the capacitor capacity.

Materials used as dielectric layers in the manufacture of semiconductor devices include general silicon oxide films and silicon nitride films. In semiconductor devices, these single films or NO or 0-NO films in combination with these films are used. In recent years, high dielectric constants such as tantalum oxide (Ta ₂ O ₅ ) having a dielectric constant 3 to 4 times larger than that of nitride films have been developed and used to increase capacitance.

However, in a capacitor formed by forming a lower electrode of polysilicon and then forming a high dielectric film such as tantalum oxide, there is a problem in that leakage current is easily generated and insulation breakdown voltage is lowered.

Meanwhile, an additional heat treatment process such as heat treatment in an ultraviolet and ozone environment and a dry oxygen heat treatment process are performed to improve the characteristics of the dielectric layer film as a method for eliminating problems such as leakage current.

The subsequent heat treatment process is due to the presence of oxygen vacancies in the tantalum oxide with arsenic (As) applied. Oxygen pore density is closely connected to high leakage current and low breakdown voltage when driving the capacitor, causing initial process failure. The heat treatment can remove oxygen pores of tantalum oxide and also remove impurities such as carbon.

However, a new problem arises when such an additional heat treatment process is performed. A new problem will be described below with reference to the drawings.

1 is a view showing an example of a conventional semiconductor device capacitor.

The lower electrode 12 is formed on the semiconductor substrate 10 while filling the contact hole with an interlayer insulating film 11 having a contact hole interposed therebetween. A reactant layer 15 of silicon oxide is formed on the lower electrode 12, and a tantalum oxide film 14 having a high dielectric constant is deposited on the entire surface of the interlayer insulating layer including the reactant layer. Above the tantalum oxide film 14 is a titanium nitride film 16 which functions as an intermediate film, and above the titanium nitride film 16, a silicon film 18 serving as an upper electrode is formed.

In the structure of the semiconductor device capacitor, the reactant layer 15 made of silicon oxide reacts with the silicon component of the lower electrode 12 by a heat treatment performed to remove oxygen voids and impurities present in the tantalum oxide film 14. Produced reactant. The reactant layer 15 is not a high dielectric material and serves to increase the thickness of the dielectric layer between the silicon film 18 and the lower electrode 12 serving as the upper electrode.

Therefore, the value of the capacitance of the capacitor is reduced compared to the theoretical single tantalum oxide film which does not undergo heat treatment, and there is no particular advantage over other dielectric films. In addition, a problem of malfunction due to a low capacitance value may also occur.

As another example, a lower electrode base is formed of polysilicon, a selective growth type HSG structure is formed on the surface thereof, and a high dielectric film such as tantalum oxide is formed thereon, and then a silicon film or a titanium nitride film and the upper electrode are formed thereon. And a silicon film for forming a capacitor of a semiconductor device. At this time, in the state in which a film is formed of tantalum oxide as a dielectric on the silicon lower electrode and arsenic is deposited, heat treatment in a UV or ozone environment or a dry oxygen heat treatment process is performed to improve the characteristics of the dielectric film having a high possibility of leakage. Due to the reaction between the doped silicon film and the tantalum oxide film used for the lower electrode, a reactant layer called silicon oxide is formed between the silicon film for the lower electrode and the tantalum oxide film. Therefore, even in this case, the dielectric constant of the reactant layer is lower than that of tantalum oxide, and the thickness of the dielectric layer is increased, thereby causing a problem of lowering the capacitance.

In the capacitor of the tantalum oxide dielectric layer, when the lower electrode is laminated with silicon, the upper electrode is nitride such as titanium, and the silicon compound and silicon are sequentially stacked, when the operating voltage is applied to the capacitor, the minimum capacitance to the maximum capacitance value is stable. The ratio of the capacitance should be secured, but in the case of reverse voltage with low potential on the upper electrode side, the electrostatic depletion region increases on the silicon lower electrode surface, which reduces the capacitance compared to the forward voltage. The larger the problem was, the less the reliability of the capacitor was caused. Therefore, it was necessary to lower the resistance value of the lower electrode.

Disclosure of Invention An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device, which can prevent the reactant layer from being formed around the lower electrode by heat treatment of the dielectric layer formed on the lower electrode on which the HSG is formed. To provide.

1 is a cross-sectional view showing an example of a conventional semiconductor device capacitor.

FIG. 2 is a cross-sectional view illustrating a state in which a photoresist is applied to the entire surface of a wafer after laminating a first conductor film on an interlayer insulating film having contact holes on a semiconductor substrate in the process of forming a capacitor of the semiconductor device according to an embodiment of the present invention. to be.

FIG. 3 is a cross-sectional view showing a state in which a photoresist pattern is formed by exposing and developing a photoresist according to a lower electrode pattern in the state of FIG.

4 is a cross-sectional view illustrating a state in which a lower electrode is formed by etching a first conductor layer using the photoresist pattern as an etching mask in the state of FIG. 3.

FIG. 5 is a cross-sectional view illustrating a state in which a photoresist pattern is removed in the state of FIG. 4 and a HSG (Hemispherical Grain) is formed on the lower electrode surface.

FIG. 6 is a cross-sectional view showing a state in which a thin layer of tungsten or titanium metal is deposited by sputtering or chemical vapor deposition on the surface of the lower electrode of FIG.

7 is a state in which a metal silicide is formed on the surface of the lower electrode by heat treatment in the state of FIG. 6, and the final lower electrode of the capacitor is formed by removing residual metal that is not silicided around the lower electrode by wet etching. It is sectional drawing which shows.

8 is a cross-sectional view illustrating a state in which a dielectric layer is formed on the final lower electrode of FIG. 7.

9 is a cross-sectional view illustrating a state in which an upper electrode is formed on the dielectric layer of FIG. 8.

10 is a cross-sectional view illustrating another embodiment of a method of manufacturing a capacitor of a semiconductor device according to the present invention.

※ Explanation of symbols for main parts of drawing

10: semiconductor substrate 11, 22: interlayer insulating film

12: lower electrode 14: tantalum oxide film

15: reactant layer 16: titanium nitride film

18: silicon film 23: first conductor film

24: photoresist 25: photoresist pattern

26, 36: lower electrode 27: HSG

28: metal film 29, 39: metal silicide film

30, 40: dielectric layer 32, 42: upper electrode

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming a lower electrode on a semiconductor substrate using a silicon-containing material; forming an HSG on the lower electrode; Stacking a dielectric material to form a dielectric layer, heat treating the dielectric layer, and forming an upper electrode on the dielectric layer, wherein the HSG is formed on the lower electrode. Forming a tungsten film on the entire surface of the semiconductor substrate; Only leaving a tungsten silicide film It is characterized by comprising a system.

The dielectric material may be a metal oxide such as tantalum oxide, and the HSG may be formed by a selective growth HSG method.

In addition, after the dielectric layer is formed, an intermediate layer may be further formed on the dielectric layer using any one of titanium, tungsten, nitrides of titanium and tungsten, and silicon compounds.

In addition, the wet etching may be performed using sulfuric acid.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 to 9 are cross-sectional views illustrating a process of forming a capacitor of a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 2, after the first conductor film 23 is laminated on the semiconductor substrate 10 on which the interlayer insulating film 22 having the contact holes (not numbered) is formed, the photoresist 24 is entirely covered. Apply to In this case, the contact hole is completely filled by stacking the first conductor film 23, and the first conductor film 23 is made of polysilicon or amorphous silicon material to which impurities are added, and the photoresist 24 is It is applied to perform photolithography for patterning the lower electrode of the capacitor.

Next, as shown in FIG. 3, the photoresist 24 is exposed and developed according to the lower electrode pattern to form the photoresist pattern 25.

Next, as shown in FIG. 4, the first conductor layer 23 is etched using the photoresist pattern 25 as an etch mask to form a lower electrode 26.

Subsequently, as shown in FIG. 5, the photoresist pattern 25 is removed and the HSG 27 is formed on the surface of the lower electrode 26. The HSG may be formed by continuously supplying silicon-based gas in a hot-walled process furnace, but supplying silicon-based gas only for a short time to form initial crystal nuclei, and then heat treating at 700 ° C. to 1000 ° C. to form the lower electrode 26. It is preferable to adopt a selective growth type HSG method in which HSG is formed by migration of silicon atoms. The HSG forming process is to increase the capacitance of the capacitor by increasing the surface area of the lower electrode. Thereafter, a process of stripping or ashing the photoresist pattern 25 remaining on the semiconductor substrate 10 is further performed.

Subsequently, as shown in FIG. 6, a metal film 28 such as tungsten or titanium is thinly stacked on the surface of the lower electrode 26 on which the HSG 27 is formed by sputtering or chemical vapor deposition (CVD).

Next, the metal film 28 is heat treated at 500 ° C to 1000 ° C. In this case, the metal film 28 around the lower electrode 26 reacts with the silicon component of the lower electrode 26 to be modified into a metal silicide film such as a tungsten silicide film and a titanium silicide film. Subsequently, by performing a wet etching process using a chemical having an excellent etching selectivity with respect to the metal film 28, a metal silicide film such as a tungsten silicide film, a titanium silicide film, or the like may be formed only around the lower electrode 26 as illustrated in FIG. 7. Remaining 29) forms the final lower electrode 26 of the capacitor. At this time, the wet etching process uses sulfuric acid, and the metal silicide layer 29 reacts with a silicon component of the lower electrode 26 by heat treatment of a tantalum oxide layer serving as a dielectric layer to form a reactant layer. It is to prevent the increase in the overall thickness.

Subsequently, as shown in FIG. 8, the dielectric layer 30 is formed of a high dielectric tantalum oxide on the completed lower electrode 26. Subsequently, a heat treatment process is performed to remove the oxygen voids and impurities of the dielectric layer 30 to improve the film quality. In this case, since the metal silicide layer 29 having already been silicided exists in the periphery of the lower electrode 26. It is suppressed that the lower electrode 26 is oxidized to form a reactant layer to increase the thickness of the dielectric layer 30.

Finally, as shown in FIG. 9, the upper electrode 32 is formed of a conductive material such as polysilicon on the dielectric layer 30.

FIG. 10 is a process cross-sectional view for explaining another embodiment of a capacitor manufacturing method of a semiconductor device according to the present invention having a cylindrical lower electrode.

Referring to FIG. 10, an HSG and a cylindrical lower electrode 36 made of silicon material doped with impurities are formed in an interlayer insulating film 22 having a contact hole (not numbered) formed thereon, and a cylinder having an HSG formed thereon. The lower electrode 36 is completed by forming a metal silicide film 39 such as titanium silicide and tungsten silicide in the periphery of the mold lower electrode 36. In this case, the metal silicide layer 39 is formed by reacting silicon components of the lower electrode 26 by heat treatment of the dielectric layer formed on the metal silicide layer 39 by a subsequent process to form a reactant layer, thereby increasing the overall thickness of the dielectric layer. It is formed to prevent it.

In addition, a dielectric layer 40 such as a tantalum oxide film is formed on the lower electrode 36, and an oxygen gap and impurities of the dielectric layer 40 are removed by performing a heat treatment process on the dielectric layer 40.

Finally, the upper electrode 42 is formed on the dielectric layer 40.

Therefore, according to the method of the present invention, in the manufacture of a semiconductor device capacitor, the silicon component of the lower electrode is oxidized during the subsequent heat treatment of the tantalum oxide dielectric layer to form a reactant layer, thereby preventing the entire dielectric layer from becoming thick and reducing capacitance. The advantage is that you can.

In addition, according to the method of the present invention, the ratio of the minimum capacitance value to the maximum capacitance value can be improved.

Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.

Claims (5)

Forming a lower electrode with a silicon-containing material on a semiconductor substrate, forming a Hespherical Grain (HSG) on the lower electrode surface, and stacking a dielectric material on the lower electrode on which the HSG is formed to form a dielectric layer A method of manufacturing a capacitor of a semiconductor device, comprising the steps of: heat treating the dielectric layer; and forming an upper electrode on the dielectric layer. Forming a tungsten film on the entire surface of the semiconductor substrate after forming the HSG on the lower electrode surface; Heat-treating the tungsten film to denature the tungsten film around the lower electrode in contact with the lower electrode to a tungsten silicide film; And Wet etching the tungsten film such that the tungsten silicide film around the lower electrode remains; Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, And the dielectric material is a metal oxide such as tantalum oxide. The method of claim 1, Wherein the HSG is formed by the selective growth HSG method capacitor manufacturing method of the semiconductor device. The method of claim 1, After the dielectric layer is formed, the method further includes forming an intermediate layer of any one of titanium, tungsten, nitrides of titanium and tungsten, and silicon compounds on the dielectric layer. Way. The method of claim 1, The wet etching method of manufacturing a capacitor of the semiconductor device, characterized in that performed using sulfuric acid.

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