[go: up one dir, main page]

KR100254788B1 - Phase locked loop apparatus - Google Patents

Phase locked loop apparatus Download PDF

Info

Publication number
KR100254788B1
KR100254788B1 KR1019970032196A KR19970032196A KR100254788B1 KR 100254788 B1 KR100254788 B1 KR 100254788B1 KR 1019970032196 A KR1019970032196 A KR 1019970032196A KR 19970032196 A KR19970032196 A KR 19970032196A KR 100254788 B1 KR100254788 B1 KR 100254788B1
Authority
KR
South Korea
Prior art keywords
signal
charge
phase
voltage
charge pump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019970032196A
Other languages
Korean (ko)
Other versions
KR19990009708A (en
Inventor
김시현
Original Assignee
서평원
엘지정보통신주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 서평원, 엘지정보통신주식회사 filed Critical 서평원
Priority to KR1019970032196A priority Critical patent/KR100254788B1/en
Publication of KR19990009708A publication Critical patent/KR19990009708A/en
Application granted granted Critical
Publication of KR100254788B1 publication Critical patent/KR100254788B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE: A phase locked loop(PLL) apparatus is provided to reduce a time for synchronizing phases by controlling an outside current flowing from a charge pump. CONSTITUTION: A phase comparing unit(10) compares a phase of a modulated input signal and an output frequency of a voltage control oscillator and outputs a signal to the voltage control oscillator. A charge pump generates a current according to the signal from the phase comparing unit(10) and outputs a signal being applicable to it. A low filter receives the signal from the charge pump and performs a low pass filtering. The voltage control oscillator controls an output frequency by using a voltage outputted through the low filter. The charge pump comprises a charge and discharge speed controlling unit(30). The charge and discharge speed controlling unit(30) controls a charge and discharge speed by controlling an amount of a flowing current according to a selection of a predetermined unit among a charge and discharge circuit of N unit by using an external control signal.

Description

위상동기루프장치{PHASE LOCKED LOOP APPARATUS}Phase-locked loop device {PHASE LOCKED LOOP APPARATUS}

본 발명은 위상동기루프장치에 관한 것으로, 특히 전압제어발진기의 제어전압을 빠르게 안정화하기 위해 챠지펌프의 전류를 조절할 수 있도록 한 위상동기루프장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronous loop device, and more particularly, to a phase synchronous loop device capable of adjusting a current of a charge pump to quickly stabilize a control voltage of a voltage controlled oscillator.

도1은 종래 위상동기루프장치의 블록 구성도로서, 이에 도시된 바와같이 변조된 입력신호(fr)와 궤환한 신호(fv)의 위상을 비교하여 그에 해당되는 신호(UP/DOWN)를 출력하는 위상비교부(10)와; 상기 위상비교부(10)에서 출력된 신호(UP/DOWN)에 따라 전류를 발생하여 그에 해당되는 신호를 출력하는 챠지펌프(11)와; 상기 챠지펌프(11)의 신호를 입력받아 이를 로우패스 필터링하는 저역필터(12)와; 상기 저역필터(12)를 통해 출력된 신호에 의해 출력주파수가 제어되는 전압제어발진기(13)와; 상기 전압제어발진기(13)의 출력주파수를 입력받아 이를 N분주하여 상기 위상비교부로 궤환하는 분주기(14)로 구성된다.1 is a block diagram of a conventional phase-locked loop device. As shown in FIG. 1, a phase of a modulated input signal fr and a feedback signal fv is compared to output a corresponding signal UP / DOWN. A phase comparator 10; A charge pump 11 generating a current according to the signal UP / DOWN output from the phase comparator 10 and outputting a signal corresponding thereto; A low pass filter 12 which receives the signal from the charge pump 11 and performs low pass filtering on the signal; A voltage controlled oscillator 13 whose output frequency is controlled by a signal output through the low pass filter 12; It is composed of a divider 14 for receiving the output frequency of the voltage-controlled oscillator 13 and divides it by N and feedback to the phase comparator.

도2는 종래 챠지펌프(11)의 회로도로서, 이에 도시된 바와같이 위상비교부(10)로부터 출력된 신호에 의해 충방전을 제어하는 충방전제어부(20)와; 상기 충방전제어부(20)의 제어신호에 의해 충방전되는 충방전부(21)로 구성한다.2 is a circuit diagram of a conventional charge pump 11, and a charge and discharge control unit 20 for controlling charge and discharge by a signal output from the phase comparison unit 10 as shown therein; The charge / discharge unit 21 is charged and discharged by the control signal of the charge / discharge control unit 20.

상기 충방전제어부(20)는 소스에 전원전압(VDD)을 인가받은 피모스트랜지스터(P30)의 게이트에 상기 위상비교부(10)의 업신호(UP)가 인가되고, 소스가 접지(VSS)된 엔모스트랜지스터(N30)의 게이트에 다운신호(DOWN)가 인버터(IN30)를 통해 반전되어 인가되고, 상기 피모스트랜지스터(P30)의 드레인과 상기 엔모스트랜지스터(N30) 드레인의 공통 접속점에서 출력신호가 발생되도록 구성된다.The charge / discharge control unit 20 is applied with the up signal UP of the phase comparator 10 to the gate of the PMOS transistor P30 to which the power supply voltage VDD is applied to the source, and the source is grounded VSS. The down signal DOWN is inverted and applied to the gate of the enMOS transistor N30 through the inverter IN30, and is output at a common connection point between the drain of the PMOS transistor P30 and the drain of the NMOS transistor N30. The signal is configured to be generated.

상기 충방전부(21)는 상기 충방전제어부(20)의 출력신호를 일측에 인가받은 저항(R1)에 접지(VSS)된 콘덴서(C1)를 일측에 인가받은 저항(R2)이 병렬로 접속되어 구성된다.The charge / discharge unit 21 is connected in parallel with a resistor R2 applied to one side of a capacitor (C1) grounded (VSS) to a resistor (R1) applied to the output signal of the charge and discharge control unit 20 on one side. It is composed.

이와같이 구성된 종래 장치의 동작을 설명한다.The operation of the conventional apparatus configured as described above will be described.

변조된 입력신호(fr)와 분주기(14)에 의해 N분주된 전압제어발진기(13)의 출력신호는 위상비교부(10)에서 위상이 비교되어 그에 해당되는 신호를 출력한다.The output signal of the voltage controlled oscillator 13 divided by the modulated input signal fr and the divider 14 is compared in phase with the phase comparator 10 and outputs a signal corresponding thereto.

먼저,입력신호(fr)가 전압제어발진기(13)의 출력신호(fv)보다 위상이 빠를 경우에, 상기 위상비교부(10)는 상기 두 신호(fr),(fv)를 입력받아 위상을 비교하여 저전위인 업신호(UP)와 고전위인 다운신호(DOWN)를 출력한다.First, when the input signal fr is out of phase with the output signal fv of the voltage controlled oscillator 13, the phase comparator 10 receives the two signals fr and fv to phase out. In comparison, a low potential up signal UP and a high potential down signal DOWN are output.

이때, 상기 위상비교부(10)로부터 출력된 업신호(UP)가 저전위로 다운신호(DOWN)는 고전위로 챠지펌프(11)에 입력되면 충방전제어부(20)의 피모스트랜지스터(P30)는 턴-온되고, 엔모스트랜지스터(N30)는 턴-오프되어 출력단은 전원전압(VDD)이 상기 피모스트랜지스터(P30)를 통해 인가되므로 고전위상태가 된다.At this time, when the up signal UP output from the phase comparator 10 is input to the charge pump 11 at a low potential at a low potential, the PMOS transistor P30 of the charge / discharge control unit 20 is It is turned on and the NMOS transistor N30 is turned off so that the output terminal is in a high potential state because the power supply voltage VDD is applied through the PMOS transistor P30.

이에따라, 상기 고전위는 충방전부(21)의 커패시터(C1)를 충전시켜 전압제어발진기(13)의 제어전압을 증가시켜 상기 전압제어발진기(13)의 출력주파수를 빠르게 한다.Accordingly, the high potential charges the capacitor C1 of the charge / discharge unit 21 to increase the control voltage of the voltage controlled oscillator 13 to speed up the output frequency of the voltage controlled oscillator 13.

반대로, 입력신호(fr)가 전압제어발진기(13)의 출력신호(fv)보다 위상이 늦을 경우에, 상기 위상비교부(10)는 상기 두 신호(fr),(fv)를 입력받아 위상을 비교하여 고전위인 업신호(UP)와 저전위인 다운신호(DOWN)를 출력한다.On the contrary, when the input signal fr is later in phase than the output signal fv of the voltage controlled oscillator 13, the phase comparator 10 receives the two signals fr and fv to change the phase. In comparison, a high potential up signal UP and a low potential down signal DOWN are output.

이때, 상기 위상비교부(10)로부터 출력된 업신호(UP)가 고전위로 다운신호(DOWN)는 저전위로 챠지펌프(11)에 입력되면 충방전제어부(20)의 피모스트랜지스터(P30)는 턴-오프되고, 엔모스트랜지스터(N30)는 턴-온되어 출력단은 접지전압(VSS)이 상기 엔모스트랜지스터(N30)를 통해 인가되므로 저전위상태가 된다.At this time, when the up signal UP output from the phase comparator 10 is input to the charge pump 11 at a high potential and the down signal DOWN is low, the PMOS transistor P30 of the charge / discharge control unit 20 is The NMOS transistor N30 is turned on and the output terminal is turned off because the ground voltage VSS is applied through the NMOS transistor N30.

이에따라, 상기 저전위는 충방전부(21)의 커패시터(C1)를 방전시켜 전압제어발진기(13)의 제어전압을 감소시키므로 상기 전압제어발진기(13)의 출력주파수는 빠르게 된다.Accordingly, since the low potential discharges the capacitor C1 of the charge / discharge unit 21 to reduce the control voltage of the voltage controlled oscillator 13, the output frequency of the voltage controlled oscillator 13 is increased.

그러나, 상기와 같이 동작하는 종래 장치는 입력신호가 저주파수에서 고주파수로 변화할 경우 충방전부의 커패시터에 충전되는 전류의 양이 저주파수일 때와 거의 동일하므로 상기 커패시터를 충전시키는 시간이 오래 걸리기 때문에 전압제어발진기의 제어전압이 입력신호와 동기되는 데 시간이 많이 걸리는 문제점이 있었다.However, in the conventional apparatus operating as described above, when the input signal changes from low frequency to high frequency, the amount of current charged in the capacitor of the charging / discharging part is almost the same as that of the low frequency. There was a problem that it takes a long time for the control voltage of the oscillator to be synchronized with the input signal.

따라서, 본 발명은 위상동기루프를 구성하는 위상비교기의 챠지펌프의 전류를 조절하여 저주파수에서 고주파수로 급격히 입력이 바뀔 때 챠지펌프의 전류를 증가시켜서 전압제어발진기의 제어전압이 빠르게 안정화하게 함으로써 입력신호와 동기되는 데 시간을 줄이도록 한 위상동기루프장치를 제공함에 그 목적이 있다.Accordingly, the present invention adjusts the current of the charge pump of the phase comparator constituting the phase synchronization loop to increase the current of the charge pump when the input is rapidly changed from low frequency to high frequency so that the control voltage of the voltage controlled oscillator can be stabilized quickly. It is an object of the present invention to provide a phase-locked loop device for reducing the time to be synchronized with the.

도1은 종래 위상동기루프장치의 블록 구성도.1 is a block diagram of a conventional phase synchronous loop device.

도2는 도1에 있어서, 챠지펌프의 회로도.2 is a circuit diagram of a charge pump in FIG.

도3은 본 발명 위상동기루프장치에 있어서의 챠지펌프 회로도.Fig. 3 is a charge pump circuit diagram of the phase synchronous loop device of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

20:충방전제어부 30:충방전속도제어부20: charge and discharge control unit 30: charge and discharge speed control unit

21:충방전부 1~N:충방전회로21: charge and discharge part 1 to N: charge and discharge circuit

상기와 같은 목적을 달성하기 위한 본 발명은 변조된 입력신호와 전압제어발진기의 출력주파수의 위상을 비교하여 그에 해당되는 신호를 출력하는 위상비교부와; 상기 위상비교부의 신호에 따라 전류를 발생하여 그에 해당되는 신호를 출력하는 챠지펌프와; 상기 챠지펌프로부터 신호를 입력받아 이를 로우패스 필터링하는 저역필터와; 상기 저역필터를 통해 출력된 전압에 의해 출력주파수가 제어되는 전압제어발진기로 구성된 위상동기루프장치에 있어서, 상기 챠지펌프는 외부 콘트롤신호에 의해 N개의 충방전회로(1~N)중 소정개를 선택하고 그에 따라 흐르는 전류의 양을 조정하여 충방전속도를 제어하는 충방전속도제어부를 더 포함하여 구성한 것을 특징으로 한다.The present invention for achieving the above object is a phase comparison unit for comparing the phase of the modulated input signal and the output frequency of the voltage controlled oscillator and outputs a signal corresponding thereto; A charge pump generating a current according to the signal of the phase comparing unit and outputting a signal corresponding thereto; A low pass filter receiving a signal from the charge pump and low pass filtering the signal; In a phase synchronous loop device comprising a voltage controlled oscillator whose output frequency is controlled by a voltage output through the low pass filter, the charge pump is configured to select a predetermined number of N charge / discharge circuits 1 to N by an external control signal. Selecting and adjusting the amount of current flowing accordingly characterized in that it further comprises a charge-discharge rate control unit for controlling the charge-discharge rate.

이하, 본 발명에 의한 위상동기루우프장치에 대한 작용 및 효과를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the operation and effects of the phase-locked loop device according to the present invention will be described in detail with reference to the accompanying drawings.

본 발명의 구성은 종래 구성도인 도1과 동일하며, 다만 챠지펌프의 충전속도를 빠르게 하도록 구성한 것이 다르다.The configuration of the present invention is the same as that of Fig. 1, which is a conventional configuration, except that the charging pump is configured to increase the charging speed.

도3은 본 발명 위상동기루프장치의 챠지펌프 회로도로서, 이에 도시한 바와같이 위상비교부(10)로부터 출력된 신호에 의해 충방전을 제어하는 충방전제어부(20)와; 외부 콘트롤신호(CNT)에 의해 전류의 양을 조정하여 충방전속도를 제어하는 충방전속도제어부(30)와; 상기 충방전제어부(20)와 충방전속도제어부(30)의 제어신호에 의해 충방전되는 충방전부(21)로 구성한다.3 is a charge pump circuit diagram of the phase-locked loop device according to the present invention, and a charge / discharge control unit 20 for controlling charge / discharge by a signal output from the phase comparator 10, as shown therein; A charge / discharge rate control unit 30 controlling the charge / discharge rate by adjusting an amount of current by an external control signal CNT; The charging and discharging control unit 20 and the charging and discharging speed control unit 30 is composed of a charge and discharge unit 21 which is charged and discharged by the control signal.

상기 충방전속도제어부(30)는 외부 콘트롤신호(CNT)에 의해 전류의 양을 조정하는 N개의 충방전회로(1~N)로 구성하며, 상기 충방전회로(1~N)는 각기 위상비교부(10)로부터 출력된 업신호(UP)에 의해 전원전압(VDD)을 인가하는 피모스트랜지스터(P1)와; 위상비교부(10)로부터 출력된 다운신호(DOWN)에 의해 접지전압(VSS)을 인가하는 엔모스트랜지스터(N1)와; 외부 콘트롤신호(CNT)를 인버터(IN1)를 통해 반전하여 그 신호를 반전단자(-)에 인가받고 상기 외부 콘트롤신호(CNT)를 두 개의 인버터(IN2),(IN3)를 통해 순차 지연시켜 비반전단자(+)에 인가받아 상기 전원전압(VDD)을 순차적으로 상기 접지전압(VSS)측으로 전송하는 제1,제2 전송게이트(G1),(G2)로 구성하며, 이와같이 구성된 본 발명의 동작을 설명하면 다음과 같다.The charge / discharge rate control unit 30 is composed of N charge / discharge circuits 1 to N that adjust the amount of current by an external control signal CNT, and the charge / discharge circuits 1 to N are respectively compared in phase. A PMOS transistor P1 for applying the power supply voltage VDD by the up signal UP output from the unit 10; An NMOS transistor N1 for applying the ground voltage VSS by the down signal DOWN output from the phase comparator 10; The external control signal CNT is inverted through the inverter IN1, the signal is applied to the inverting terminal (-), and the external control signal CNT is sequentially delayed through the two inverters IN2 and IN3. The first and second transfer gates G1 and G2 are applied to the inverting terminal + to sequentially transfer the power supply voltage VDD to the ground voltage VSS. This is as follows.

먼저, 기본적인 동작은 종래와 동일하다.First, the basic operation is the same as in the prior art.

즉, 입력신호(fr)가 전압제어발진기(13)의 출력신호보다 빠를 경우에 위상비교부(10)는 상기 두 신호(fr),(fv)를 입력받아 위상을 비교하여 저전위인 업신호(UP)와 고전위인 다운신호(DOWN)를 출력한다.That is, when the input signal fr is faster than the output signal of the voltage controlled oscillator 13, the phase comparator 10 receives the two signals fr and fv and compares the phases so as to compare the phase with a low potential up signal ( UP) and a high potential down signal (DOWN).

이에따라, 챠지펌프(11)의 충방전제어부(20)는 상기 저전위인 업신호(UP)에 의해 피모스트랜지터(P30)를 턴온시키고 상기 고전위인 다운신호(DOWN)가 인버터(IN30)를 통해 반전된 신호에 의해 엔모스트랜지스터(N30)는 턴오프되어 상기 피모스트랜지스터(P30)를 통해 전원전압(VDD)이 출력된다.Accordingly, the charge / discharge control unit 20 of the charge pump 11 turns on the PMOS transistor P30 by the low signal up signal UP, and the high potential down signal DOWN is transmitted through the inverter IN30. The NMOS transistor N30 is turned off by the inverted signal, and a power supply voltage VDD is output through the PMOS transistor P30.

이때, 충방전부(21)의 커패시터(C1)의 충전전압이 증가되어 전압제어발진기(13)는 발진주파수(fv)를 빠르게 하여 입력신호(fr)와 동기시킨다.At this time, the charging voltage of the capacitor C1 of the charging and discharging unit 21 is increased so that the voltage controlled oscillator 13 speeds up the oscillation frequency fv to synchronize with the input signal fr.

반대로, 입력신호(fr)의 위상이 전압제어발진기(13)에서 피이드백된 신호(fv)의 위상보다 작을 경우에 위상비교부(10)는 상기 두신호(fr),(fv)를 입력받아 위상을 비교하여 고전위인 업신호(UP)와 저전위인 다운신호(DOWN)를 출력한다.On the contrary, when the phase of the input signal fr is smaller than the phase of the signal fv fed back from the voltage controlled oscillator 13, the phase comparator 10 receives the two signals fr and fv. The phase is compared to output a high potential up signal UP and a low potential down signal DOWN.

이에따라, 챠지펌프(11)의 충방전제어부(20)는 상기 고전위인 업신호(UP)를 피모스트랜지스터(P30)의 게이트에 입력받아 턴오프되고 상기 저전위인 다운신호(DOWN)를 인버터(IN30)를 통해 반전하여 그 신호를 게이트에 인가받는 엔모스트랜지스터(N30)는 턴온되어 상기 충방전제어부(20)의 출력단은 접지(VSS)되어 저전위상태가 된다.Accordingly, the charge / discharge control unit 20 of the charge pump 11 receives the high signal UP signal UP to the gate of the PMOS transistor P30 and turns off the low signal DOWN signal to the inverter IN30. The NMOS transistor N30, which is inverted through the signal and is applied to the gate, is turned on so that the output terminal of the charge / discharge control unit 20 is grounded (VSS) to a low potential state.

이때, 충방전부(21)의 커패시터(C1)에 충전된 전압은 상기 충방전제어부(21)의 출력단을 통하여 접지(VSS)로 흐르므로 상기 커패시터(C1)에 충전된 전압은 감소된다.In this case, since the voltage charged in the capacitor C1 of the charge / discharge unit 21 flows to the ground VSS through the output terminal of the charge / discharge control unit 21, the voltage charged in the capacitor C1 is reduced.

이에따라, 전압제어발진기(13)의 제어전압이 감소되므로 상기 전압제어발진기(13)에서 출력되는 발진주파수(fv)는 느려져서 입력신호(fr)와 위상이 동기된다.Accordingly, since the control voltage of the voltage controlled oscillator 13 is reduced, the oscillation frequency fv output from the voltage controlled oscillator 13 is slowed to synchronize the phase with the input signal fr.

만약, 입력신호(fr)가 낮은 주파수에서 높은 주파수로 변화하면 마이크로컴퓨터에서 이를 판단하여 적절한 외부 콘트롤신호(CNT)를 충방전속도제어부(30)에 입력하여 전류의 양을 증가시켜 충방전부(21)의 커패시터(C1)를 빠르게 충전한다.If the input signal fr changes from a low frequency to a high frequency, the microcomputer determines this and inputs an appropriate external control signal CNT to the charge / discharge rate control unit 30 to increase the amount of current to charge / discharge unit 21. Fast charge capacitor C1).

이에따라, 상기 충방전부(21)의 커패시터(C1)에 빠르게 충전된 전압이 전압제어발진기(13)의 제어전압을 증가시켜 상기 전압제어발진기(13)의 발진주파수(fv)와 상기 높은 주파수로 변화된 입력신호(fr)와 빠르게 위상이 동기된다.Accordingly, the voltage rapidly charged in the capacitor C1 of the charge / discharge unit 21 increases the control voltage of the voltage controlled oscillator 13 so that the oscillation frequency fv and the high frequency of the voltage controlled oscillator 13 are changed. The phase is quickly synchronized with the input signal fr.

즉, 마이크로컴퓨터가 입력신호(fr)의 변화를 체크하여 적절한 외부 콘트롤신호(CNT)로 충방전속도제어부(30)를 제어하여 전류를 증가시킴으로써 상기 충방전부(21)의 커패시터(C1)를 빠르게 충전한다.That is, the microcomputer checks the change in the input signal fr and controls the charge / discharge rate control unit 30 with an appropriate external control signal CNT to increase the current to quickly increase the capacitor C1 of the charge / discharge unit 21. To charge.

이에따라, 전압제어발진기(13)의 제어전압이 빠르게 증가하므로 발진주파수(fv)의 위상과 낮은 주파수에서 높은 주파수로 변화하는 입력신호(fr)의 위상이 빠르게 동기된다.Accordingly, since the control voltage of the voltage controlled oscillator 13 increases rapidly, the phase of the oscillation frequency fv and the phase of the input signal fr changing from a low frequency to a high frequency are quickly synchronized.

상기와 같이 동작하는 본 발명은 챠지펌프에 흐르는 전류를 외부에서 조절이 가능하게 하여 입력주파수가 급격히 높은 주파수로 바뀔 경우 챠지펌프의 전류를 많이 흐르게 하여 전압제어발진기의 콘트롤전압이 안정화되는 시간을 줄여 위상동기에 걸리는 시간을 줄일 수 있는 효과가 있다.The present invention operating as described above is able to adjust the current flowing in the charge pump from the outside to reduce the time for the control voltage of the voltage controlled oscillator to stabilize by flowing a lot of current of the charge pump when the input frequency is changed to a high frequency rapidly The time taken for phase synchronization can be reduced.

Claims (2)

변조된 입력신호와 전압제어발진기의 출력주파수의 위상을 비교하여 그에 해당되는 신호를 출력하는 위상비교부와; 상기 위상비교부의 신호에 따라 전류를 발생하여 그에 해당되는 신호를 출력하는 챠지펌프와; 상기 챠지펌프로부터 신호를 입력받아 이를 로우패스 필터링하는 저역필터와; 상기 저역필터를 통해 출력된 전압에 의해 출력주파수가 제어되는 전압제어발진기로 구성된 위상동기루프장치에 있어서, 상기 챠지펌프는 외부 콘트롤신호에 의해 N개의 충방전회로(1~N)중 소정개를 선택하고 그에 따라 흐르는 전류의 양을 조정하여 충방전속도를 제어하는 충방전속도제어부를 더 포함하여 구성한 것을 특징으로 하는 위상동기루프장치.A phase comparison unit for comparing a phase of a modulated input signal with an output frequency of the voltage controlled oscillator and outputting a signal corresponding thereto; A charge pump generating a current according to the signal of the phase comparing unit and outputting a signal corresponding thereto; A low pass filter receiving a signal from the charge pump and low pass filtering the signal; In a phase synchronous loop device comprising a voltage controlled oscillator whose output frequency is controlled by a voltage output through the low pass filter, the charge pump is configured to select a predetermined number of N charge / discharge circuits 1 to N by an external control signal. And a charging / discharging speed control unit for controlling the charging / discharging speed by selecting and adjusting the amount of current flowing accordingly. 제1 항에 있어서, 충방전회로(1~N)는 각기 위상비교부로부터 출력된 업신호에 의해 전원전압을 인가하는 피모스트랜지스터와; 위상비교부로부터 출력된 다운신호에 의해 접지전압을 인가하는 엔모스트랜지스터와; 외부 콘트롤신호를 제1 인버터를 통해 반전하여 그 신호를 반전단자에 인가받고 아울러 상기 외부콘트롤신호를 제2,제3 인버터를 통해 순차 지연시켜 비반전단자에 인가받아 상기 전원전압을 순착적으로 접지전압측으로 전송하는 제1,제2 전송게이트로 구성한 것을 특징으로 위상동기루프장치.2. The apparatus of claim 1, wherein the charge / discharge circuits 1 to N each include a PMOS transistor for applying a power supply voltage by an up signal output from a phase comparator; An MOS transistor applying a ground voltage by a down signal output from the phase comparator; The external control signal is inverted through the first inverter and the signal is applied to the inverting terminal, and the external control signal is sequentially delayed through the second and third inverters to be applied to the non-inverting terminal, thereby grounding the power supply voltage. A phase locked loop device comprising: first and second transfer gates for transmitting to a voltage side.
KR1019970032196A 1997-07-11 1997-07-11 Phase locked loop apparatus Expired - Fee Related KR100254788B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970032196A KR100254788B1 (en) 1997-07-11 1997-07-11 Phase locked loop apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970032196A KR100254788B1 (en) 1997-07-11 1997-07-11 Phase locked loop apparatus

Publications (2)

Publication Number Publication Date
KR19990009708A KR19990009708A (en) 1999-02-05
KR100254788B1 true KR100254788B1 (en) 2000-05-01

Family

ID=19514152

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970032196A Expired - Fee Related KR100254788B1 (en) 1997-07-11 1997-07-11 Phase locked loop apparatus

Country Status (1)

Country Link
KR (1) KR100254788B1 (en)

Also Published As

Publication number Publication date
KR19990009708A (en) 1999-02-05

Similar Documents

Publication Publication Date Title
US5740213A (en) Differential charge pump based phase locked loop or delay locked loop
EP0777333B1 (en) Power saving PLL circuit
KR100372486B1 (en) Horizontal oscillation circuit
US5629651A (en) Phase lock loop having a reduced synchronization transfer period
US5923715A (en) Digital phase-locked loop circuit
US20010015667A1 (en) Clock signal generating circuit using variable delay circuit
US20040080342A1 (en) Method and apparatus for stable phase-locked looping
KR20070121951A (en) Voltage controlled oscillator, phase locked loop circuit having same, and control method of phase locked loop circuit
EP1292032A1 (en) Synchronous device
US5898336A (en) Charging pump circuit and a phase-locked loop circuit using the same
JP7257711B2 (en) Fast-locking phase-locked loop circuit for cycle-slip avoidance
US5081428A (en) Voltage controlled oscillator having 50% duty cycle clock
US7312666B2 (en) PLL circuit configured to distribute its loop control signal to CDR circuits
JP3098471B2 (en) Semiconductor device for low power supply
CN210899136U (en) Phase-locked loop circuit, chip, circuit board and electronic equipment
US5081429A (en) Voltage controlled oscillator with controlled load
US20050083138A1 (en) PLL circuit
KR100711103B1 (en) Adaptive three-state phase frequency detector and detection method and phase locked loop using the same
JP3561035B2 (en) Synchronous clock generation circuit
US6614318B1 (en) Voltage controlled oscillator with jitter correction
US11411566B2 (en) Charge pump
KR20000018820A (en) Phase locked loop circuit for reducing lock-in-time
KR20050007821A (en) Phase locked loop circuit having adaptive variable bandwidth
KR100254788B1 (en) Phase locked loop apparatus
KR19990023417A (en) Phase locked loop circuit

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20070130

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20080208

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20080208

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000