KR100237307B1 - Dual speed decoding apparatus - Google Patents

Abstract

The present invention relates to a 2x-speed reproduction apparatus for an MPEG video signal decoder, which decodes a part of an interpolation frame for reducing a correlation between frames through bidirectional prediction in one pixel group during video signal reproduction, Speed playback of a video signal, a video signal, a digital video disc, and the like.

To this end, the present invention determines the number and order of effective B pixels to be decoded in a single pixel group by using an arbitrary calculation value related to the number of all pixels existing in one pixel group and the number of B pixels, Speed high-speed reproduction processor for reproducing and restoring a part of the B pixel through the I-pixel and the P-pixel to perform full high-speed reproduction together with the I pixel and the P pixel.

Description

Speed playback apparatus of an MPEG (MPEG) video signal decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double-speed playback apparatus for a video signal decoder used in a Moving Picture Expert Group (hereinafter referred to as MPEG) MPEG1 or MPEG2 video Main Profile @ ML (Main Level) More particularly, the present invention can be applied to a video CD, a digital video disc, or the like by decoding a part of an interpolation frame which reduces the correlation between frames through bidirectional prediction in one pixel group during video signal reproduction, Speed playback apparatus of an MPEG video signal decoder.

Currently, widely used video information storage or transmission system is an analog system, and when the analog system is converted into a digital system, excellent performance can be obtained in image quality, reliability and easiness of data processing, and studies are underway .

The digital processing technology of such video information is widely applied to high-definition TV (HD-TV), digital television (D-TVR), video compact disc (VIDEO-CD), digital video disc (DVD), video on demand And it is expected that the application range will be further expanded in the future.

However, when the video data is digitally processed, the amount of information is much larger than that of the analog method. Therefore, in order to use the transmission and storage media effectively, it is necessary to reduce the amount of video information through the encoder. A decoder is needed to recover the original signal.

Currently, the international standard for encoding / decoding digital motion picture signals is standardized through MPEG1 of International Standard Organization (ISO), and standardization of MPEG2 is being prepared especially for a high-definition moving image coding / decoding apparatus.

A typical compression technique of a video signal can be effectively performed by eliminating redundant information using a temporal and spatial correlation of video information and variable-length encoding the same, and a representative technique thereof is a motion compensation type discrete cosine transform (Motion Compensated DCT Transform) as an entropy coding method in MPEG2, which is in the process of standardization of moving pictures.

The MPEG2 moving picture encoder includes a frame memory 1, a frame / field memory 2, a subtracter 3 and a DCT 4 (4) for obtaining a bit stream encoded at an output terminal with respect to a video input signal as shown in the figure. A quantizer 5, a variable length code (VLC), a mux 13 and a buffer 14. The demultiplexer 6 demultiplexes the output of the quantizer 6 and an inverse discrete cosine transformer A motion estimator 10 which is combined with the adaptive predictor 9 and a feedback line consisting of an adder 15 and an adaptive predictor 9 and a quantizer 5 And an activity calculator 11 and a ratio calculator 12 which are combined with each other.

As shown in FIG. 2, the frame structure of the MPEG1 or MPEG2 coding scheme includes an Intra frame (hereinafter referred to as an I frame) for reducing the spatial redundancy information of the video information and a predicted frame for reducing the correlation between the frames through the forward prediction (hereinafter referred to as a B pixel) for reducing a correlation between frames through a bidirectional prediction (hereinafter referred to as a P pixel) and bidirectional prediction.

The decoding of the video signal having the frame structure of MPEG1 or MPEG2 MP @ ML as shown in FIG. 2 is performed through the following process.

That is, the P pixel can be completely restored by the motion compensation only if there is the decoded I pixel, and the B pixel can be decoded through the motion restoration only when there is the decoded I pixel and the P pixel used for the prediction of the B pixel in the encoding process Do.

Therefore, the high speed reproduction of the video signal having the frame structure of FIG. 2 is generally performed by decoding only the I pixel and the P pixel, so that the minimum high speed reproduction speed becomes 3x speed, which is a limitation in performing high speed 2x speed reproduction.

Accordingly, the present invention has been made to solve the above problems, and it is an object of the present invention to provide a decoding method and a decoding method for decoding a part of an interpolation frame for reducing a correlation between frames through bidirectional prediction in one pixel group, Speed reproduction of an MPEG video signal decoder capable of realizing high-speed reproduction.

In order to achieve the above object, the present invention determines the number and order of valid B pixels to be decoded in a single pixel group by using an arbitrary calculation value relating to the number of all pixels and the number of B pixels existing in one pixel group And reproduces and restores a portion of the B pixel through the number and the order thereof, thereby performing a full high-speed reproduction at 2x speed together with the I pixel and the P pixel, thereby providing a 2x speed reproduction apparatus for an MPEG video signal decoder do.

1 is a block diagram of a video signal encoder showing a moving picture coding method of MPEG2;

2 is a view showing a structure of a video frame in the MPEG2 moving picture coding method.

3 is a block diagram of a MPEG2 video signal decoder including a 2x playback apparatus according to the present invention;

FIG. 4 is a diagram illustrating a video frame structure showing a hierarchical structure of moving picture data presented by MP @ ML of MPEG2; FIG.

5 is a circuit diagram showing an embodiment of effective data detection and transmission means in a 2x playback apparatus according to the present invention.

6 is a diagram illustrating a video frame structure for explaining pixels restored upon 2x speed reproduction according to the present invention;

DESCRIPTION OF REFERENCE NUMERALS

24: 2x fast reproduction processor 41: Pixel type code detector

42: logical end gate 43, 47: inverter

44: latch 45: B pixel counter

46: comparator 48: logic ORGate

49: data delay GOP: pixel group

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the configuration of a double-speed playback apparatus of an MPEG video signal decoder according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram of a MPEG2 video signal decoder including a 2x-speed high-speed playback apparatus according to the present invention. As shown in the figure, the system controller 20 performs playback The MPEG2 system layer decoder 23 is provided with a processor 21, an input buffer 22 and an MPEG2 system layer decoder 23. The MPEG2 system layer decoder 23 performs a high- Speed fast reproduction processor 24 for performing a video compression process on the video signal and a video buffer 25 and a video decoder 26 and a video digital-analog converter 27 and an audio buffer 28 for each video audio signal, (29) and an audio digital / analog converter (30).

Speed reproduction processor 24 performs a high-speed reproduction command received from the system controller 20 to generate a single pixel group < RTI ID = 0.0 > And valid data detecting and transmitting means for detecting and transmitting effective data for reproducing and restoring a part of the B pixels through the number and order of the effective B data.

At this time, the 2x fast reproduction processor 24 can calculate the number of B pixels (No_B_Decpic) to be decoded in a single pixel group differently according to the number of all pixels (No_Totalpic) existing in a single pixel group, The number of B pixels to be decoded in a single pixel group is determined as No_B_Decpic = 0.5 × (No_Totalpic - No_Bpic), and when the counted number of pixel groups is "0" No_B_Decpic = 0.5 X (No_Totalpic - No_Bpic + 1), and in other cases, No_B Decpic = 0.5 X (No_Totalpic - No_Bpic - 1) in the case of GOP_Count = 0 .

The order (Order_B_Decpic) of the B pixels to be decoded is set to Order_B_Decpic = 2K + 1 (0? K <No_B_Decpic).

FIG. 4 is a video frame structure diagram showing a hierarchical structure of moving picture data presented in MP @ ML of MPEG2.

As shown in the figure, the highest layer of the moving picture data is a sequence layer and the next higher layer is a group of picture groups (1'ST GOP - N'TH GOP) layer (1'ST SEQUENCE) hierarchy. One pixel group is composed of I pixels for performing intra-frame encoding, P pixels for performing forward predictive encoding, and B pixels for bidirectional predictive encoding Pixel, and the period of one pixel group (GOP) is the period of the I pixel.

5 is a circuit diagram showing one embodiment of effective data detecting and transmitting means in a double speed reproduction apparatus according to the present invention. The circuit shown in FIG. 5 includes a pixel type code for detecting each pixel code (i_type, p_type, b_type) A latch 44 which receives the B pixel code b_type of the pixel type code detector as an input signal and maintains a B pixel input state; and a latch 44 And a logic end gate 42 and an inverter 43 for supplying a clock signal ck to the clock signal ck.

A B pixel counter 45 for counting the number of B pixels in a single pixel group using the B pixel code b_type and the I pixel code i_type of the pixel type code detector 41, A comparator 46 for comparing the count output b_cnt with an arbitrary operation value to detect valid data; and a comparator 46 for b_validating the output cmp-out of the comparator and synthesizing the output with the output of the latch to generate valid data v_act, And an inverter 47 and a logic or gate 48 for transferring data.

And a data delayer 49 for delaying the reproduction data for an arbitrary time period and outputting the encoded data.

FIG. 6 is a diagram illustrating a video frame structure for explaining pixels restored upon 2 × -speed fast reproduction according to the present invention. FIG. 6 shows a result of detecting and restoring only valid B pixels in a single pixel group (1 GOP).

The operation of the present invention as described above will be described as follows.

The main operation of the present invention realizes high-speed reproduction at a minimum 2-times speed by only partially decoding B pixels constituting a pixel group (GOP). Generally, in order to realize high-speed reproduction from the MPEG2 pixel structure of FIG. 4, Is possible.

That is, the 2x speed reproduction processor 24 is realized through the following process.

The number (No_Totalpic) of all the pixels in the pixel group (GOP) is checked to determine No_B_Decpic = 0.5 x (No_Totalpic - No_Bpic) if the number of B pixels to be decoded in the pixel group (GOP) (No_B_Decpic = 0.5 × (No_Totalpic - No_Bpic + 1)) is determined if the value of the pixel group (GOP_Count) is "0" - 1).

Here, No_Totalpic is the total number of pixels constituting the pixel group (GOP), No_Bpic is the number of B pixels in the pixel group (GOP), and GOP count is a value obtained by counting the number of pixel groups (GOP) to be.

Therefore, in the 2x-speed fast reproduction processor, the number of B pixels (No_B_Decpic) to be decoded in the pixel group (GOP) is determined by the above-described calculation method during actual 2x speed reproduction.

Further, in the 2x-speed fast reproduction processor, the order of B pixels to be decoded (Order_B_Decpic) is determined as follows, whereby continuous B pixels are not reproduced, thereby maximizing the visual effect of fast reproduction.

That is, Order_B_Decpic = 2K + 1 (where 0 < k &lt; No_B_Decpic)

In accordance with the high-speed reproduction command of the system controller 20, the pixel-type code detector 41 extracts each pixel code (i_type, p_type, b_type A combination signal that has passed through the logical end gate 42 and the inverter 43 supplies a clock signal to the latch 44 while one pixel group is being held so that the latch 44 outputs the B pixel code (b_type) is input, the signal is maintained in a single pixel group for a certain period of time and output.

At the same time, the B pixel counter 45 counts the B pixel code (b_type) on the basis of the I pixel code (i_type) detected by the pixel type code detector 41 to calculate the number of B pixels in one pixel group And the comparator 46 compares the count value with the number of B pixels (No_B_Decpic) to be decoded in the single pixel group (GOP) already calculated and the order of B pixels to be decoded (Order_B_Decpic) By outputting through the inverter 47 and the logic or gate 48, it is possible to reproduce and restore only a part of the B pixel by the No_B_Decpic and the Order_B_Decpic as well as the I and P pixels at the time of high speed reproduction, thereby realizing the full high speed reproduction at double speed.

In other words, as shown in FIG. 6, the number of pixels restored at the time of double-speed reproduction is 12 frames in one GOP in FIG. 4. In this case, one I pixel, three P pixels and two B pixels are reproduced, Speed processing can be performed at double speed.

According to the double-speed playback apparatus of the MPEG video signal decoder according to the present invention as described above, the speed of the minimum fast playback of the MPEG decoder can be realized at double speed, and the order of the B pixels restored at the time of high- It is useful to obtain a visual effect at the time of high-speed reproduction by arranging according to the state of the buffer.

Claims (3)

An input buffer and an MPEG2 system layer decoder for decoding the reproduced data according to a data control signal of the system controller, and a decoder for decoding the video signal output from the MPEG2 system layer decoder according to a high- A video decoder and a video digital-to-analog converter for converting and outputting a video signal output from the 2x-speed high-speed reproduction processor into an analog video signal; An MPEG video signal decoder having an audio buffer, an audio decoder, and an audio digital-to-analog converter for converting and outputting an audio signal output from a decoder to an analog audio signal, Exists in the pixel group Determines the number and order of effective B pixels to be decoded in a single pixel group with the calculation values related to the number of all pixels and the number of B pixels, and reproduces B pixels selected by the determined number and order to obtain I pixels and P And outputs the video signal along with the pixel. The apparatus of claim 1, wherein the 2x speed reproduction processor comprises: The number of B pixels to be decoded in a single pixel group is set to No_B_Dec _pic = 0.5 X (No_Total _pic - No_B _pic ) when the number of all pixels existing in the pixel group is an even number, and a value Is set to No_B_Dec _pic = 0.5 X (No_Total _pic - No_B _pic + 1) in the case of "0", and No_B_Dec _pic = 0.5 X (No_Total _pic - No_B _pic - 1) And the order of the B pixels (Order_B_Dec _pic ) is set to Order_B_Dec _pic = 2K + 1 (0? K <No_B_Dec _pic ). Here, No_B_Dec _PIC is the number of B pixels to be decoded in the pixel group (GOP), No_Total _PIC is the total number of pixels constituting the pixel group (GOP), and No_B _PIC is the number of B pixels in the pixel group . The apparatus of claim 1, wherein the 2x speed reproduction processor comprises: A pixel type code detector for detecting each pixel code (i_type, p_type, b_type) in accordance with the pixel type from the reproduction data; A latch for storing the B pixel code detected by the pixel type code detector to maintain the B pixel input state; A logic AND gate and an inverter for supplying a clock signal to the latch while one pixel group is held; A B pixel counter for counting the number of B pixels in a single pixel group using the B pixel code and the I pixel code of the pixel type code detector; A comparator for comparing the count output of the B pixel counter with a predetermined operation value to detect valid data; An inverter for inverting an output of the comparator; And a validated data detecting and transmitting means comprising a logical OR gate for logically summing the outputs of the inverter and the latch to transmit valid data.