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KR100237020B1 - Method for forming a metal layer of a semiconductor - Google Patents

Method for forming a metal layer of a semiconductor Download PDF

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Publication number
KR100237020B1
KR100237020B1 KR1019960048292A KR19960048292A KR100237020B1 KR 100237020 B1 KR100237020 B1 KR 100237020B1 KR 1019960048292 A KR1019960048292 A KR 1019960048292A KR 19960048292 A KR19960048292 A KR 19960048292A KR 100237020 B1 KR100237020 B1 KR 100237020B1
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metal layer
layer
forming
semiconductor device
insulating layer
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KR19980029053A (en
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최승봉
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

본 발명은 반도체 소자의 금속층 형성 방법에 관한 것으로, 금속층 식각후 잔류되는 염소(Chlorine)성분을 수증기(H2O Fume)를 이용하여 제거시키므로써 금속층의 부식이 방지되고 공정의 진행이 용이하게 이루어질 수 있는 반도체 소자의 금속층 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal layer of a semiconductor device, which removes chlorine components remaining after metal layer etching using water vapor (H 2 O fume), thereby preventing corrosion of the metal layer and facilitating the progress of the process To a method of forming a metal layer of a semiconductor device.

Description

반도체 소자의 금속층 형성 방법Method for forming a metal layer of a semiconductor

본 발명은 반도체 소자의 금속층 형성 방법에 관한 것으로, 특히 금속층 식각후 잔류되는 염소 성분을 용이하게 제거할 수 있도록 한 반도체 소자의 금속층 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a metal layer of a semiconductor device, and more particularly, to a method of forming a metal layer of a semiconductor device capable of easily removing residual chlorine after etching a metal layer.

일반적으로 반도체 소자의 제조 공정에서 금속층은 알루미늄(Al)과 같은 금속으로 형성되며 이중 또는 다중 구조로 형성된다.Generally, in the manufacturing process of a semiconductor device, the metal layer is formed of a metal such as aluminum (Al) and is formed into a double or multi structure.

종래에는 제1도에 도시된 바와 같이 절연층(2)이 형성된 실리콘 기판(1)상에 금속층(3) 및 감광막(4)을 순차적으로 형성한 후 상기 감광막(4)을 패터닝한다. 그리고 제2도에 도시된 바와 같이 패터닝된 상기 감광막(4)을 마스크로 이용한 식각 공정으로 상기 금속층(3)을 패터닝한 후 CF4가스를 이용한 플라즈마(Plasma) 처리를 실시하여 노출된 상기 절연층(2)상에 잔류되는 염소(Cl) 성분을 제거한다. 이후 초수순을 이용하여 상기 절연층(2)의 표면을 1차 세정시킨 후 제3도에 도시된 바와 같이 상기 감광막(4)을 제거하고 솔벤트(Solvent)를 이용하여 상기 절연층(2) 및 금속층(3)의 표면을 2차 세정시킨다.Conventionally, as shown in FIG. 1, a metal layer 3 and a photoresist layer 4 are sequentially formed on a silicon substrate 1 on which an insulating layer 2 is formed, and then the photoresist layer 4 is patterned. As shown in FIG. 2, the metal layer 3 is patterned by an etching process using the patterned photoresist 4 as a mask, and then subjected to a plasma process using CF 4 gas, (Cl) component remaining on the substrate (2). After that, the surface of the insulating layer 2 is cleaned first, and then the photosensitive film 4 is removed as shown in FIG. 3, and the insulating layer 2 and the insulating layer 3 are removed by using a solvent. And the surface of the metal layer 3 is secondarily cleaned.

상기와 같은 금속층 패터닝 공정에는 CF4가스를 이용한 플라즈마 처리 및 초순수를 이용한 세정으로 이루어지는 치환 과정이 포함된다. 이는 금속층 식각후 잔류되는 염소(Cl) 성분이 대기중의 수분과 반응하므로써 발생되는 금속층의 부식을 방지하기 위하여 잔류된 염소(Cl) 성분을 불소(F) 성분으로 치환시키는 공정이다. 그런데 종래의 금속층 형성 방법을 이용하는 경우 상기 치환 공정에 소요되는 시간이 길고 솔벤트 세정을 위한 별도의 습식 세정조(Wet Station)가 필요하기 때문에 소자의 수율이 저하되는 문제점이 있다.The metal layer patterning process includes a plasma process using CF 4 gas and a cleaning process using ultra pure water. This is a process of replacing the residual chlorine (Cl) component with the fluorine (F) component in order to prevent the corrosion of the metal layer caused by the reaction of the residual chlorine (Cl) component with the moisture in the atmosphere. However, when the conventional metal layer forming method is used, the time required for the replacement process is long, and a separate wet washing station for cleaning the solvent is required, which leads to a problem that the yield of the device is lowered.

따라서 본 발명은 금속층 식각후 잔류되는 염소(Cl) 성분을 수증기를 이용하여 제거시키므로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속층 형성 방법을 제공하는데 그 목적이 있다.Accordingly, it is an object of the present invention to provide a method of forming a metal layer of a semiconductor device, which eliminates the above-mentioned disadvantages by removing the residual chlorine (Cl) component by using steam.

상기한 목적을 달성하기 위한 본 발명은 절연층이 형성된 실리콘 기판상에 금속층 및 감광막을 순차적으로 형성한 후 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 패터닝된 상기 감광막을 마스크로 이용한 식각 공정으로 상기 금속층을 패터닝하는 단계와, 상기 단계로부터 노출된 상기 절연층상에 잔류되는 염소 성분을 제거하기 위하여 CF4및 O2가스를 이용한 플라즈마 처리를 실시하는 단계와, 상기 단계로부터 수증기를 이용하여 상기 절연층의 표면을 세정시키는 단계와, 상기 단계로부터 상기 감광막을 제거한 후 초순수를 이용하여 상기 절연층 및 금속층의 표면을 헹구는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: sequentially forming a metal layer and a photoresist layer on a silicon substrate having an insulating layer formed thereon; patterning the photoresist layer; and etching the photoresist layer using the patterned photoresist layer as a mask. The method comprising the steps of: patterning a metal layer; performing a plasma process using CF 4 and O 2 gas to remove chlorine components remaining on the insulating layer exposed from the step; Cleaning the surface of the insulating layer and the metal layer, and rinsing the surface of the insulating layer and the metal layer using ultrapure water after removing the photosensitive film from the step.

제1도 내지 제3도는 종래 반도체 소자의 금속층 형성 방법을 설명하기 위한 소자의 단면도.FIGS. 1 to 3 are sectional views of a device for explaining a conventional metal layer forming method of a semiconductor device.

* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS

1 : 실리콘 기판 2 : 절연층1: silicon substrate 2: insulating layer

3 : 금속층 4 : 감광막3: metal layer 4: photosensitive film

이하, 상기 제1도 내지 제3도를 재 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the above first to third drawings.

먼저, 상기 제1도에 도시된 바와 같이 절연층(2)이 형성된 실리콘 기판(1)상에 금속층(3) 및 감광막(4)을 순차적으로 형성한 후 상기 감광막(4)을 패터닝한다. 그리고 제2도에 도시된 바와 같이 패터닝된 상기 감광막(4)을 마스크로 이용한 식각 공정으로 상기 금속층(3)을 패터닝한 후 CF4및 O2가스를 이용한 플라즈마(Plasma)처리를 실시하여 노출된 상기 절연층(2)상에 잔류되는 염소(Cl) 성분을 제거한다. 이때 상기 플라즈마 처리는 800 내지 1200mT의 압력 및 300 내지 500와트(W)의 고주파 전력(RF Power)이 공급되는 분위기하에서 실시되며 상기 CF4및 O2가스의 플로우(Flow)량은 각각 80 내지 100SCCM 및 5 내지 20SCCM이 되도록 한다. 이후 300 내지 600mT의 압력 및 300 내지 700SCCM의 수증기(H2O Fume)가 플로우되는 상태에서 400 내지 700와트(W)의 고주파 전력이 공급되도록 한 후 잔류되는 염소(Cl) 성분을 완전히 제거시키기 위하여 상기 수증기를 이용하여 상기 절연층(2)의 표면을 세정시키는데, 이때 상기 수증기와 염소(Cl)의 반응으로 인해 발생되는 HCl의 증발을 돕기 위해 상기 실리콘 기판(1)의 온도를 150 내지 200℃ 정도로 유지시킨다. 그리고 제3도에 도시된 바와 같이 산소(O2) 플라즈마를 이용하여 상기 감광막(4)을 제거한 후 초순수를 이용하여 상기 절연층(2) 및 금속층(3)의 표면을 헹구는데, 상기 감광막(4) 제거시 제거비(Ashing Rate)는 2 내지 10㎛/min가 되도록 한다.First, as shown in FIG. 1, a metal layer 3 and a photoresist layer 4 are sequentially formed on a silicon substrate 1 on which an insulating layer 2 is formed, and then the photoresist layer 4 is patterned. 2, the metal layer 3 is patterned by an etching process using the patterned photoresist layer 4 as a mask, and plasma processing using CF 4 and O 2 gas is performed to expose The chlorine (Cl) component remaining on the insulating layer 2 is removed. At this time, the plasma treatment is performed under an atmosphere of a pressure of 800 to 1200 mT and a RF power of 300 to 500 W, and the flow amounts of CF 4 and O 2 gases are 80 to 100 SCCM And 5 to 20 SCCM. Then, in order to completely remove the remaining chlorine (Cl) component after supplying a high frequency power of 400 to 700 watts (W) in a state of 300 to 600 mT of pressure and 300 to 700 SCCM of steam (H 2 O Fume) The surface of the insulating layer 2 is cleaned using the water vapor. In order to help evaporate the HCl generated due to the reaction of the water vapor and the chlorine (Cl), the temperature of the silicon substrate 1 is maintained at 150 to 200 ° C . 3, the photoresist layer 4 is removed using an oxygen (O 2 ) plasma, and then the surfaces of the insulating layer 2 and the metal layer 3 are rinsed with ultrapure water. 4) The removal rate (Ashing Rate) at the time of removal is 2 to 10 탆 / min.

상술한 바와 같이 본 발명에 의하면 금속층 식각후 잔류되는 염소 성분을 수증기를 이용하여 제거시키므로써 금속층의 부식이 효과적으로 방지되고 솔벤트를 이용한 세정 공정을 실시하지 않으므로 공정의 진행이 용이하게 이루어질 수 있으며, 따라서 소자의 신뢰성 및 수율이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, since the chlorine component remaining after the metal layer etching is removed by using steam, the corrosion of the metal layer is effectively prevented and the cleaning process using the solvent is not performed, so that the process can be easily performed. There is an excellent effect that the reliability and yield of the device can be improved.

Claims (6)

반도체 소자의 금속층 형성 방법에 있어서, 절연층이 형성된 실리콘 기판상에 금속층 및 감광막을 순차적으로 형성한 후 상기 감광막을 패터닝하는 단계와, 상기 패터닝된 감광막을 마스크로 이용한 식각 공정으로 상기 금속층을 패터닝하는 단계와, CF4및 O2가스를 이용한 플라즈마 처리를 실시하여, 상기 노출된 절연층 상에 잔류되는 염소성분을 1차적으로 제거하는 단계와, 300 내지 600mT의 압력 및 400 내지 700W의 고주파 전력이 공급되는 분위기하에서 수증기를 300 내지 700SCCM으로 플로우시켜 세정 공정을 실시하여, 상기 노출된 절연층 상에 잔류되는 염소성분을 2차적으로 제거하는 단계와, 상기 감광막을 제거한 후 초순수를 이용하여 상기 절연층 및 금속층의 표면을 헹구는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.A method of forming a metal layer of a semiconductor device, the method comprising: sequentially forming a metal layer and a photoresist layer on a silicon substrate having an insulating layer formed thereon; patterning the photoresist layer; and patterning the metal layer by an etching process using the patterned photoresist layer as a mask And a plasma treatment using CF 4 and O 2 gases to primarily remove chlorine components remaining on the exposed insulating layer, and a step of applying a pressure of 300 to 600 mT and a high frequency power of 400 to 700 W Removing the chlorine component remaining on the exposed insulating layer by performing a cleaning process by flowing water vapor at 300 to 700 SCCM in an atmosphere of supplying the insulating film, removing the photosensitive film, And rinsing the surface of the metal layer. . 제1항에 있어서, 상기 플라즈마 처리는 800 내지 1200mT의 압력 및 300 내지 500와트(W)의 고주파 전력이 공급되는 분위기하에서 실시되는 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.The method according to claim 1, wherein the plasma treatment is performed in an atmosphere in which a pressure of 800 to 1200 mT and a high frequency power of 300 to 500 W are supplied. 제1항에 있어서, 상기 CF4및 O2가스의 플로우 량은 각각 80 내지 100SCCM 및 5 내지 20SCCM인 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.The method according to claim 1, wherein the flow rates of the CF 4 and O 2 gases are 80 to 100 SCCM and 5 to 20 SCCM, respectively. 제1항에 있어서, 상기 세정 공정은 상기 실리콘 기판의 온도가 150 내지 200℃인 상태에서 실시되는 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.The method according to claim 1, wherein the cleaning step is performed at a temperature of 150 to 200 캜. 제1항에 있어서, 상기 감광막은 산소(O2)플라즈마에 의해 제거되는 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.The method of claim 1, wherein the photoresist layer is removed by an oxygen (O 2 ) plasma. 제1 또는 제5항에 있어서, 상기 감광막의 제거비는 2 내지 10㎛.min인 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.The method for forming a metal layer of a semiconductor device according to any one of claims 1 to 5, wherein the removal ratio of the photoresist film is 2 to 10 占 퐉 min.
KR1019960048292A 1996-10-25 1996-10-25 Method for forming a metal layer of a semiconductor Expired - Fee Related KR100237020B1 (en)

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JPH05335293A (en) * 1992-06-03 1993-12-17 Nippon Steel Corp Method and apparatus for manufacturing semiconductor device
JPH0737866A (en) * 1993-07-26 1995-02-07 Fujitsu Ltd Method for forming contact hole in multilayer wiring structure

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Publication number Priority date Publication date Assignee Title
JPH05335293A (en) * 1992-06-03 1993-12-17 Nippon Steel Corp Method and apparatus for manufacturing semiconductor device
JPH0737866A (en) * 1993-07-26 1995-02-07 Fujitsu Ltd Method for forming contact hole in multilayer wiring structure

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