KR100223646B1 - Interleaver and deinterleaver of global mobile communication system terminal - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to an interleaver and a deinterleaver of a global mobile communication system (GSM) terminal.

2. Technical problem to be solved by the invention

The present invention provides an interleaver and a deinterleaver that can implement an interleaver and a deinterleaver of a GSM terminal transmission and reception unit in hardware.

3. Summary of Solution to Invention

When interleaving the GSM terminal transmitter, the voice data is written to the memory means using the formula defined in the GSM specification. After the deinterleaving, the voice data is sequentially written to the memory means, and at the time of reading, the address is generated using an equation defined in the GSM specification to restore the order of the voice data.

4. Important uses of the invention

Used for global mobile communication system terminals.

Description

Interleaver and deinterleaver of global mobile communication system terminal

1 is a block diagram of a typical GSM terminal.

2A and 2B are block diagrams of the interleaver 30 and the deinterleaver 52 in the first diagram.

3A and 3B are memory map configuration diagrams of the interleaver memory 76 and the deinterleaver memory 86 in FIG.

4 is a memory map diagram for showing read / write order in case of full rate speech.

The present invention relates to Global System for Mobile Communication (hereinafter referred to as GSM), and more particularly, to an interleaver and a deinterleaver of a GSM terminal transmission and reception unit.

In general, European digital cellular communication systems adopt GSM as a standard. The GSM regulation stipulates only the order in which data bits inputted for interleaving and deinterleaving should be output. For example, for Full Rate Speech,

i (B, j) = c (n, k)

B = Bo + 4n + k mod (8)

j = 2 [(49k) mod57] + [(k mod8) div4] In this case, i (B, j) is interleaved data and c (n, k) is the input data of the interleaver as the output of the convolutional encoder. N denotes the number of data blocks to be transmitted, and B denotes an order of bursts of the output data. Bo represents the first burst, usually zero. k is a number indicating a bit position in the input data block, and j is a bit position in the output burst. In the case of a plate spitz, one data block composed of 456 bits (called a first data block) is input, spread into eight bursts, and then outputs the first four bursts. In this case, one burst consists of 114 bits, and when the next second data block is input, the remaining four bursts of the first data block and eight bursts using the new four bursts are spread to spread the remaining four bursts of the first data block. Is output. When the first data block is input, n is 0. Therefore, as the input bit order k increases, the order of the output data is determined as follows.

c (0, 0) i (0, 0), c (0, 1) i (1, 98), c (0, 2) i (2, 82)

c (0, 3) i (3, 66), c (0, 4) i (4, 51), c (0, 5) i (5, 33)

c (0, 6) i (6, 19), c (0, 7) i (7, 3), c (0, 8) i (0, 100)... When the next second data block is input, n = 1, the output data order is as follows, as k, the input bit order, is increased.

c (1, 0) i (4, 0), c (1, 1) i (5, 98), c (1, 2) i (6, 82)

c (1, 3) i (7, 66), c (1, 4) i (8, 51), c (1, 5) i (9, 33)

c (1, 6) i (10, 19), c (1, 7) i (11, 3), c (1, 8) i (4, 100)... In the above-described determination of the data output order, the second bit of the first data block is output to the 99th of the second burst, and the sixth bit of the first data block is output to the 34th of the sixth burst. In addition, it can be seen that the second bit of the second data block is output to the 99th of the sixth burst, and the sixth bit of the second data block is output to the 34th of the tenth burst. In the case of data, one 456-bit data block is input, spread over 22 burst sections, and then output by four bursts. The SACCH (SACCH), SDCCH, which is a control channel, is inputted with one block of 456 bits, spread over four bursts, and output one burst at a predetermined location. RACH (Random Access Channel) and SCH (Synchronize Channel) is inputted with one data block consisting of 36 bits and 78 bits, respectively, and outputted without changing bit order in one burst. As described above, the GSM regulations formally define interleaving and deinterleaving. However, the provisions of actual hardware are not provided.

Accordingly, an object of the present invention is to provide an interleaver and a deinterleaver that can implement interleaving and deinterleaving of a GSM terminal transmission and reception unit in hardware.

The present invention provides an interleaver memory for interleaving voice decoded data transmitted from a talker of the terminal to prevent burst error on a transmission path; A write address generator for generating and outputting a write address in accordance with a specification of a global mobile system that defines in what order the input data bits should be output; A read address generator for generating and outputting a read address for sequentially reading data written to the interleaver memory; And an interleaver configured to select and output an address output from the write address generator and the read address generator to the interleaver memory according to a logic state of an interleave read / write signal.

The present invention also includes a deinterleaved memory for inputting and deinterleaving restoration data before encryption; A write address generator for generating and outputting a sequential address of the terminal from the restored data; A read address generator for generating and outputting a read address so that the restoration data written to the deinterleaver memory is read according to the specification of the global mobile system; And a deinterleaver comprising a selector for selectively outputting one of the signals input from the read address generator and the write address generator to the deinterleaver memory according to a logic state of the deinterleave read / write signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, numerous specific details such as the number of bits and the number of bursts of specific data blocks are shown to provide a more general understanding of the invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

1 is a block diagram of a GSM terminal according to the present invention. The GSM terminal is composed of a transmitter and a receiver. First, referring to the transmitter, the voice signal input from the transmitter 20 is converted into digital data by an analog-to-digital converter (ADC) 22, and the cyclic redunancy code (CRC) bits of the block encoder 24 are converted into digital data. After the tail bit is added, the bit ordering unit 26 is applied to the convolutional encoder 28 after the bit order is reversed. At this time, data input from a peripheral device such as a computer is directly input to the convolutional encoder 28 through the data interface 64. Data encoded by the convolutional encoder 28 is input to an interleaver 30 and interleaved to prevent burst errors on the transmission path. The interleaved data is ciphered by the encryptor 32 and reorganized into a burst structure according to the transmission standard in the burst builder 34 and then modulated in the GMSK (Gaussian Minimum Shift Keying) modulator 36. do. The GMSK-modulated data is converted into an analog signal by a digital to analog converter (DAC) 38 and wirelessly transmitted to a base station through an antenna 42 via an RF (Radio Frequency) transmitter 40. .

On the other hand, referring to the operation of the GSM terminal receiver, the signal transmitted from the base station is received by the RF receiver 44 through the antenna 42 and converted into digital data by the ADC 46 and then GMSK demodulation and equalizer ( Demodulated at 48). It is then restored to the data before it is encrypted in the decryptor 50 and deinterleaved by the deinterleaver 52 to be brought into a state before interleaving and applied to the convolutional decoder 54. In the Viterbi-decoded output by the convolutional decoder 54, data is transmitted to the peripheral device via the data interface 64, and the voice data is the bit deordering unit 56 and the block decoder 58. After being converted into an analog signal by the DAC (60) through the receiver 62 is output as a voice.

2a shows a block diagram of the interleaver 30 according to the present invention. In FIG. 2A, the interleaving write address generator 70 generates a write address according to a formula defined by the GSM SPEC and outputs the write address to the interleaver memory 76 through P1 of the multiplexer 74. The read address generator 72 sequentially generates read addresses and outputs the read addresses to the interleaver memory 76 through P2 of the multiplexer 74. The multiplexer 74 selects and outputs the write address and read address by the interleaver 30 read / write signal IN R / W input through P3. At this time, the interleaver memory 76 writes the decoded data Txc (Transmit Convolution Encoder Oupput) transmitted from the convolutional encoder 28 to the write address input through the multiplexer 74. Thereafter, when the data write is completed, the interleaver memory 76 outputs data corresponding to read addresses sequentially input through the multiplexer 74. Hereinafter, data output from the interleaver memory 76 is defined as Txi (Transmit Interleaving). First, when the interleaver 30 writes the decoded data Txc transmitted from the convolutional encoder 28 to the interleaver memory 76, the interleaving write address generator 70 generates a write address according to the formula defined in the GSM SPEC and generates the write address. The decoding data Txc is written to the write address. At this time, the decoded data input to the interleaver 30 is input in units of data blocks, and when one data block is input, the interleaving write address generator 70 spreads using an area corresponding to a burst according to the formula defined in the GSM SPEC standard. Let's do it. After the data write is completed, the read address generator 72 generates a sequential read address and reads and outputs data of the read address. That is, since the data read is sequentially read from the bit of? B of the burst B ?, even if the decoded data Txc entered earlier is written to the rear end of the interleaver memory 76, it is output late. By using this, the order of the output data Txi of the interleaver 30 can be changed, and the data Txi output from the interleaver memory 76 is read out by four bursts. That is, the read address generated by the read address generator 72 is as follows in the case of the first data block.

Bø (ø) Bø (1) Bø (2) … Bø (113) B1 (ø) B1 (1) … B1 (113) B2 (ø) … B2 (113) B3 (ø) B3 (1) … B3 (113).

B4 (ø) for the second data block B4 (1) … B4 (113) B5 (ø) … B5 (113) B6 (ø) … B6 (113) B7 (ø) … Same as B7 (113).

FIG. 2B shows a block diagram of the deinterleaver 52 in FIG. 1 and the deinterleaving is performed in the reverse of interleaving. In FIG. 2B, the write address generator 80 sequentially generates the same address as the read address generator 72 of the interleaver 30 and outputs the same address to the deinterleaver memory 86 through P4 of the multiplexer 84. The deinterleaving read address generator 82 generates an address matching the value obtained by the equation of GSM SPEC and outputs it to the deinterleaver memory 86 through P5 of the multiplexer 84. The multiplexer 84 selects and outputs the write address and read address by the deinterleaver 52 read / write signal DIN R / W input through P6. At this time, the deinterleaver memory 86 writes data Rxdci (Receive Deciphering Output) transmitted from the decoder 50 to the write address input through the multiplexer 84. Thereafter, when the data write ends, the deinterleaver memory 86 outputs data corresponding to the deinterleaving read addresses sequentially input through the multiplexer 84 to restore the interleaved data order for the first time. Hereinafter, data output from the deinterleaver memory 86 is defined as Rxdi (Receive Deinterleaving Output).

3A and 3B show schematic structures of the memories 76 and 86 used in the interleaver 30 and the deinterleaver 52, respectively, and B24, B25 on the horizontal axis. Denotes a burst area, and?, 1, 2, 3, ..., 113 of the vertical axis indicate bit positions in each burst B. FIG. First, in the interleaver memory 76 (FIG. 3A), since the maximum area spread during interleaving of voice data is 8 bursts, interleaving can be performed using B? To B7. In other words, when the writing and reading of the first data block is over for the part over 8 bursts, the data in the 4 burst parts has already been output and can be used again. On the other hand, 22 burst areas are required since data input from peripheral devices is spread over 22 bursts. However, since voice data and data from peripheral devices do not overlap, the same memory area can be used. That is, audio data uses bursts B? -B7, and data input from peripheral devices uses bursts B? -B21. In addition, the fast associated control channel (FACCH) of the control data uses only four bursts of the bursts B? B2 by stealing the data. The SACCH input between the voice data and the data should be written one burst of data in four burst areas and then output one burst every given time so that separate areas (B22 to B25) are allocated so that there is no loss of data. do. That is, when only the control signal is transmitted, the RACH uses burst B? And the SACCH uses bursts B22 to B25.

3B shows the structure of the deinterleaver memory 86. In addition to the use area of the interleaver memory 76, a burst young B26 for SCH is separately provided. The reason is that SCH data can be input in the middle of the voice data or the control data, thereby preventing damage to the voice data and the control data. By setting the memory structure as described above, it is possible to minimize the memory size by sharing the burst area that can be shared to the maximum.

4 is a diagram illustrating a memory configuration showing a procedure for writing / reading data into a memory in the case of full rate speech according to an embodiment of the present invention. First, in the interleaving operation, the data of the first input data block is first written to eight burst areas B? B7 in the order of the solid lines. Burst Bø for reading subsequent written data B1 B2 Leads in the order of B3. If this is expressed in the order of the input data, i (0, 0) X i (0, 64) X i (0, 128) X i (0, 392) X i (0, 57) … (Where X represents no data). When the first data comes in, 456 bits are spread across eight bursts, so half of the first four burst regions are not filled. After that, when the next data block is input, it is written in the order of the dotted line. After the light is finished, the next four bursts are B4 B5 B6 Leads in the order of B7. I (1, 0) i (0, 228) i (1, 64) i (0, 982) … i (0, 4) … i (1, 392) i (0, 164) i (1, 57) i (0, 285) … Leads in order. Therefore, the interleaving defined in the GSM SPEC is satisfied. Then, the procedure for restoring the interleaved data back to the first data is as follows. The first four bursts B1 B2 Write in the order of B3. However, since eight bursts are required to restore the first data block, deinterleaving is performed after four additional bursts are written. The next four bursts are B4 B5 B6 After writing in the order of B7 and reading in the order of the solid line shown in FIG. 4, the data output is i (0, 0) i (0, 1) i (0, 2) i (0, 3) … Same as Afterwards, the next four bursts are added to Bø B1 B2 After writing in the order of B3 and reading in the order of the dotted lines shown in FIG. 4, data is output in the following order. i (1, 0) i (1, 1) i (1, 2) i (1, 3) … . Therefore, it can be seen that the interleaved data is completely restored to the original data through deinterleaving.

As described above, the present invention has the advantage that hardware can implement the interleaving and deinterleaving of the GSM terminal transmission and reception unit.

Claims (2)

In an interleaver of a global mobile communication system terminal, An interleaver memory for interleaving voice decoded data transmitted from the transmitter of the terminal to prevent burst error on a transmission path; A write address generator for generating and outputting write addresses in accordance with the specification of the global mobile system that defines the order in which the input data bits should be output; A read address generator for generating and outputting a read address for sequentially reading data written to the interleaver memory; And a selector configured to selectively output an address output from the write address generator and the read address generator to the interleaver memory according to a logic state of an interleave read / write signal. In the deinterleaver of the global mobile communication system terminal, A deinterleaver memory for inputting and deinterleaving restoration data before encryption; A write address generator for generating and outputting a sequential address so that the decompression data is written to the deinterleaver memory in the order of the interleaver output data of the terminal; A read address generator for generating and outputting a read address so that the restoration data written to the deinterleaver memory is read according to the specification of the global mobile system; And a selector for selectively outputting one of the signals input from the read address generator and the write address generator to the deinterleaver memory according to the logic state of the deinterleave read / write signal. Interleaver.