KR100225902B1 - Method of adjusting gradation of display system by irregular addressing - Google Patents

Abstract

The development of plasma flat panel displays has enabled applications in television and computer monitors. In such a display panel, unlike a simple display panel such as a numeric display, it is indispensable to display a sufficient color tone, which is achieved by adjusting the gradation of each color pixel. In an AC-PDP or a DC-PDP driven by a memory method, gray level adjustment is generally performed by adjusting the number of sustain discharges. Conventional gray scale adjustment by sequential addressing requires that pixels be off It requires a high scanning frequency and a high current for a constant brightness, thereby consuming a lot of power. In order to solve these problems, unlike the conventional driving method in the plasma display system, an irregular addressing method in which at least two electrode lines are addressed by different sub-field order or permutation, and the lengths of the sub- to provide. According to the irregular addressing method of the present invention, it is possible to minimize the time when the pixels are turned off in the gray level adjustment. As a result, it is possible to reduce the amount of current flowing through the pixels of the driving circuit and the plasma display panel for achieving a constant brightness and to lower the scanning frequency, thereby improving the brightness of the plasma display panel, reducing power consumption, And shows an advantage that the manufacturing of the driving circuit is simplified.

Description

Method and system for adjusting gradation of display system by irregular addressing

The present invention relates to a display system, and more particularly, to an addressing apparatus and method of a plasma display panel.

BACKGROUND ART [0002] Researches on a flat panel display device as a display device used for a television, a computer monitor, an advertisement board, and the like are actively conducted. Among such flat panel display devices, plasma display panels (hereinafter referred to as PDPs) are widely developed for television and computer monitors because they are large in size and simple in structure.

The PDP can be roughly divided into a DC-PDP and an AC-PDP. The DC-PDP has a matrix structure in which pixels are located at points where a plurality of anode lines and cathode lines intersect each other. Either the positive polarity line or the negative polarity line becomes a scanning electrode, and a scanning pulse is sequentially applied to each pixel in a predetermined order. The other electrode line intersecting the scan electrode line becomes a data electrode or a signal electrode and determines whether the pixels connected to the scan line addressed according to the image data are turned on and off. At this time, a sustain pulse is applied to the unaddressed electrode lines, and the pixels that are once turned on when addressed are kept turned on by the sustain pulse. In the case of off pixels, the sustain pulse voltage is kept lower than the initial discharge voltage (Firing Voltage or Ignition Voltage) of the pixel. When the turned-on pixels are turned off, a sustain pulse is removed from the scan electrode for a predetermined period or more, and an erase pulse (Extinction Pulse) is provided to turn off all the pixels connected to the scan electrode at once.

AC-PDPs can be roughly divided into two types: a double substrate structure and a surface discharge structure. Like the DC-PDP, the AC-PDP has a pixel at the intersection of a column electrode and a row electrode, and a sustain pulse is periodically applied to each electrode line. In the AC-PDP having a double substrate structure, a sustain pulse is applied to both the scan electrode and the signal electrode by using one of the row and column electrode lines as the scan electrode and the other as the signal electrode like the DC-PDP, And a signal voltage is applied to the signal electrode.

In the AC-PDP of the surface discharge structure, the scan electrodes are arranged in parallel to the common electrode, and the signal electrodes are orthogonal to the common electrode and the scan electrode, and the pixels are located at the intersections. Surface discharge structure There are two types of driving method of AC-PDP that are simultaneous with addressing and sustaining separated by time (ADS method). In the ADS method, an erasing discharge is generated between the common electrode and the scanning electrode to remove wall charges from all the pixels on the entire screen, and scan voltage pulses are successively applied to the scanning electrodes, A signal voltage pulse corresponding to the video signal is applied through the signal electrode. After the addressing of the entire screen is completed, the sustain discharge is performed for a period determined by the binary weight of the subfield, and these processes are repeated for a predetermined number of subfields within one frame period. The manner in which the addressing and the sustain is simultaneously performed is similar to the driving method of the double substrate structure, and the irregular gray scale adjustment method of the present invention is effective in such a manner that the addressing and the sustain are simultaneously performed.

FIG. 1 is a view schematically showing a PDP display system. The display system of FIG. 1 comprises a PDP panel 1, a signal electrode line driving circuit 2, a scanning electrode line driving circuit 3, a control circuit 4 and an interface circuit 5 which are display portions. The PDP panel 1 serves as a video display unit, and is composed of a plurality of row electrodes and column electrodes and a plurality of pixels located at the intersections. The scan electrode line driving circuit 3 is connected to a plurality of scan electrode lines, and applies a pulse voltage for addressing to a predetermined scan electrode line in addition to periodically applying discharge sustain voltage pulses to all the scan electrodes. The signal electrode line driver circuit 2 is connected to a plurality of signal electrode lines, and applies a voltage to the signal electrode line corresponding to a video signal corresponding to a pixel selected by the scanning electrode line. The control circuit 3 is connected to the signal electrode line driving circuit 2 and the scanning electrode line driving circuit 3 to control turning on and off of each pixel. The interface circuit 5 is connected to the control circuit 4 and converts a video signal input to the PDP display system into a signal suitable for the control circuit and transmits the converted signal.

FIG. 2 is a view illustrating an addressing method in the PDP as shown in FIG. The signals applied to the scan electrode lines and the signal electrode lines are all pulse-shaped signals, and different voltage waveforms are applied to the scan electrode lines in accordance with three operation modes of Extinction, Sustain, and Writing. In the case of the basic addressing method, only one of all the scan electrodes is addressed in one pulse period. When the entire scan electrodes are divided into a plurality of frames, one scan electrode can be addressed for each frame in one pulse period.

In the signal electrode, a signal corresponding to each signal electrode line is applied according to image information to be displayed on pixels corresponding to the addressed scan electrode. When the entire scan electrodes are divided into a plurality of frames, the number of signal electrode driving circuits should be equal to the number of frames.

Each pixel of the display system is at a position corresponding to the intersection of the signal electrode and the scan electrode. Whether the pixels are turned on or not is determined depending on what voltage waveform is applied to the signal electrode when scan addressing through the scan electrode. 2, in order to conceptually explain the driving method of the memory type PDP, a voltage waveform as shown is applied from the initial state in which all the four pixels connected to the two scan electrodes and the two signal electrodes are turned off in the DC-PDP And how each pixel is turned on and off. That is, in the T1 period, the S1 scan electrode line is addressed and a low voltage (Vk) is applied only to the signal electrode line D1, so that the pixel P11 is turned on. This is called writing. The turned-on pixel P11 is kept turned on until the S1 scan electrode line is turned off in the period T5. Likewise, the pixel P21 and the pixel P12 are also turned on in the periods T3 and T6, respectively.

The driving scheme conceptually illustrated in FIG. 2 can be applied to a DC-PDP or an AD-PDP having an arbitrary number of electrode lines. Actual voltage waveforms and timing can be determined by the electrode structure, the presence or absence of auxiliary electrodes or auxiliary pixels, As shown in FIG.

A PDP having such an addressing structure is mainly applied to a video display such as a television or a computer monitor. Unlike a simple display panel such as a numeric display, a sufficient color tone is indispensable in a television or a computer monitor. In the AC-PDP or the DC-PDP driven by the memory method, the gray scale adjustment is performed by adjusting the ON time of each pixel.

Grayscale adjustment in the memory scheme is basically done by determining how long a pixel is on for a fraction of a frame period. For example, in the case of performing a display function with 8-bit 256 gradations, the brightest pixel is turned on 255 × M times (where M is a minimum unit of gradation as an integer) within one frame period, which means that 255 × M It means receiving a sustain pulse.

However, since it is inefficient to perform individual gradation adjustment for all of a large number of pixels, a subfield method is mainly used in conventional memory type gray scale adjustment. The subfield method is a method in which the entire frame period is divided into subfields given a binary weight, and the time during which the pixel is turned on in each subfield is determined by the binary weight of the subfield. Therefore, the number of subfields in one frame period is equal to the number of bits of the digital input signal for indicating the brightness of the pixels for gray scale adjustment.

FIG. 3 is a view schematically showing the timing of 8-bit gradation adjustment addressing in the subfield method. In the case of the 8-bit gradation adjustment in the subfield method, one frame period is divided into 8 subfields, and the time during which the pixels are turned on in each subfield is 128 (= 27) × M, 64 (= 26) 25 = M, 16 (= 24) M, 8 (= 23) x M, 4 (= 22) x M, 2 (= 21) x M and M. In the case where the arrangement of the binary weights of the subfields is arranged in this order, if the gradation of an arbitrary pixel is represented by a binary number '10101101', the pixel has 128 × M, 32 × M, 8 × M, M is turned on only when addressed in the subfield of the binary weight, and is turned off in the other subfields.

As shown in FIG. 3a, in the conventional gray scale adjustment by the sub-field method, the length of the sub-field is determined by the number of the electrode lines. That is, the length of the subfield is determined as the product of the number of the electrode lines and the period of the scan signal or a multiple thereof. Also, in the conventional method, all the pixels are sequentially addressed in the same subfield, so that the order of proceeding from one subfield to the next is the same in all pixels. Therefore, all the pixels are turned on for a time corresponding to the binary weight of the subfield after the addressing corresponding to the corresponding subfield is performed, and until the address corresponding to the subfield is addressed after the lapse of the time corresponding to the binary weight, The off state is maintained by the pulse. That is, in the conventional sub-field method, since the length of the sub-field is constant, in order to vary the turn-on time of the pixel in each sub-field, the time required for the pixel to be turned off necessarily occurs. As a result, according to the sub-field method, even the brightest pixel as shown in FIG. 3a must be turned off for a predetermined time or longer, which is an obstacle to the brightness of the PDP screen.

As described above, in the conventional method, all the scan electrode lines are driven by the same sub-field sequence and permutation, but in the irregular addressing, at least two electrodes are driven by different sub-field permutations, as shown in FIG. For example, in the case of 8-bit grayscale driving, the number of different permutations in the order of applying 8 subfields is , Which is much larger than the electrode line of a general PDP.

The irregular addressing in FIG. 3b utilizes the fact that even when only a part of different sub-field permutations are applied, the time for which the screen of the PDP is turned off can be greatly reduced. The present invention applies irregular addressing The condition for determining the addressing order when performing the addressing is specified.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a PDP display system with improved luminous efficiency of a display device. Here, the luminous efficiency refers to the ratio of the brightness of the display device to the power supplied to the display device through the drive circuit.

It is another object of the present invention to provide a PDP display system by an irregular addressing method.

It is still another object of the present invention to provide a method of adjusting grayscales by an irregular addressing method.

It is still another object of the present invention to provide a method of adjusting a gradation of a display system.

It is still another object of the present invention to provide a gradation adjusting apparatus of a display system.

The irregular addressing method according to the present invention can be implemented as a method of applying a general binary value signal as one of signal applying methods in addition to application to a display system.

FIG. 1 is a conceptual diagram schematically showing a display system using a plasma display panel. FIG.

Fig. 2 schematically shows the addressing scheme for each pixel in the display system of Fig. 1; Fig.

3A and 3B are diagrams conceptually showing a conventional gray scale adjustment method of a sub-field method and an irregular addressing method.

FIG. 4 is a conceptual diagram showing a 3-electrode line and a 4-bit gradation method by irregular addressing according to the present invention;

FIG. 5 is a conceptual diagram showing a sequence of 8-electrode lines and 4-bit gradation irregular addressing by interleaving the irregular addressing method and the conventional sequential addressing method according to the present invention.

6 is a conceptual diagram showing a permutation order and an addressing order of subfields when the irregular addressing method according to the present invention is applied to 10 electrode line groups.

DESCRIPTION OF THE REFERENCE NUMERALS

1: PDP panel 2: signal electrode line driving circuit

3: scan electrode line drive circuit 4: control circuit

5: Interface circuit

According to the principles of the present invention, there is provided a method of adjusting a gradation of a display system as follows.

[1] A display device comprising: display means including a plurality of pixels for displaying a video signal; a plurality of first electrode lines connected to a plurality of pixels; a plurality of second electrode lines intersecting the first electrode lines and connected to a plurality of pixels; A display signal applying means for applying a display signal to at least one of the first electrode line and the second electrode line, and control means for controlling an application time of the display signal, To the display signal applying means a control signal for maintaining a desired pixel in an ON state for a time corresponding to one of a plurality of sub time periods included in the cycle, The display signal is applied to the first electrode line in response to the control signal, and the plurality of sub-time periods is a binary weight of the video signal indicated by the binary value The upper display signal is not applied to the pixels already in ON state and the display signals corresponding to the same lower time period are not sequentially applied to the pixels adjacent to each other , And a display signal corresponding to a different sub-time period is applied to pixels adjacent to each other at the same time point, thereby reducing the time during which the pixels are not displayed, thereby improving the luminous efficiency of the pixels .

In the gray scale adjustment method of [1], the predetermined time period is equal to or larger than M × N (M: number of first electrode lines, N: gray scale adjustment is bit number) which is the minimum time period required for addressing. And a uniform unit time period that is a multiple of the least common multiple of 2 ^N -1, which is the minimum number of cycles for displaying the value.

According to the principle of the present invention, there is provided a gradation adjusting apparatus of a display system as described below.

[2] A display system including a display unit including a plurality of pixels for displaying a video signal, a plurality of first electrode lines connected to a plurality of pixels, and a plurality of second electrode lines crossing the first electrode lines and connected to a plurality of pixels, A display signal applying means for applying a display signal to at least one of the first electrode line and the second electrode line and a control means for controlling the application time of the display signal, The display signal applying means applies a control signal to the display signal applying means for maintaining the desired pixel in the ON state for a time corresponding to one of the plurality of sub time periods included, And applying a display signal to the first electrode line in response to the first signal, wherein the plurality of sub-time periods are proportional to the binary weight of the video signal indicated by the binary value The display signal has a different temporal length and the display signal is not applied to the pixels that are already in the ON state and the display signals corresponding to the same sub time period are not sequentially applied to the pixels adjacent to each other, Wherein a display signal corresponding to a different sub-time period is applied to adjacent pixels to thereby reduce a time period during which pixels are not displayed, thereby improving the luminous efficiency of the pixels.

The tone adjustment device of [2] may further include the following features.

(1) The predetermined time period is equal to or larger than M × N (M: number of first electrode lines, N: number of bits of gray scale adjustment) which is the minimum time period required for addressing. And a non-uniform unit time period that is a multiple of the least common multiple of 2 < ^N >

(2) The control means further includes a storage means for storing the order of application of the control signal when the number of the first electrode lines and the number of bits of the gray scale adjustment are determined, and the control signal of the control means is stored in the storage means As shown in FIG.

The principle of irregular addressing of the present invention can be applied to the application of a general binary value signal, wherein the following method and apparatus for applying a binary value signal are provided according to the principles of the present invention.

[3] a predetermined time period in which a group of signals represented by binary values are applied includes a plurality of sub-time periods (sub-time periods) corresponding to respective application time periods of a group of signals, A method of applying a binary value signal having a different temporal length proportional to the binary weight of a signal represented by the binary value, wherein the binary value signal is not redundantly applied to the element to which another signal has already been applied, Wherein signals corresponding to the same sub-time period are not sequentially applied to the devices, and display signals corresponding to different sub-time periods are applied to the devices adjacent to each other at the same time point.

[4] An apparatus for applying a binary signal, comprising: signal applying means for applying the binary signal to a desired device; and control means for controlling the application time of the binary signal, Applies a control signal to the signal applying means to maintain the desired element in an ON state for a time corresponding to one of a plurality of sub time periods included in the time period, Applying a binary signal to a desired device in response to the control signal, wherein the plurality of sub-time periods have respective different temporal lengths proportional to the binary weights of the binary signal, The binary value signals corresponding to the same sub time period are not sequentially applied to the elements adjacent to each other And a binary value signal corresponding to a different sub-time period is applied to the elements adjacent to each other at the same time point.

Other objects, features, and advantages of the present invention will be apparent from the following detailed description and the accompanying drawings.

The irregular addressing according to the present invention is a method of determining the addressing order of the scan electrodes in controlling the brightness of the pixels. It is the same as the conventional sub-field method in which the gray scale adjustment is performed by adjusting the number of sustain discharges in accordance with the input digital video signal The lengths of the subfields are proportional to the binary weights corresponding to the subfields so that they have different temporal lengths and the order is set such that the addressing of the scan electrodes do not overlap each other within one addressing period, It is a way to maximize the luminous efficiency by eliminating or minimizing the time that must be present. The concept of the irregular addressing of the present invention basically consists of row and column electrode lines (or signal transmission devices), and either one of the row or column electrode lines becomes a scan electrode and a scan signal such as an addressing voltage is applied to the scan electrode In a system capable of selecting pixels (or display elements) placed at the intersection of a row and a column, the subsequent state of the selected pixel can be selected and selected (either in the on or off state).

That is, irregular addressing according to the present invention is intended to eliminate the time required for scan addressing the entire screen separately from the time when the pixels are grown in each subfield in the case of the subfield method by sequential addressing. According to the present invention, the length of each sub-field is made to be proportional to the binary weight corresponding to the sub-field, so that the scan electrodes have a different temporal length, Fields are addressed differently from one another in order to be able to belong to subfields having different binary weights for each pixel at the same time. For example, assuming that the addressing period and the sustain period are both 1 in the 4-bit gradation adjustment, 15 sustain pulses are applied to each pixel, and are addressed four times each. Therefore, three electrode lines can be addressed for irregular addressing within 15 pulse periods. In general, the number of electrode lines in irregular addressing is not determined by the address method, but is determined according to the specification of the display device. For example, in the case of VGA, the number of pixels is 640 × 480, and each pixel has three color pixels, so that the actual number of pixels is tripled. In most flat panel display devices, a matrix driving method is used, and addressing is performed by an X-electrode line and a Y-electrode line. For example, when the X-electrode line is a scan electrode line, the Y-electrode line becomes a signal electrode line. In the plasma display system, it is desirable that the frequency of the scan signal is low. Therefore, in the case of VGA, the number of scan electrodes is generally 480, and thus the number of signal electrodes is 640 × 3. FIG. 4 illustrates an addressing sequence of scanning electrode lines when three electrode lines are adjusted in 4-bit gradation, where Ai (i = 0, 1, 2, 3) Lt; RTI ID = 0.0 > subfields. ≪ / RTI > That is, A0 = 1, A1 = 2, A2 = 4, and A3 = 8.

As shown in Fig. 4, when L1 is addressed at T = 1, the 0th bit signal is applied to the signal electrode line. When T = 2, L1 is again addressed, and the 1 st bit signal is applied to the signal electrode line, And the pixels lying in L1 in 3 are located in a subfield with a binary weight of 1. At T = 3, a signal of the first bit is applied to the signal electrode line by addressing L2, and the pixels in L2 at T = 3 and 4 are in a subfield having a binary weight of 1. As described above, it can be seen that the signal of the binary weight corresponding to the signal electrode line can be applied so that addressing to each electrode line is not overlapped in each address period, and the electrode lines L1, L2, and L3 are 0-1-2- 3, 1-0-2-3, and 1-2-0-3, respectively.

In order to adjust the N number of electrode lines in 4-bit gradation, four address cycles are required for one electrode line, so 4 × N address cycles are required. However, since 4 x N address periods must be generated within 15 sustain cycles, an address period that is larger than 4 x N and is a multiple of 15 close to 4 x N is required.

When performing 8-bit gradation adjustment with 480 scan electrodes, such as VGA, at least 4080 address periods are required, which is greater than 8 × 480 and a multiple of 255, and the brightest pixel may be on for the entire period of one frame period . This results in a brightness of more than four times that in the case of FIG. 1, in which an address period of 8 x 480 is required in one frame period and pixels can be turned on for only a quarter of the frame period. However, in the sequential addressing method, when the pixel is turned on twice or four times, the number of pulse periods required for one frame period increases by 12.5% and 50%, respectively, so that the turn-on time of the pixel is 4/9 and 8/12 However, this causes a problem that the scanning frequency is increased, and even if the scanning frequency is increased, it does not reach the brightness of the irregular addressing.

In the above description, it is assumed that the DC-PDP is turned off momentarily when the pixel is turned off. However, in the case of the DC-PDP, it is necessary to turn off the sustain pulse during one or more sustain cycles because the plasma is required to be decayed after discharge. In this case, one frame period TF is given by TF = NS x TP + N x NE x TP, where TP is the sustain and addressing pulse periods, NS is the number of sustain pulses in one frame, N is the number of binary bits of gray- Is the number of pulses required to turn off the pixel. The number of sustain pulses NS in one frame should be a multiple of 15 for 4-bit grayscale adjustment, and a multiple of 63 and 255 for 6-bit and 8-bit, respectively. As an example, in order to address 480 electrode lines in one frame when an 8-bit gradation adjustment of a PDP having NE = 4 and an addressing number of 480 is performed, NS + 8 × 4 8 × 480 must be satisfied. And NS must be a multiple of 255, so the minimum NS is 3825.

FIG. 5 shows that 8-electrode lines are irregularly addressed when NE = 1 and NS = 3 × 7 with 3-bit gradation adjustment. In FIG. 5, E indicates a period during which the electrode lines are turned off, and FIG. 5 shows what image signals are to be transmitted to the data electrode lines in the bottom column. For example, sending the least significant bit of the pixels connected to the electrode line L1 in the first period and the most significant bit of the pixels connected to the fourth period in the second period.

As shown in FIG. 5, since there are only two subfields 0-1-2 and 2-1-0 in the 3-bit gradation driving, L1 to L4 have a sequence of 0-1-2 and L5 to L6 are 2- Lt; RTI ID = 0.0 > 1-0 < / RTI > Therefore, when only the L1 to L4 or L5 to L6 electrode lines are viewed, they are driven by the conventional sequential addressing scheme, and thus the electrode line groups having different sub-field order are sequentially addressed in the group and irregular addressing is caused between the groups. do. With this interleaving, many electrode lines can be irregularly addressed with fewer subfield permutation combinations.

Actually, in PDP, since there are many electrode lines and high gradation units, the number of permutation combinations increases, so a computer program must find a permutation combination satisfying the conditions described above. For example, in the 6-bit grayscale adjustment, the minimum number of time periods NT is 63 and TF-69 when NE = 1, so that the maximum NS is INT (69/6) and NS = 11. In FIG. 6, a case in which each electrode line group can be driven by permutation in different subfields with NS less than ten is found by a computer program. In actual PDP, it is possible to perform irregular addressing using the interleaving applied in FIG. 5 by dividing into 10 scan groups in FIG. 6 (for example, in the case of VGA, each group is composed of 480/10 = 48 scan electrode lines). FIG. 6 shows that the scan group S1 is driven with the subfield sequence 0-4-3-2-1-5, and the respective addressing cycles are 1, 34, 29, 20, 3, and 37, respectively.

If this is applied to a PDP having 480 scan electrode lines, each scan group is made up of 48 electrode lines, and each group is sequentially addressed by itself. Therefore, the actual addressing period is 69 × 48 = 3312, and the ith electrode line of the first group is i, 33 × 69 + i, 28 × 69 + i, 19 × 69 + i, 2 × 69 + i, The gradation bit image data of 0, 4, 3, 2, 1 is addressed in the addressing period of the address period.

According to the irregular addressing method of the present invention, it is possible to minimize the time when the pixels are turned off in the gray level adjustment. As a result, it is possible to reduce the amount of current flowing through the pixels of the driving circuit and the plasma display panel for achieving a constant brightness and to lower the scanning frequency, thereby improving the brightness of the plasma display panel, reducing power consumption, And shows an advantage that the manufacturing of the driving circuit is simplified.

The irregular addressing method of the present invention may be applied to an electro-luminescence display (ELD) and a field emission display (FED) when an active matrix method is applied in addition to a plasma display panel ).

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Therefore, the scope of the present invention is not limited by the above detailed description, but is determined only by the matters described in the claims.

Claims (5)

A display unit including a plurality of pixels for displaying a video signal, a plurality of first electrode lines connected to the plurality of pixels, a plurality of second electrode lines crossing the first electrode lines and connected to the plurality of pixels, And display means for applying a display signal to at least one of the second electrode lines, and control means for controlling an application time of the display signal, the method comprising the steps of: Applying a control signal to the display signal applying means by the control means to maintain a desired pixel in an ON state for a time corresponding to one of a plurality of sub time periods, The display signal is applied to the first electrode line by the display signal applying means in response to the control signal, The time period has a different temporal length proportional to the binary weight of the video signal indicated by the binary value and the display signal is not applied to the pixels already in ON state and the same sub time A display signal corresponding to a different sub-time period is applied to pixels adjacent to each other at the same point in time so that the time during which the pixel is not displayed is reduced and the luminous efficiency Of the display system. The method of claim 1, wherein the predetermined time period is equal to or greater than M x N (M: number of first electrode lines, N: number of bits of gray scale adjustment), which is a minimum time period required for addressing, And a uniform unit time period which is a multiple of a least common multiple of 2 ^N -1, which is the minimum number of periods for display. A display unit including a plurality of pixels for displaying a video signal, a plurality of first electrode lines connected to the plurality of pixels, and a plurality of second electrode lines crossing the first electrode lines and connected to the plurality of pixels, A display signal applying means for applying a display signal to at least one of the first electrode line and the second electrode line and a control means for controlling an application time of the display signal, Applies a control signal to the display signal applying means to hold a desired pixel in an ON state for a time corresponding to one of a plurality of sub time periods included in the cycle, Applies a display signal to the first electrode line in response to the control signal, and the plurality of sub-time periods is a binary value And the display signal has a different temporal length proportional to the binary weight of the visual image signal, and the display signal is not applied to pixels that are already in ON state, And a display signal corresponding to a different sub-time period is applied to the pixels adjacent to each other at the same time point, thereby reducing the time during which the pixel is not displayed, thereby improving the luminous efficiency of the pixels Display system. The method of claim 3, wherein the predetermined time period is equal to or greater than M x N (M: number of first electrode lines, N: number of bits of gray scale adjustment) which is a minimum time period required for addressing, And a unit time period which is a multiple of a least common multiple of 2 ^N -1, which is a minimum number of cycles for displaying the display data. 5. The apparatus according to claim 3 or 4, wherein the control means further comprises storage means for storing an order of application of the control signal when the number of the first electrode lines and the number of bits of the tone adjustment are determined, Is applied in accordance with the application order stored in the storage means.