KR100189742B1 - Level shifter - Google Patents

Abstract

In the present invention, a level shifter is a level shifter that can adjust an output by satisfying timing conditions between two different inputs, and includes a level shifter, a reset part, and a latch part. The level shifter unit generates an output of the boosted voltage level when the first input signal is at the power supply voltage level. The reset unit resets the output of the level shifter unit to the ground level when the second input signal is input, the first input signal is the ground voltage level, and the second input signal is the power supply voltage level. The latch unit maintains the output of the level shifter unit at the boosted voltage level when the first input signal is at the power supply voltage level, and inverts the output of the level shifter unit. The present invention can reduce the layout area of a chip by obtaining a ground voltage Vss or an internally applied voltage Vpp at a desired time without adding a separate logic circuit.

Description

Level shifter

1 is a circuit diagram of a conventional level shifter

2 is an operational waveform diagram of the level shifter shown in FIG.

3 is a circuit diagram of a level shifter according to the present invention.

4 is an operating waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

10: level shifter 20: reset

30: latch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter, and more particularly to a level shifter circuit that can change its output by a second input without adding a special logic circuit when the first input signal is at ground (Vss) level. will be.

In general, a level shifter is a circuit used to generate an output voltage stepped up from a voltage level input from a semiconductor integrated circuit. In particular, semiconductor memories are frequently used in word line drivers and block selection circuits.

Cell transistors of semiconductor memories are designed to have a relatively larger threshold voltage than other normal transistors in order to reduce leakage current. When the cell transistor is turned on, the charge stored in the cell capacitor is loaded on the bit line (or bit bar line) (read operation) or vice versa from the bit line (or bit bar line) to the cell capacitor (write operation). .

At this time, the voltage level of the bit line may not sufficiently increase due to the large threshold voltage of the cell transistor, and thus the sense amplifier may not detect it. In order to solve this problem, the word line is driven by using an internal boost voltage Vpp higher than the power supply voltage Vcc. This problem occurs not only in memory cells but also in many parts of semiconductor memories such as data input / output bus lines.

However, since the internal boost voltage Vpp accumulates and generates charges supplied by the power supply voltage Vcc, it is difficult to supply a large amount of power like the power supply voltage Vcc. Therefore, it is desirable to use as little internal boost voltage (Vpp) as possible to realize low power consumption.

In order to suppress the consumption of the internal boosted voltage Vpp, it is necessary to output the internal boosted voltage Vpp only when necessary, and to suppress the generation and output of the internal boosted voltage Vpp while not necessary. As one means for implementing this, the level shifter shown in FIG. 1 is used.

1 is a conventional level shifter circuit diagram.

A typical level shifter includes first and second inverters INV1 and INV2, first and second NMOS transistors NT1 and NT2, and first and second PMOS transistors PT1 and PT2. .

The source of the first PMOS transistor PT1 and the second PMOS transistor PT2 is connected to the internal boost voltage Vpp. The drain of the first PMOS transistor PT1 is connected in common with the drain of the first NMOS transistor NT1, and the source of the first NMOS transistor NT1 is grounded. The drain of the second PMOS transistor PT2 is connected in common with the drain of the second NMOS transistor NT2, and the source of the second NMOS transistor NT2 is grounded.

In addition, the gate of the first PMOS transistor PT1 is connected to the common drain of the second PMOS transistor PT2 and the second NMOS transistor NT2, and the gate of the second PMOS transistor PT2 is connected to the first PMOS transistor PT2. It is connected to the common drain of the MOS transistor PT1 and the first NMOS transistor NT1.

The input S is directly input to the gate of the first NMOS transistor NT1, and the input S is inverted by the first inverter INV1 to the gate of the second NMOS transistor NT2. In addition, the input of the second inverter INV2 is connected to the common drain of the second PMOS transistor PT2 and the second NMOS transistor NT2 to output an internal boost voltage Vpp or a ground voltage VSS.

2 is an operation waveform diagram of the level shifter shown in FIG. In the ready state, the circuit operation in the time period T1 to T2 is as follows.

When the power supply voltage Vcc is applied to the input S, the first NMOS transistor NT1 is turned on so that the node N1 becomes the ground voltage Vss, and the second NMOS transistor NT2 is connected to the first NMOS transistor NT2. It is turned off by the low level output of inverter INV1. Since the ground voltage Vss of the node N1 turns on the second PMOS transistor PT2, the voltage level of the node N2 becomes the internal boost voltage Vpp to turn the first PMOS transistor PT1. -Turn it off. The internal boost voltage Vpp of the node N2 is inverted to the low level of the ground voltage Vss by the second inverter INV2, which is the output OP.

When the ground voltage Vss is applied to the input S in a period after the time T2, the first NMOS transistor NT1 is turned off and the second NMOS transistor NT2 is turned off at the first inverter INV1. The voltage level of the node N2 becomes the level of the ground voltage Vss by being turned on by the output high level voltage.

The ground voltage Vss of the node N2 turns on the first PMOS transistor PT1 so that the voltage level of the node N1 becomes the level of the internal boost voltage Vpp. As a result, the second PMOS transistor PT2 is turned off to maintain the voltage level of the node N2 at the ground voltage Vss. Since the ground voltage Vss of the node N2 is inverted by the inverter INV2, the voltage level of the output OP becomes the level of the boosted voltage Vpp.

However, such a conventional level shifter is configured to regulate the output with one input. However, in actual wordline driving timing, a predetermined timing margin is required when the wordline is reactivated in an inactive state. This is because the voltage level of the bit line (or bit bar line) needs some time to return to the precharge voltage level. Due to the timing margin at the time of driving the word line, it is necessary to control the activation time and the deactivation time of the word line independently.

At this time, in order to construct a circuit suitable for timing, the output of the level shifter must be controlled by two independent signals. To implement this, it is necessary to add a separate logic circuit for generating two independent signals at the input of the conventional level shifter described above. However, the addition of such a separate logic circuit results in an increase in layout area.

Accordingly, an object of the present invention is to provide a necessary timing margin by controlling a transition point of a voltage level of an output signal using only two different input signals without providing a separate logic circuit.

The present invention for achieving the above object is a level shifter that can adjust the output by satisfying the timing conditions between two different inputs, comprising a level shifter, a reset, a latch.

The level shifter unit generates an output of the boosted voltage level when the first input signal is at the power supply voltage level. The reset unit resets the output of the level shifter to the ground level when the second input signal is input, the first input signal is the ground voltage level, and the second input signal is the power supply voltage level. The latch unit maintains the output of the level shifter unit at the boosted voltage level when the first input signal is at the power supply voltage level, and inverts the output of the level shifter unit.

A preferred embodiment of the present invention as described above will be described with reference to FIG. 3 and FIG. First, FIG. 3 is a circuit diagram of a level shifter according to the present invention, and is largely composed of a level shifter 10, a reset 20, and a latch 30.

In the level shifter unit 10, the first input S is directly input to the gate of the first NMOS transistor NT11. It is also inverted by the inverter INV11 and input to the gate of the second NMOS transistor NT12. An internal boost voltage Vpp is applied to the sources of the first and second PMOS transistors PT11 and PT12, and the drain of the first PMOS transistor PT11 is equal to the drain of the first NMOS transistor NT11. Commonly connected, the source of the first NMOS transistor NT11 is connected to ground.

The drain of the second PMOS transistor PT12 is connected to the drain of the second NMOS transistor NT12 in common, and the source of the second NMOS transistor NT12 is connected to the reset unit 20.

In addition, the gate of the first PMOS transistor PT11 is connected to the common drain of the second PMOS transistor PT12 and the second NMOS transistor NT12, and the gate of the second PMOS transistor PT12 is connected to the first PMOS transistor PT12. It is connected to the common drain of the MOS transistor PT11 and the first NMOS transistor NT11.

The reset unit 20 generates a reset signal at a desired timing, and a second input RESET is applied to the gate of the third NMOS transistor NT13 in order to adjust the output. The source is connected to the source of the second NMOS transistor NT12 of the level shifter unit 10, and the drain is connected to ground.

In order to compensate and invert the output of the level shifter, the latch unit 30 applies an internal boost voltage Vpp to the source of the third PMOS transistor PT13, and outputs the level shifter 10 to the source. The drain of the 3 PMOS transistor PT13 and the input of the second inverter INV12 are commonly connected, and the output of the second inverter INV12 is connected to the gate of the third PMOS transistor to compensate for the output. Signal is output at a boosted voltage (Vpp) or ground (Vss) level.

4 is a waveform diagram of the level shifter according to the present invention of FIG. The operation of the level shifter of the present invention will be described with reference to the operation waveform diagram shown in FIG.

When the first input S is applied to the ground Vss level during the time period T0 to T1, the first NMOS transistor NT11 is turned off and the power supply voltage Vcc is turned on by the first inverter INV1. The second NMOS transistor NT12 is turned on after being inverted to the level. At this time, since the second input RESET is applied at the power supply voltage Vcc level, the third NMOS transistor NT13 is turned on so that the node N12 is at the level of the ground voltage Vss.

The ground voltage Vss of the node N12 turns on the first PMOS transistor PT11, and the node N11 becomes the boost voltage Vpp, thereby turning off the second PMOS transistor PT12. The N12 maintains the ground voltage Vss and is compensated by the third PMOS transistor PT13 so that the internal boosted voltage Vpp level is output to the output terminal OP after passing through the second inverter INV12.

In the time period T1 to T2, a signal having a power supply voltage Vcc level is applied to the first input S, so that the first NMOS transistor NT11 is turned on so that the node N11 has a ground voltage Vss. do. The second NMOS transistor NT12 is turned off due to the voltage inverted to the high level by the first inverter INV11.

The ground voltage Vss of the node N11 turns on the second PMOS transistor PT12 so that the node N12 becomes the level of the boost voltage Vpp. As a result, the first PMOS transistor PT11 is turned off so that the node N11 maintains the level of the ground voltage Vss. The internal boosted voltage Vpp level of the node N12 is compensated by the third PMOS transistor PT13 and then inverted by the second inverter INV12 so that the ground Vss level is output to the output terminal OP.

At the time T2 to T3, the state of the time T1 to T2 section is maintained. The power supply voltage Vcc of the second input RESET does not affect the output when the second NMOS transistor NT12 is turned off.

At times T3 to T4, the first input S is changed to the level of the ground voltage Vss so that the second NMOS transistor NT12 is turned on. For this reason, although the node N12 should be at the level of the ground voltage Vss, the output terminal OP is maintained at the ground Vss level by keeping the previous state by compensation to the third PMOS transistor PT13.

In the period after the time T4, the signal is returned to the ready state, and the third NMOS transistor NT13 is also turned on so that the node N12 is at the ground Vss level. Therefore, the output passes the second inverter INV12 and the boosted voltage Vpp is output to the output terminal OP.

That is, only when the first input signal is at the ground Vss level, the power supply voltage Vcc of the second input RESET may invert the output to adjust the output of the output terminal OP.

4 shows that a predetermined time interval occurs between the time when the first input signal S transitions from the power supply voltage level to the ground voltage level and the time when the second input signal RESET rises to the power supply voltage level. This time interval soon determines the desired timing margin.

When the output OP is viewed, even after the first input signal S transitions to the ground voltage level, the output OP remains at the ground voltage level, and at the time when the second input signal RESET transitions to the power voltage level. It can be seen that the output OP only changes to the power supply voltage level. This time interval is the desired timing margin.

Therefore, in the present invention, only the second input is added to the normal level shifter, and the two input signals alone can sufficiently secure the necessary timing margin by controlling the transition point of the voltage level of the output signal.

Claims (4)

A level shifter, comprising: a level shifter section for generating an output of a boosted voltage level when a first input signal is at a power supply voltage level, a second input signal is input, wherein the first input signal is a ground voltage level and the second input is input; A reset unit for resetting the output of the level shifter unit to the ground level when the signal is at the power supply voltage level, and maintaining the output of the level shifter unit at the boosted voltage level when the first input signal is at the power supply voltage level; And a latch unit for inverting and outputting the output of the level shifter unit. 2. The gate driving circuit of claim 1, wherein the level shifter unit has a first PMOS transistor and a drain supplied with the boost voltage to a source in common with a drain of the first PMOS transistor, and has a source grounded. The boost voltage is supplied to a first NMOS transistor and a source to which a signal is input, a second PMOS transistor to which a voltage of a common drain of the first PMOS transistor and the first transistor transistor is input, and a drain to a gate thereof. A second NMOS transistor connected to a drain of the second PMOS transistor in common to form an output terminal, a source of which is connected to the reset unit, and a gate of which the inverted signal of the first input signal is input; And a first inverter for inverting an input signal and outputting the input signal to the gate of the second NMOS transistor. The level shifter of claim 1, wherein the reset unit comprises a third NMOS transistor having the second input signal input to a gate, a drain thereof connected to a source of the second NMOS transistor, and a source of which is grounded. The third PMOS transistor of claim 1, wherein the latch unit is supplied with the boost voltage and connected to the output of the level shifter, and the output of the level shifter is inverted. A level shifter comprising a second inverter output to the gate of the MOS transistor.