KR0138861B1 - Jpeg standard quantizer inverse quantizer architecture - Google Patents

Abstract

The present invention calculates the inverse of the quantization value in advance and stores it in a separate ROM to convert the division operation into a multiplication operation so that the quantization and inverse quantization can be performed using only one multiplication circuit without a separate divider.

F ^Q (u, v) = integer round [F (u, v) × ¹ / _{q (u, v)} ]... … (Equation 3)

An object of the present invention is to provide a quantization / dequantization circuit of an image compression / restore quantizer.

A characteristic configuration includes an address generator for generating an address for RAM access (write / read) control in raster scanning order by a start signal of block data input together with image data and a 6-bit output of the address generator. A quantization table RAM including four 64 × 8 bit quantization tables created by adding a selection signal for selecting a quantization memory bank to upper bits and an inverse value (1 to 1/2225) of the quantization coefficients of the quantization table RAM A memory circuit section of a ROM, a booth encoding means for outputting a booth coding coefficient using a multiplicand and a multiplier input in the form of a bit string, and a rounding number storage addition means for storing a rounding number for the booth coding coefficient; If the mode of the quantizer is quantization, the result of dividing the standardization coefficient multiplied by the inverse of the quantization value is output in parallel. Consisting of a multiplier circuit part of the adder / barrel shifter means

Description

Quantization / Dequantization Circuit of Image Compression / Restore Quantizer

1 is an internal structural block diagram of a quantization / dequantization circuit according to the present invention.

2 is a block diagram showing a detailed configuration of the memory section of FIG.

3 is a block diagram showing a detailed configuration of the multiplier section of FIG.

* Explanation of symbols for main parts of the drawings

U10: memory circuit section U20: multiplier circuit section

101: address generator 102: RAM

103: ROM 201: Booth encoding means

202: addition means for storing the rounding water

203: Parallel adder / barrel shifter means

301 to 304: flip-flop 401: bit string

402: booth encoder

403: CSA tree for storing rounding numbers

404,405: Predicted adder 406, 410, 411: Multiplexer

407: parallel adder 408: barrel shifter

409: overflow detector

The present invention relates to a quantization circuit for implementing a VLSI (Very Large Scale Inttegration) implementation of a baseline JPEG (Decompression and Decompression) algorithm, and more particularly, to an international image compression / restore standard using a booth multiplier. The present invention relates to a quantization / dequantization circuit of an image compression / restore quantizer capable of performing quantization / inverse quantization (QUANTIZATION / INVERSE QUANTIZATION) required by an instrument (JPEG: JOIN PHOTOGRAPHIC EXPERTS GROUP).

The quantization process in a general quantization circuit can be represented by Equation 1 below.

Intended to quantization in the (formula 1) is rounded to the nearest integer value by dividing the DCT coefficient F (u, v) the quantization interval Q (u, v) by a quantization table, yeokyang magnetization is quantized on the other hand the value F ^q It is equivalent to multiplying (u, v) by the quantization interval Q (u, v) and is equal to (Equation 2).

F ^q (u, v) = F ^q (u, v) x Q (u, v)... … (Equation 2)

However, since the conventional quantization function has a separate multiplier for quantization and a multiplier for inverse quantization, the configuration is complicated and the result of the multiplication is limited to every clock. The acid function could not be implemented at the same time.

The present invention has been made to solve the above problems, and the object of the present invention is to calculate the inverse of the quantization value in advance and store it in a separate ROM to convert the division operation into a multiplication operation. Quantization and inverse quantization

F ^q (u, v) = integer round [F (u, v) x 1 / Q (u, v)]... … (Equation 3)

An object of the present invention is to provide a quantization / dequantization circuit of an image compression / restore quantizer.

A special feature of the quantization / dequantization circuit of the image compression / restore quantizer according to the present invention for achieving the above object is RAM access in raster scanning order by the start signal of block data input together with image data. An address generator for generating an address for (write / read) control and four 64 × 8 bit quantization tables generated by adding a selection signal for selecting a quantization memory bank to the 6-bit output of the address generator as an upper bit. A booth coding coefficient is output using a memory circuit unit in ROM that stores quantization table RAMs and inverse values (1-1 / 225) of the quantization coefficients of the quantization table RAMs, and power and multipliers input in the form of bit strings. Both the booth encoding means, the rounding number storage addition means for storing the rounding number for the booth coding coefficient, and the modes of the quantizer If it as composed of a multiplier circuit in a parallel adder / barrel shifter means that dividing the standardized coefficients multiplied by the inverse of the quantization values back to the result.

Hereinafter, a preferred embodiment of an image compression / restore quantization circuit according to the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a structure of an image compression / restore quantization circuit according to the present invention. As shown in the drawing, the memory circuit unit U10 scans a raster by a start signal of block data input together with image data. An address generator 101 for generating an address for sequential RAM access (write / read) control, and a 64x8 binary code obtained by adding a selection signal for selecting a quantization memory bank to the 6-bit output of the address generator as an upper bit. A quantization table RAM 102 including four bit quantization tables, and a ROM 103 which stores the inverse values (1-1 / 225) of the quantization coefficients of the quantization table RAM. The circuit unit U20 is a booth encoding means (BOOTH RECODER) 201 for outputting a booth coding coefficient using a multiplier and a multiplier input in the form of a bit string, and a rounding number for the booth coding coefficient. A parallel adder / barrel shifter for outputting the result by dividing the CARRY SAVE ADDER 202 for storing and the reference coefficient multiplied by the inverse of the quantization value when the mode of the quantizer is quantization. Means 203.

FIG. 2 is a detailed circuit diagram of the memory circuit unit U10 of FIG. 1 as a block data start signal BS, which is a control signal together with data input from a DCT or a zigzag block in a quantizer in the JPEG algorithm as shown in the drawing. When the BLOCK START is input, the address generator 101 outputs a total of 6 bits from 0 to 1 in increments of 1 per clock, and 2, which is a quantization table selection signal (QBANK), to the 6-bit output signal of the address generator. A quantization table RAM 102 for storing 256x8 bits of data by combining bit data into higher bits, and an inverse value of 1 / Q (u, v) of the quantization coefficient Q (u, v) of the quantization table RAM to be used in the quantization mode. v) a ROM 103 for storing, a plurality of deflip-flops 301, 302, 303, 304 for synchronizing the quantization coefficients Q (u, v), and any of the ROMs. NOR to compute 2-bit output as a negative logic sum This desirability is composed of tree 305. The

3 is a detailed circuit diagram of the multiplier circuit unit U20 of FIG. 1, and as shown in the figure, the booth encoding means 201 is a multiplicand A and a multiplier B inputted in the form of a 12-bit bit string 401. It is preferable to constitute a booth encoder 402 for outputting the booth coding coefficients (Y1 ~ Y11) using, and the rounding number storage virtual means 202 is rounded up to the booth coding coefficients (Y1 ~ Y11) A rounding number storage adder 403 for storing a number, a rounded-up number adder 404, 405 for reflecting the rounding or rounding number of the rounding number storage adder in the operation of the parallel adder; Preferably, the multiple adders 410, 411, and 406 for synthesizing the output of the adder for rounding number storage, and the parallel adder / barrel shifter means 203 are the multiplexers 410 and 411. ) As the sum of Carry and Sum, and the other multiplexer 406 The parallel adder 407 using the output of the rounding number c, and the least significant bit at the output of the parallel adder to an arbitrary reference coefficient (Scale) multiplied by the inverse of the quantization value when the mode of the quantizer is quantization. It is preferable to configure a barrel shifter 408 for comparing a value discarded and an overflow detector 409 for detecting an overflow of the barrel shifter and outputting an error signal ERROR and a result signal RESULT. .

The operation of the quantization / dequantization circuit of the image compression decompression quantizer according to the present invention will be described in detail with reference to the configuration as described above.

First, in the JPEG algorithm, a block data start signal (BS: BLOCK START), which is a control signal, is input to the address generator 101 together with data input from a DCT or a zigzag block in the quantizer.

When the block data start signal BS is input, the address generator 101, which is designed as a 6-bit counter, increases from 0 to 1 per clock and outputs up to 63.

The quantization table memory selection signal QBANK, that is, the 2-bit signal, is added to the 6-bit high order MSB output from the counter which is the address generator, so that all 8 bits are the address of the RAM 102 which is the quantization table. .

The quantization coefficient Q (u, v) thus obtained is stored in the flip-flop 301 and then inputted to the address of the ROM 103 for obtaining the inverse value of Q (u, v) to be used in the quantization mode. The Q (u, v) value to be used in the mode is traced back to the next flip-flop 302 to synchronize with the ROM.

The value stored in the ROM is a 13-bit integer value whose integer value P (u, v) is given by Equation 4 below.

(Equation 5) shows the scale value and the range of use used in the present invention, it can be expressed as (Equation 6) below when (Equation 4) is applied to (Equation 3).

In the present invention, as shown in Equation 6, 1 / Q (u, v) is multiplied by 2 ^B and then the result of multiplying it by the reference coefficient value is stored in the ROM, 1 / Q without scaling. For error-free multiplication results for (u, v), 20 bits are required instead of 13 bits, to solve problems such as hardware increase and circuit delay speed in constructing a multiplication circuit for a 20-bit multiplier.

Thus, the value obtained by (4) is data having 13 bits of valid bits, and 256x13 bits of ROM are required to store these values.

However, in the present invention, the most significant bit (MSB), i.e., P (12), of the standardized coefficient P (u, v) always has a value of '1' when P (11) and P (10) are '0'. Since P (11) and P (10) can be obtained P (12) through the NOR gate 305 operation, the data width of the ROM for P (u, v) is reduced by 1 bit as shown in FIG. It can be reduced to 12 bits.

The quantization coefficients Q (u, v) obtained in the quantization table 102 are stored in the next flip-flop 303 to be the input of the multiplier in the inverse quantization mode, and the output P (11: 0) of the ROM 103 is In the quantization mode together with the most significant bit P 12 obtained by the NOR gate 305 operations of P 11 and P 10, it is stored in the next flip-flop 304 to become an input of a multiplier.

The multiplier circuit part of the present invention uses a booth method multiplication (BOOTH METHOD MULTIPLIER) algorithm consisting of a booth encoder 402, a CARRY SAVE ADDER tree 403, and a parallel adder 407.

(Please refer to H. DAM and A. GUPTA, A General Multibit Recoding of Two's complement Binary numbers abd its proof with application in Multiplier Implementation, IEEE Transactions on Computers, vol. 39. No 8, pp 1006 ~ 1015, August 1990).

The multiplicators A and multipliers B of the multiplier circuit part input DCT coefficients F (u, v) and q (7: 0) when the mode of the quantizer is quantization, and in case of inverse quantization, the quantized value FQ ( u, v) and P (12: 0) are input.

The multiplicand A is 11 bits of data, and the multiplier B is 13 bits of data as shown in Equation 7 below.

The multiplier A input to the multiplier circuit part is divided into six three-bit booth encoders 402 in the form of a bit string 401 of FIG. 3 according to the booth algorithm, and one three-bit booth encoders Y1 to Y11. Outputs the booth coding coefficient Y by inputting the three bits of the multiplier A and the multiplier B, Y having one of B or 2B, -B, 2B, 0, and the six booths The coding coefficient Y is input to the CSA tree 403 composed of four rounding factor storage adders.

As shown in FIG. 3, 22 pairs of outputs of the CSA tree 403 are output, and are represented as T (21: 0) in the following description.

The output T of the CSA tree 403 is an input of the parallel adder 407 and its shape is determined according to the mode of the quantizer. The inputs of the parallel adder are SUM (12: 0), CARRY (12: 0), and C ( CARRY).

If the mode of the quantizer is quantization, SUM and CARRY have the corresponding value of T (21: 9), and T (8: 4) is added to the CARRY LOOKAHEAD ADDER 404 for rounding off. The rounded number is reflected in the calculation of the parallel adder 407.

The reason for dropping the lower 9 bits of T and adding the bit value of 21: 9 to the sum and round number is the process of redistributing 1 / Q (u, v) multiplied by 2 ^B in Equation 4. This process is equivalent to dividing the result T by 2 ^12, and dividing by the remaining 2 discards the least significant bit (LSB) of the result 13 bits of the parallel adder 407 and uses the remaining 12 bits as inputs to the barrel shifter 408. It takes place in the process.

If the mode of the quantizer is inverse quantization, SUM and CARRY have a corresponding value of T (14: 2), and the result is rounded by inputting T (1: 0) into the predictor-adder 405 for rounding off. The reason for reflecting the number in the parallel adder operation and discarding the lower two bits of T in SUM and CARRY and giving the bit value of 14: 2 is 5 bit left when entering q (7: 0) into multiplier B in Equation 7. To redistribute the shift or multiplication by 2 ⁵ , this process is equivalent to dividing by 2 ⁴ and dividing by the remaining 2 discards the LSB of the 13 bits resulting from the parallel adder 407 and the remaining 12 bits of the barrel shifter 408. This is done in the process of input.

The barrel shifter 408 is a process of dividing the reference coefficient multiplied by 1 / Q (u, v) when P (u, v) is obtained in Equation 4 when the mode of the quantizer is quantization. If 4, 16, 64, the input value is shifted to the right by 0, 2, 4, 6 respectively.

When the mode of the quantizer is inverse quantization, the barrel shifter 408 outputs the same value as the input value, so the output value of the multiplier circuit part is finally output through the overflow detector 409 as a result of the quantizer. 409) checks whether the output value of the multiplier is within the range of -1023 to +1023 in the quantization mode and -1024 to +1023 in the inverse quantization mode. If an overflow occurs, an error signal is generated.

As described above, according to the quantization / dequantization circuit of the image compression restoring quantizer according to the present invention, the inverse of the quantization value is calculated in advance and stored in a separate ROM so that the division operation is converted into a multiplication operation without a separate divider. It is useful to enable quantization and inverse quantization with only a multiplication circuit.

Claims (6)

The start signal of the block data input together with the image data generates an address for RAM access control in the raster scan order, and a selection signal for selection of a quantized memory bank is provided to the generated 6-bit output. A memory circuit unit for storing a quantization coefficient in a 64 × 8 bit quantization table added by higher bits and storing an inverse value (1-1 / 225) of the quantization coefficient of the quantization table; A multiplier circuit that outputs a booth coding coefficient using a multiplier, stores roundings for the sub-coding coefficients, and outputs a result by dividing the reference coefficient multiplied by the inverse of the quantization value when the mode of the quantizer is quantization And a quantization / inverse quantization circuit of an image compression / restore quantizer. The address generator of claim 1, wherein the memory circuit unit U10 generates an address for controlling RAM access (write / read) in a raster scan order by a start signal of block data input together with image data. 101), a quantization table RAM 102 including four true 64x8 bit quantization tables formed by adding a selection signal for selecting a quantization memory bank to a six-bit output of the address generator as an upper bit, and the quantization 10. A quantization / dequantization circuit of an image compression / restore quantizer, characterized in that it comprises a ROM (103) which stores inverse values (1-1 / 225) of quantization coefficients of a table RAM. 2. The multiplier circuit unit U20 of claim 1, further comprising: a booth encoding unit 201 for outputting a Sousse coding coefficient using a multiplier and a multiplier input in the form of a bit string, and a rounding number for the booth coding coefficient. A rounding adder 202 and a parallel adder / barrel shifter means 203 for dividing the reference coefficient multiplied by the inverse of the quantization value and outputting the result if the mode of the quantizer is quantization. A quantization / dequantization circuit of an image compression / restore quantizer. 4. The booth encoder of claim 3, wherein the booth encoder 201 outputs the booth encoders Y1 to Y11 by using a multiplicand A and a multiplier B input in the form of a 12-bit bit string 401. And a quantization / dequantization circuit of an image compression / restore quantizer. 4. The rounding number storage adding means 202 is a rounding number storage adding means 403 for storing rounding numbers for the booth encoders Y1 to Y11, and the rounding number storing adder. Selects the output signals of the rounding number adders 404 and 405 and the rounding number storage adder 403 according to the quantization / dequantization mode to reflect the rounding or rounding of The multiplexer 410 for providing the input of the rounding number of the parallel adder 407 and the output signal of the rounding number storage adder 403 according to the quantization / dequantization mode are selected and the parallel adder ( The multiplexer 411 for providing the sum of the sums 403 and the output signal of the rounding number storage adder 403 according to the quantization / dequantization mode are selected to round up the number of rounds (403). multiplex to provide as input of c) Video compression / decompression quantizer quantizing / inverse quantizing circuit of which is characterized by consists of 406. 4. The parallel adder / barrel shifter means (203) uses the outputs of the two multiplexers (410, 411) as the sum and the sum of the other multiplexers (406). The parallel adder 407 using the output as the rounding number (c), and if the mode of the quantizer is quantization, an arbitrary reference coefficient multiplied by the inverse of the quantization value is discarded from the output of the parallel adder. A quantization of image compression / restoration quantizer comprising a barrel shifter 408 for comparing values and an overflow detector 409 for detecting an overflow of the barrel shifter and outputting an error signal and a result signal. Inverse quantization circuit.