KR0173211B1 - Fault and interrupt processing apparatus in duplicating the control system of atm exchanger - Google Patents

Abstract

The present invention collects system-level faults occurring in each device of an ATM switching system using a SuperSPARC processor and CPU errors already allocated to the NMI of a SuperSPARC interrupt handler as NMI sources and stores them in an internal register, The present invention has been made to solve the above-mentioned problems occurring in the prior art.

It is another object of the present invention to provide a fail-over device separately from the interrupt match device in order to overcome a system level failure.

To this end, the present invention delays the reset for a threshold time period in order to transmit data that could not be transferred from the activation system to the inactivation system. Also, the present invention controls the on / off state of the bus transceiver device of the high-speed data transfer channel so that the contents of the memory between the activation system and the deactivation system coincide with each other, and prevents the fault occurring in the abnormal system from affecting the normal system.

Description

Asynchronous Transfer Mode Switches for fault handling and interrupt handling in duplicating control systems

FIG. 1 is an internal block diagram of an interrupt processing device and a fail-over device for overcoming a system failure in duplication of an ATM switch control system.

FIG. 2 is a block diagram of a board herniation signal (off_bd) generation unit; FIG.

FIG. 3 is a block diagram of a remote system fault signal (r_fail) generation unit.

DESCRIPTION OF THE REFERENCE NUMERALS

1: fault mask part 2: fault collecting part

3: ISR unit 4: NMI signal generation unit

5: bus sensing unit 6: clock distributor

7: reset delay unit 8: channel control unit

9: Transceiver control section

The present invention relates to an apparatus for overcoming a failure occurring at a system level when a fault tolerant system is configured using a duplication scheme in an ATM exchange control system using a SuperSPARC processor.

The most important consideration in constructing a fault tolerant system using redundancy is that, in the event of a system-level emergency failure such as a power failure or a malfunction, It is most important to configure the system as if it did not cause any obstacle to the operation of the entire system.

In the present invention, when a system-level fault occurs, the fault can be overcome through the interrupt matching device and the fail-over device. Since a failure occurring in a redundant device is an urgent system failure such as a power failure or a malfunction, it is required to be notified to a processor as soon as a failure occurs. In order to overcome this failure in interrupt form, priority must be interrupted, Level non-maskable interrupt (NMI).

SuperSPARC commercial interrupts are allocated to overcome NMI errors that have already occurred in the CPU, so that it is impossible to directly match many system faults with SuperSPARC interrupt processors.

Accordingly, the present invention collects system-level faults that may occur in each device of the ATM switch control system using the SuperSPARC processor and CPU errors already assigned to the NMI of the SuperSPARC interrupt handler as NMI sources and stores them in the internal registers The present invention has been made in view of the above problems, and it is an object of the present invention to provide an interrupt matching apparatus capable of overcoming a system failure by generating an interrupt.

It is another object of the present invention to provide a fail-over device separately from the interrupt match device in order to overcome a system level failure.

In order to achieve the above object, the present invention provides an interrupt matching apparatus which, when an address strobe signal (as) from a local bus is generated, decodes an address from the local bus and then accesses an Interrupt Source Register (ISR) And outputs a signal for accessing the fault mask register by decoding the address if the read / write signal r / w is detected during the local bus monitoring, a bus monitoring unit for generating a signal mask_acc for changing a mask value and a mask_wr for changing a mask value, an internal register value changing unit for changing an internal register value to a value of data generated on the local bus and generating an effective response signal, A fault mask unit for outputting a mask signal according to a signal for accessing and changing an internal register value, And a processor for storing an interrupt source signal from the fault collection unit and for receiving a signal for reading an interrupt source value from the bus detection unit, An ISR unit for notifying the NMI source of the value of the internal register (ISR) to the local bus through a data line, generating an effective response signal and outputting the NMI source, To the processor interrupt processing unit of the processor interrupt processing unit.

In addition, the present invention provides a fail-over apparatus comprising: a clock distributor for receiving a clock used as a local bus clock of a processor and outputting a divided clock; a clock distributor for synchronizing a clock output from the clock distributor, A reset delay unit for receiving a signal level of the reset signal man_rst and outputting a signal rst for driving an internal counter to notify of occurrence of a reset, A channel controller for outputting a signal for determining a direction of a high-speed data transmission channel when the system senses occurrence of activation / deactivation; and a control unit for receiving a channel control related signal output from the channel control unit and determining a high- And a transceiver control unit provided to the bus transceiver.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an interrupt matching device and a fail-over device for overcoming a system failure occurring in an ATM switch control system redundancy device using a SuperSPARC processor.

As shown in the figure, an interrupt matching apparatus according to the present invention includes a fault mask unit 1, a fault collecting unit 2, an ISR unit 3, an NMI signal generating unit 4, and a bus monitoring unit 5 And includes a clock divider 6, a reset delay unit 7, a channel control unit 8, and a transceiver control unit 9.

If another fault occurs while one fault occurs and the fault is handled, the fault mask unit 1 prevents an interrupt caused by another fault until the interrupt service of the fault occurred is solved. If multiple failures occur at the same time, the processor will fail to determine failover priority and the system will crash. The SuperSPARC interrupt handler notifies the processor that an interrupt has occurred via the interrupt line ir1 [3: 0]. If the value of the interrupt line ir1 [3: 0] is received as F, the processor detects that an NMI has occurred. The processor generates an address corresponding to the ISR to identify the source of the NMI. At this time, the processor changes the signal level of the read / write signal r / w to H and changes the signal level of the address strobe signal as to H. If the signal level of the read / write signal r / w is H, it is used as a read signal. If the signal level is L, it is used as a write signal. The above behavior is that the SuperSPARC processor detects the NMI from the SuperSPARC interrupt handler and generates it on the local bus to verify the NMI source.

If the signal level of the address strobe signal as is H, the bus monitoring unit 5 changes the signal level of the signal isr_acc for reading the ISR value to H if the address is an address for accessing the Interrupt Source Register (ISR) after decoding the address .

The ISR register is a Read-Only register. The ISR 3 receiving the signal level of isr_acc H informs the processor of the value of ISR via the data line to the local bus and informs the NMI source of the valid response signal . The processor that receives the value of the ISR unit 3, before receiving the interrupt service, stops the interrupt service before the current interrupt service is terminated. The value of " The processor generates an address for changing the internal register value of the failure mask section 1, changes the signal level of the address strobe signal as to H, and changes the signal level of the read / write signal r / w to L.

When the signal monitoring unit 5 detects the signal level during the monitoring of the local bus, the signal level of the signal mask_acc for decoding the address and for accessing the internal register of the fault mask unit 1 is set to H, the value of the internal register of the fault mask unit The signal level of the signal mask_wr for changing the signal level is changed to H level. The fault mask unit 1 receiving this signal changes the internal register value of the fault mask unit 1 to the value of data generated on the local bus and generates a valid response signal. The fault mask unit 1 which changed the internal register value changes the value of the mask signal mask [7: 0].

There are seven kinds of faults that can occur in the duplication device of the ATM exchange control system.

The buf_ful signal is a buffer pool full from the buffer device. Until this situation is cleared, the duplication device can not store the data generated in the active system in the buffer device, thus losing the corresponding data at that moment. As a result, It is difficult to maintain the memory contents between the two.

power_fail occurs when power failure occurs in each system and it is difficult to maintain the function of the system any more.

timeout is a signal to consider that the system has failed because the processor has not initialized the location dock timer periodically.

When Xerr signal is transmitted from the active system to the inactive system through the high-speed data transmission channel, which is a redundant data transmission path, when the ATM switch control system using the SuperSPARC processor is implemented as a redundant system, a data writing error, a timeout ≪ / RTI > is received from the deactivation system.

The r_fail_in signal is a signal notified when a failure occurs in the other system.

Off_bd is a signal for checking whether or not the other party's system is herniated. The Off_bd signal generator is shown in FIG.

man_rst is a signal generated when a manual reset occurs.

The SuperSPARC interrupt processing device has already used the CPU error signal aerr as an NMI, so that it can not deal with faults occurring in the duplication device. Even if the NMI is not assigned to the CPU error signal aerr, the SuperSPARC interrupt device has only one NMI, which limits the number of failures occurring at the system level. In order to solve this problem, the present invention collects the CPU error signal a rr together with the system fault signals at the fault collecting unit 2. The signal level of the active state of buf_fel, power_fail, aerr, xerr, r_fail_in, off_bd, man_rst, and timeout is H. The interrupt mask section that receives the signal level of this signal at H always stores only one fault in the ISR value by the mask signal mask [7: 0] of the mask register. The interrupt mask unit changes the corresponding signal level of int_aerr, int_buf, int_pwr_fail, int_time_out, int_xerr, int_rfail, int_off_bd, int_man_rst corresponding to each fault NMI to store the NMI source in the ISR and stores the signal int_wr To the H level.

The ISR unit 3 maintains the value of the ISR until the processor receives the signal level of the signal isr_acc for reading the value of the interrupt from the bus monitoring unit 5 by H. Since only one NMI line is allocated to the SuperSPARC interrupt processing apparatus, the ISR unit 3 storing the source of the NMI changes the signal level of the corresponding NMI line of irq [7: 0] to indicate that the NMI has occurred And notifies the NMI signal generation unit 4 that an NMI has occurred. If the value of irq [7: 0] is not 0, the NMI signal generation unit 4 changes the signal level of the NMI to H to inform the SuperSPARC interrupt processing apparatus of the occurrence of the NMI. The NMI signal changed to H keeps the signal level until irq [7: 0] becomes 0. The SuperSPARC interrupt handler that receives the NMI signal level H changes the value of the interrupt level irl [3: 0] to F to inform the processor that an NMI has occurred.

In the meantime, in the present invention, in order to prevent fault propagation through channel control when a reset occurs or a fault occurs, a device for overcoming a fault has been invented.

The reset delay unit 7 of the fail-over unit may perform a manual reset for the SuperSPARC if the system is deadlocked and the failure can not be overcome by key input or any other method, If a reset occurs in the system at the moment of pressing the manual reset switch, the contents of the memory between the activation system and the inactive system of the high-speed data transfer device, which is one of the duplication devices of the ATM exchange control system, The loss of data stored in the buffer in the concurrent channel does not maintain the identity of the memory contents between the active and inactive systems. This can not implement the concurrent write method applied in the ATM switch control system redundant device, and as a result, the redundant device can not be used as a fault tolerant system.

The Concurrent Write method is a method for maintaining the contents of the memory at the same time in constructing a fault tolerant system so that other system can inherit the system function if a failure occurs in the system performing the system function.

The clock divider 6 receives the 40 MHz clock used as the MBus clock, which is the local bus of the SuperSPARC processor, and divides the clock into 8.2 uS. The clock dly-clk divided by 8.2uS is used as the clock of the reset delay unit 7. [ The reset delay unit 7 drives the internal counter when receiving the signal level of the manual reset signal man_rst from the reset control unit in synchronization with the clock divided by 8.2 uS in the clock divider 6. The time required for the main processor to write an external cache of 1 Mbyte into its own memory is 10.6 ms. After receiving the signal level of man_rst by H, the reset delay unit 7 informs the reset control unit that a reset has occurred after about 1300 dly-clk in order to notify the reset logic that a reset has occurred after 10.6 ms The signal level of the signal (rst) for changing the signal level (rst) must be changed to H, but it takes at least several hundreds ms for the user to turn on / off the manual reset switch. When the reset delay unit 7 reaches the threshold value of dly-clk capable of removing noise that can be generated by the reset switch, the reset delay unit 7 outputs the signal level rst of the reset signal to the reset logic, Is changed to H.

The contents of the active system cache not reflected in the memory of the deactivation system is transmitted by the above-mentioned interrupt logic while performing the operation in the reset delay unit 7. [

The channel control unit 8 is for determining a high-speed data transmission channel direction when a failure occurs in the system and the high-speed data transmission channel is disconnected or when the system is activated / deactivated. The channel control unit 8 receives a signal Xerr indicating that an error has occurred during data transmission from the system, a signal r_fail_in indicating that a failure has occurred in the partner system, a signal off_bd indicating that the partner board has been hung up, a signal man_rst indicating that a manual reset has occurred in the own system It is necessary to disconnect the channel in order to prevent malfunctioning of the normal system due to a fault occurring in the other party or the own system. In this case, the channel control unit 8 changes the signal channel disconnection signal level for disconnecting the channel to H. In a redundant system of an ATM exchange control system using a SuperSPARC processor, there is always only one activation system that performs a system function. When the signal activation (act) and inactive (stby) signals for determining the system mode are simultaneously received by H or L, the channel negotiation is erroneously performed or the channel negotiation is not completed. In this case also, the channel control unit 8 changes the signal channel disconnection signal level for disconnecting the channel to H.

If your system determines the activation system, it will receive the signal level of act as H. the channel controller 8 changes the signal level of the signal channel_act for changing the direction of the high-speed data transmission channel to the active mode to H. If the system is determined to be inactive, the signal level of stby is received as H. The channel controller 8 receiving the signal level stby and the signal level H changes the signal level of the signal channel_stby for changing the high-speed data transmission channel direction to the inactive mode to H.

The bus transceiver control unit 9 is a part for determining the state of the high-speed data transmission channel. The bus transceiver control unit 9 changes the signal level of the signal EN * for disconnecting the high-speed data transmission channel to H if the channel disconnection signal level is H from the channel control unit 8. [ The bus transceiver receiving this signal changes its state to tri-state. In the present invention, a bus transceiver is implemented using 74FCT16245. The bus transceiver control unit 9 changes the signal level of EN * to L to change the direction of the high-speed data transmission channel to the active mode if the signal level of the channel_act is received from the channel control unit 8 by H, The value of the signal DR changes the signal level in accordance with the signal. If the signal A is used as an output in the active system, change the signal level of DR to L. The bus transceiver control unit 9 changes the signal level of EN * to L to change the direction of the high-speed data transmission channel to the inactive mode if the signal level of the channel_stby is received from the channel control unit 9 by H, The value of the signal DR to be determined changes the signal level to match the signal.

FIG. 2 is a block diagram of a circuit for generating a board hernal signal.

The A pin and the B pin between the A system and the B system are crossed on the back board. The B pin is directly connected to the ground on each board, and the A pin is pulled up through a resistor. When both the A system and the B system are mounted on the back board, the board hernal signal off_bd in the A system and the B system receives the L value which is the signal level received through the B pin of the mutual system. If the B system is herniated, the B pin of the B system is floated, and the hernation signal level of the hernation signal off_bd of the A system is changed to H, thereby detecting that the board of the B system is herniated. When the signal level of off_bd is received as H, the failure is overcome in the same manner as shown in Fig.

FIG. 3 is a block diagram of a signal R_fail signal generator for notifying a failure of another system when a remote system fails;

The R_fail signal generator collects all the faults in the system. If the signal level of one of the signals ar, power_fail, xerr, timeout, man_rst and buf_ful related to the failure is changed to H in the system A, the signal level of the remote system failure output signal r_fail_out is changed to H. In this case, since the remote fault output signal r_fail_out is a signal to inform the B system that the A system has failed, the A system does not check the signal level of r_fail_out. The signal r_fail_out of the system A whose signal level is changed to H is input to the remote fault signal r_fail_in of the system B through the backboard. The B system receiving the signal level of r_fail_in from the A system as H is input to the interrupt mask unit as shown in FIG. 1, and notifies the processor that the A system has failed in the form of an interrupt.

Thus, the present invention configured to operate as described above is configured to delay the reset for a threshold time to transmit data that is not transferred from the activation system to the inactivation system, and to cause the memory contents between the activation system and the inactivation system to coincide The on / off control of the bus transceiver device of the high-speed data transfer channel is controlled, thereby preventing the fault occurring in the abnormal system from affecting the normal system.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventive concept as defined by the appended claims and their equivalents. It is not limited.

Claims (3)

When the address strobe signal as from the local bus is generated, the address isr_acc for reading the value of the ISR is set to HIGH if the address is an address for accessing the Interrupt Source Register (ISR) after decoding the address from the local bus. A signal mask_acc for accessing the fault mask register and a signal mask_wr for changing the mask value when the read / write signal r / w is sensed during the local bus monitoring, A bus monitoring unit 5 for generating an effective response signal by changing the internal register value to the value of data generated on the local bus and generating an effective response signal for accessing and changing the internal register value from the bus sensing unit 5 (1) for outputting a mask signal in accordance with a signal, and a failure signal generation unit (2) for receiving an interrupt source signal from the bus sense unit (5) and for receiving an interrupt source signal from the interrupt sense unit (5) An ISR unit 3 for notifying the NMI source of the value of the internal register ISR to the local bus through the data line, generating an effective response signal and outputting the NMI source, And an NMI signal generation unit (4) for outputting to the external processor interrupt processing apparatus that an NMI source of the NMI source has been generated. A clock divider 6 for receiving a clock used as a local bus clock of the processor and outputting a divided clock; and a clock generator 6 for receiving a manual reset signal man_rst A reset delay unit 7 for driving the internal counter to output a signal rst for informing the occurrence of a reset, and a high-speed data transmission channel A channel control unit 8 for outputting a signal for determining a direction of a high-speed data transmission channel when the activation / deactivation of the high-speed data transmission channel is detected, and a control unit 8 for receiving a channel control related signal output from the channel control unit 8, And a transceiver control unit (9) for providing a signal to the bus transceiver Failure of the system. 3. The system of claim 2, wherein the channel controller (8) comprises: a signal that an error has occurred during data transmission from the system; a signal that a failure has occurred in the counterpart system; a signal that the counterpart board has failed; A channel disconnection signal for preventing a normal system from malfunctioning due to a failure occurring in the other party or its own system is output and an active signal and a deactivation signal for determining a redundant system mode and outputs a signal for changing the direction of the high-speed data transmission channel to the active mode and the inactivation mode according to the generation of the stby signal, and outputs a channel disconnection signal when the act and stby signals occur at the same time Wherein the redundant ATM switching system comprises: