KR0171945B1 - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR0171945B1 KR0171945B1 KR1019950032741A KR19950032741A KR0171945B1 KR 0171945 B1 KR0171945 B1 KR 0171945B1 KR 1019950032741 A KR1019950032741 A KR 1019950032741A KR 19950032741 A KR19950032741 A KR 19950032741A KR 0171945 B1 KR0171945 B1 KR 0171945B1
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- metal wiring
- semiconductor device
- forming
- material layer
- unevenness
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- H10P50/71—
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- H10P50/267—
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- H10P70/273—
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 하부절연층이 형성된 반도체기판 상부에 요철을 형성하고, 그 상부에 금속배선 물질층을 형성한 다음, 금속배선마스크를 이용한 건식식각공정으로 상기 금속배선 물질층과 요철을 순차적으로 식각하여 패터닝하고 이 때 발생되는 식각잔류물을 습식방법으로 제거한 다음, 세척 및 건조공정을 실시하여 반도체기판과 금속배선의 접착력이 향상된 금속배선을 형성함으로써 금속배선의 손상을 방지하고, 후속공정을 용이하게 하여 반도체소자의 수율 및 생산성을 향상시키고, 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and to form an unevenness on an upper surface of the semiconductor substrate on which the lower insulating layer is formed, and to form a metal wiring material layer thereon, and then by the dry etching process using a metal wiring mask. The metal wiring material layer and unevenness are sequentially etched and patterned, and the etching residues generated at this time are removed by a wet method, followed by a washing and drying process to form a metal wiring with improved adhesion between the semiconductor substrate and the metal wiring. It is a technology that prevents the damage, and facilitates the subsequent process to improve the yield and productivity of the semiconductor device, thereby enabling high integration of the semiconductor device.
Description
제1a도 및 제1b도는 종래기술에 따른 반도체소자의 금속배선 형성 방법을 도시한 단면도.1A and 1B are cross-sectional views showing a method for forming metal wirings of a semiconductor device according to the prior art.
제2a도 및 제2b도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.2A and 2B are cross-sectional views illustrating a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,12 : 반도체기판 13 : 요철11,12: semiconductor substrate 13: unevenness
15,23 : 금속배선물질층 17 : 감광막패턴15,23: metal wiring material layer 17: photoresist pattern
19,27 : 금속배선 25 : 식각잔류물19,27: Metal wiring 25: Etch residue
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 반도체소자가 고집적화됨에 따라 에스펙트비(aspect ratio)가 높은 금속배선을 형성하는 공정 중 금속배선의 무너짐 현상을 방지하기 위한 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a technique for preventing a metal wiring from collapsing during a process of forming a metal wiring having a high aspect ratio as the semiconductor device becomes highly integrated. .
종래 기술에는 하부 절연층이 형성된 반도체기판 상부에 금속배선 재료를 형성하고, 금속배선마스크를 이용한 식각 공정으로 상기 금속배선을 식각하여 금속배선을 형성하였다.In the related art, a metal wiring material is formed on a semiconductor substrate on which a lower insulating layer is formed, and the metal wiring is etched by an etching process using a metal wiring mask to form metal wiring.
제1a도 및 제1b도는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.
제1a도를 참조하면, 하부절연층(도시안됨)이 형성된 반도체기판(21) 상부에 금속배선(23)을 형성한다.Referring to FIG. 1A, the metal wiring 23 is formed on the semiconductor substrate 21 on which the lower insulating layer (not shown) is formed.
이 때, 상기 금속배선(23)은 상기 반도체기판(21) 상부에 금속배선 물질층을 형성하고, 이를 금속배선마스크(도시안됨)를 이용한 식각공정으로 식각하여 금속배선(23)을 형성한다.In this case, the metal wiring 23 forms a metal wiring material layer on the semiconductor substrate 21, and the metal wiring 23 is etched by an etching process using a metal wiring mask (not shown) to form the metal wiring 23.
그러나, 고집적화된 반도체소자의 높은 에스펙트비로 인하여 상기 금속배선(23)의 하측에 패터닝되지않은 금속배선 물질층의 잔류물(25)이 남을 수 있다.However, due to the high aspect ratio of the highly integrated semiconductor device, a residue 25 of the unpatterned layer of metallization material may remain under the metallization 23.
제1b도를 참조하면, 습식방법으로 상기 잔류물(25)을 제거하고, 세척한 다음, 건조기에서 말려 완성된 금속배선(27)을 형성하였다. 이 때, 상기 세척공정은 증류수를 이용하여 실시한다.Referring to FIG. 1B, the residue 25 was removed by a wet method, washed, and then dried in a dryer to form a completed metal wiring 27. At this time, the washing step is carried out using distilled water.
그러나, 상기 완성된 금속배선(27)은 하부절연층과의 접착력이 낮아 습식식각공정시 발생되는 모세관현상에 의하여 금속배선(27)이 넘어지는 현상이 발생한다.However, the completed metal wiring 27 has a low adhesive strength with the lower insulating layer, which causes the metal wiring 27 to fall down due to capillary phenomenon generated during the wet etching process.
상기한 바와같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 금속배선이 하부절연층과의 접착력이 낮아 습식식각공정시 모세관 현상으로 인하여 패턴이 무너지는 현상이 유발되고, 이로인하여 후속공정을 실시할 수 없도록 하여 반도체소자의 생산성 및 수율을 저하시키는 문제점이 있다.As described above, in the method of forming the metal wiring of the semiconductor device according to the prior art, the metal wiring has a low adhesive strength with the lower insulating layer, causing the pattern to collapse due to the capillary phenomenon during the wet etching process. There is a problem in that the productivity and yield of the semiconductor device can be reduced by making it impossible to implement.
따라서, 본 발명은 종래기술의 문제점을 해결하기 위하여, 하부절연층 상부에 요철형상을 형성하고 그 상부에 금속배선을 형성함으로써 금속배선과 하부절연층의 접착력을 향상시켜 높은 에스펙트비를 갖는 고집적화된 반도체소자의 금속배선을 용이하게 형성할 수 있도록 하여 반도체소자의 생산성 및 수율을 향상시킬 수 있는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the problems of the related art, the present invention improves the adhesion between the metal wiring and the lower insulating layer by forming an uneven shape on the lower insulating layer and forming a metal wiring thereon, thereby achieving high integration with high aspect ratio. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device that can easily form a metal wiring of the semiconductor device to improve the productivity and yield of the semiconductor device.
이상의 목적을 달성하기 위한 본 발명인 반도체소자의 금속배선 형성방법은, 하부절연층이 형성된 반도체기판 상부에 요철을 형성하되, 실리콘을 함유하는 알루미늄합금을 증착하고 습식방법으로 상기 알루미늄합금을 제거하여 실리콘으로 형성하는 공정과, 전체표면 상부에 금속배선 물질층을 형성하는 공정과, 금속배선 마스크를 이용한 플라즈마 건식방법으로 상기 금속배선 물질층과 요철을 순차적으로 식각하여 금속배선 물질층 패턴과 요철 패턴을 형성하는 공정과, 상기 금속배선 물질층 패턴과 요철 패턴 사이의 식각잔류물을 습식방법으로 제거하고 세척 및 건조함으로써 금속배선을 형성하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention includes forming irregularities on an upper surface of a semiconductor substrate on which a lower insulating layer is formed, depositing an aluminum alloy containing silicon, and removing the aluminum alloy by a wet method. The metal wiring material layer and the concave-convex pattern by sequentially etching the metal wiring material layer and the concave-convex pattern by the forming process, forming the metal wiring material layer on the entire surface, and plasma dry method using the metal wiring mask. And forming a metal wiring by removing the etch residue between the metal wiring material layer pattern and the uneven pattern by a wet method, and washing and drying.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a도 및 제2b도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A and 2B are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
제2a도를 참조하면, 하부절연층(도시안됨)이 형성된 반도체기판(11) 상부에 요철(13)을 형성한다.Referring to FIG. 2A, the unevenness 13 is formed on the semiconductor substrate 11 on which the lower insulating layer (not shown) is formed.
이 때, 상기 요철(13)은 실리콘을 함유하는 알루미늄 합금을 형성하고, 상기 알루미늄합금만을 습식방법으로 식각함으로써 상기 반도체기판(11) 상부에 실리콘으로 형성된 실리콘 노듈(silicon nodule)의 형태로 형성된다.At this time, the irregularities 13 are formed in the form of a silicon nodule formed of silicon on the semiconductor substrate 11 by forming an aluminum alloy containing silicon, and etching only the aluminum alloy by a wet method. .
여기서, 상기 요철(13)은 상기 반도체기판(11)과 금속배선재료(15)과의 접착력을 증가시키기위한 것으로서, 후속공정에서 식각공정이 용이하도록 실리콘을 함유하는 반구형태로 형성한다.Here, the unevenness 13 is to increase the adhesion between the semiconductor substrate 11 and the metal wiring material 15, and is formed in a hemispherical shape containing silicon to facilitate the etching process in a subsequent process.
그 다음에, 전체표면상부에 금속배선 물질층(15)을 형성한다. 그리고, 그 상부에 금속 배선마스크(도시안됨)를 이용한 노광 및 현상 공정으로 감광막패턴(17)을 형성한다.Next, a metal wiring material layer 15 is formed over the entire surface. Then, the photosensitive film pattern 17 is formed on the top thereof by an exposure and development process using a metal wiring mask (not shown).
제2b도를 참조하면, 상기 감광막패턴(17)을 마스크로하여 상기 금속배선 물질층(15)과 요철(13)을 순차적으로 식각하되, 플라즈마를 이용한 건식방법으로 식각함으로써 금속배선 물질층(15)패턴과 요철(13)패턴을 형성한다.Referring to FIG. 2B, the metal wiring material layer 15 and the unevenness 13 are sequentially etched using the photoresist pattern 17 as a mask, and the metal wiring material layer 15 is etched by a dry method using plasma. ) Patterns and irregularities 13 patterns are formed.
여기서, 상기 플라즈마식각공정은 상기 요철(13)을 제거하기위하여 과도 식각한다.Here, the plasma etching process is excessively etched to remove the unevenness 13.
그 다음에, 상기 금속배선 물질층(15)패턴과 요철(13)패턴의 적층구조 측벽 및 저부에 남아있는 식각잔류물(도시안됨)을 습식방법으로 제거하고 세척공정을 실시한 다음, 건조기를 이용하여 건조시킴으로써 하부가 요철(13)패턴으로 형성되고, 상부가 금속배선 물질층(15)으로 형성되는 금속배선(19)을 형성한다.Next, the etching residues (not shown) remaining on the sidewalls and the bottom of the stacked structure of the metallization material layer 15 pattern and the unevenness 13 pattern are removed by a wet method, followed by a washing process, and then using a dryer. By drying, the lower portion is formed in the unevenness 13 pattern, and the upper portion is formed of the metal wiring 19 formed of the metal wiring material layer 15.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 하부절연층이 형성된 반도체기판 상부에 요철을 형성하고, 후속 금속 배선 형성공정을 실시함으로써 금속배선과 반도체기판의 접착력을 향상시켜 상기 금속배선이 손상되는 현상을 방지하고, 그에 따른 반도체 소자의 수율 및 생산성을 향상시키며, 반도체소자의 고집적화를 가능하게 하는 효과가 있다.As described above, the metal wiring forming method of the semiconductor device according to the present invention improves the adhesion between the metal wiring and the semiconductor substrate by forming irregularities on the upper surface of the semiconductor substrate on which the lower insulating layer is formed, and performing a subsequent metal wiring forming process. There is an effect of preventing the metal wiring from being damaged, thereby improving the yield and productivity of the semiconductor device, and enabling high integration of the semiconductor device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950032741A KR0171945B1 (en) | 1995-09-29 | 1995-09-29 | Metal wiring formation method of semiconductor device |
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|---|---|---|---|
| KR1019950032741A KR0171945B1 (en) | 1995-09-29 | 1995-09-29 | Metal wiring formation method of semiconductor device |
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| KR970018235A KR970018235A (en) | 1997-04-30 |
| KR0171945B1 true KR0171945B1 (en) | 1999-03-30 |
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| KR1019950032741A Expired - Fee Related KR0171945B1 (en) | 1995-09-29 | 1995-09-29 | Metal wiring formation method of semiconductor device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014081966A1 (en) * | 2012-11-26 | 2014-05-30 | Applied Materials, Inc. | Stiction-free drying process with contaminant removal for high-aspect-ratio semiconductor device structures |
| US10032624B2 (en) | 2015-10-04 | 2018-07-24 | Applied Materials, Inc. | Substrate support and baffle apparatus |
| US10283344B2 (en) | 2014-07-11 | 2019-05-07 | Applied Materials, Inc. | Supercritical carbon dioxide process for low-k thin films |
| US10304703B2 (en) | 2015-10-04 | 2019-05-28 | Applied Materials, Inc. | Small thermal mass pressurized chamber |
| US10777405B2 (en) | 2015-10-04 | 2020-09-15 | Applied Materials, Inc. | Drying process for high aspect ratio features |
| US11133174B2 (en) | 2015-10-04 | 2021-09-28 | Applied Materials, Inc. | Reduced volume processing chamber |
-
1995
- 1995-09-29 KR KR1019950032741A patent/KR0171945B1/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014081966A1 (en) * | 2012-11-26 | 2014-05-30 | Applied Materials, Inc. | Stiction-free drying process with contaminant removal for high-aspect-ratio semiconductor device structures |
| US10347511B2 (en) | 2012-11-26 | 2019-07-09 | Applied Materials, Inc. | Stiction-free drying process with contaminant removal for high-aspect ratio semiconductor device STR |
| US10354892B2 (en) | 2012-11-26 | 2019-07-16 | Applied Materials, Inc. | Stiction-free drying process with contaminant removal for high-aspect ratio semiconductor device structures |
| US11011392B2 (en) | 2012-11-26 | 2021-05-18 | Applied Materials, Inc. | Stiction-free drying process with contaminant removal for high-aspect ratio semiconductor device structures |
| US10283344B2 (en) | 2014-07-11 | 2019-05-07 | Applied Materials, Inc. | Supercritical carbon dioxide process for low-k thin films |
| US10032624B2 (en) | 2015-10-04 | 2018-07-24 | Applied Materials, Inc. | Substrate support and baffle apparatus |
| US10304703B2 (en) | 2015-10-04 | 2019-05-28 | Applied Materials, Inc. | Small thermal mass pressurized chamber |
| US10777405B2 (en) | 2015-10-04 | 2020-09-15 | Applied Materials, Inc. | Drying process for high aspect ratio features |
| US11133174B2 (en) | 2015-10-04 | 2021-09-28 | Applied Materials, Inc. | Reduced volume processing chamber |
| US11424137B2 (en) | 2015-10-04 | 2022-08-23 | Applied Materials, Inc. | Drying process for high aspect ratio features |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970018235A (en) | 1997-04-30 |
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