KR0143035B1 - Charge pump circuit - Google Patents
Charge pump circuitInfo
- Publication number
- KR0143035B1 KR0143035B1 KR1019940038582A KR19940038582A KR0143035B1 KR 0143035 B1 KR0143035 B1 KR 0143035B1 KR 1019940038582 A KR1019940038582 A KR 1019940038582A KR 19940038582 A KR19940038582 A KR 19940038582A KR 0143035 B1 KR0143035 B1 KR 0143035B1
- Authority
- KR
- South Korea
- Prior art keywords
- charge pump
- pump circuit
- high voltage
- clock signal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Read Only Memory (AREA)
Abstract
본 발명은 챠지 펌프회로에 관한 것으로, 클럭신호 발생기로부터 입력되는 입력펄스의 전압차를 증가시켜 네가티브 챠지펌프회로의 펌핑전압을 빠른 시간내에 얻을 수 있도록 하므로써 빠른 펌핑시간을 갖는 펌핑회로에 의해 소거모드시 소요되는 시간을 단축시키도록 한 챠지 펌프회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit, and increases the voltage difference of an input pulse input from a clock signal generator so that a pumping voltage of a negative charge pump circuit can be obtained within a short time by a pumping circuit having a fast pumping time. It relates to a charge pump circuit to shorten the time required.
Description
제1도는 본 발명에 따른 챠지 펌프회로의 블록도.1 is a block diagram of a charge pump circuit according to the present invention.
제2도는 제 1 도에서의 고전압 드라이버의 상세 회로도.2 is a detailed circuit diagram of the high voltage driver in FIG.
제3도는 제 1 도에서의 포지티브 챠지 펌프회로의 상세회로도.3 is a detailed circuit diagram of the positive charge pump circuit in FIG.
제4도는 제 1 도에서의 네가티브 챠지 펌프회로의 상세회로도.4 is a detailed circuit diagram of the negative charge pump circuit in FIG.
제5도는 종래 및 본 발명에 따른 챠지 펌프회로의 파형도.5 is a waveform diagram of a charge pump circuit according to the prior art and the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:클럽신호발생기 2:고전압 드라이버1: Club Signal Generator 2: High Voltage Driver
3:포지티브 챠지 펌프회로 4:네가티브 챠지 펌프회로3: Positive charge pump circuit 4: Negative charge pump circuit
5:트랜스터 트랜지스터부 6:캐패시터 트랜지스터부5: transistor transistor section 6: capacitor transistor section
본 발명은 챠지 펌프회로에 관한 것으로, 특히 클럭신호 발생기로 부터 입력되는 입력퍼스의 전압차를 증가시켜 네가티브 챠지펌프회로의 펌핑전압을 빠른 시간내에 얻을 수 있도록 한 챠지펌프회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit, and more particularly, to a charge pump circuit in which a pumping voltage of a negative charge pump circuit can be obtained in a short time by increasing the voltage difference of an input perth input from a clock signal generator.
일반적으로 네가티브 챠지펌프회로의 높은 전압을 이용하는 플레쉬이이피롬(Flash EEPROM)의 소거모드시 적용된다.In general, it is applied in the erase mode of the flash EEPROM using the high voltage of the negative charge pump circuit.
종래에는 소거모드시 고전압을 얻기 위해 챠지 펌프회로의 입력펄스에 대해 주기 및 펌핑단위수를 조절하여 원하는 전압을 얻을 수 있었다.Conventionally, in order to obtain a high voltage in the erase mode, a desired voltage may be obtained by adjusting a cycle and a number of pumping units with respect to an input pulse of a charge pump circuit.
그러나 펄스의 주기가 너무 작거나 너무 큰 경우에는 펌핑전압 및 속도가 나빠지는 문제점이 있고, 펌핑속도를 늘기기 위해 펌핑단을 늘려주므로 인해 칩 면적이 많이 소모되는 단점이 있다.However, if the period of the pulse is too small or too large, there is a problem in that the pumping voltage and speed is bad, and because the pumping stage is increased to increase the pumping speed, the chip area is consumed a lot.
따라서 본 발명은 클럭신호 발생기로부터 입력되는 입력펄스의 전압차를 증가시켜 네가티브 챠지펌프회로의 펌핑전압을 빠른 시간내에 얻을 수 있도록 하므로써 상기한 단점을 해소할 수 있는 챠지 펌프회로를 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a charge pump circuit capable of solving the above-mentioned disadvantages by increasing the voltage difference of an input pulse input from a clock signal generator so that the pumping voltage of a negative charge pump circuit can be obtained in a short time. have.
상술한 목적을 달성하기 위한 본 발명은 클럭신호 발생기로부터 공급되는 클럭신호를 입력으로 하며 고전압을 출력시키도록 한 포지티브 챠지 펌프회로와, 상기 클럭신호 발생기로부터 공급되는 클럭신호 및 상기 포지티브 챠지 펌프회로로부터 공급되는 고전압을 입력으로 하며 네가티브 챠지펌프회로를 구동하기 위한 큰 전압차를 갖는 클럭신호를 출력하도록 하는 고전압 드라이버와, 웰 바이어스 전압을 입력으로 하고 상기 포지티브 챠지펌프회로로부터 공급되는 고전압 및 상기 고전압 드라이버로부터 공급되는 큰 전압차를 갖는 클럭신호를 입력으로 하며 빠른 신호내에 펌핑전압을 얻을 수 있도록 한 네가티브 챠지 펌프회로로 구성되는 것을 특징으로 한다.The present invention for achieving the above object is a positive charge pump circuit for inputting the clock signal supplied from the clock signal generator and outputting a high voltage, from the clock signal supplied from the clock signal generator and the positive charge pump circuit A high voltage driver for inputting a high voltage supplied and outputting a clock signal having a large voltage difference for driving a negative charge pump circuit; a high voltage and the high voltage driver supplied from the positive charge pump circuit with a well bias voltage as an input; It is characterized in that it is composed of a negative charge pump circuit which inputs a clock signal having a large voltage difference supplied from the circuit and obtains a pumping voltage in a fast signal.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제 1 도는 본 발명에 따른 챠지 펌프회로의 블록도로서 그 동작을 설명하면 다음과 같다.1 is a block diagram of a charge pump circuit according to the present invention will be described as follows.
클럭신호 발생기(1)는 링오실레이터(도시안됨)로 부터 공급되는 신호를 입력으로 하여 포지티브 챠지펌프회로(3) 및 고전압 드라이버(2)를 통해 네가티브 챠지펌프회로(4)로 클럭신호를 발생시킨다. 이때 발생된 클럭신호를 입력으로 하는 포지티브 챠지 펌프회로(3)는 고전압을 만들게 된다.The clock signal generator 1 inputs a signal supplied from a ring oscillator (not shown) to generate a clock signal to the negative charge pump circuit 4 through the positive charge pump circuit 3 and the high voltage driver 2. . At this time, the positive charge pump circuit 3 using the generated clock signal as an input generates a high voltage.
이 고전압을 상기 고전압 드라이버(2)로 입력되어 작은 전압 차를 갖는 클럭신호를 큰 전압차를 갖는 클럭신호(PH1 및 PH2)로 변환시킨다. 변환된 큰 전압차를 갖는 클럭신호(PH1및 PH2) 및 고전압(VHV)신호와 웰 바이어스(Well Bias) 전압에 의해 네가티브 챠지 펌프회로(4)가 구동되므로써 빠른 펌핑속도를 갖는 네가티브 챠지펌핑전압(NQP)이 출력되게 된다.The high voltage is inputted to the high voltage driver 2 to convert clock signals having a small voltage difference into clock signals PH1 and PH2 having a large voltage difference. Negative charge pumping voltage having a high pumping speed by driving the negative charge pump circuit 4 by the clock signals PH1 and PH2 and the high voltage V HV signal and the well bias voltage having the large voltage difference. (NQP) is output.
제 2 도는 제 1 도에서의 고전압 드라이버의 상세회로도로서 동작을 설명하면 다음과 같다.FIG. 2 is a detailed circuit diagram of the high voltage driver of FIG.
입력단자(IN)로 입력되는 상기 클럭신호 발생기(1)로부터 공급되는 클럭신호와 고전압 입력단자(HV)로 입력되는 상기 포지티브 챠지펌프회로(3)로부터 공급되는 고전압에 의해 출력(OUT)으로 큰 전압차를 갖는 클럭신호(PH1 및 PH2)가 출력된다. 즉, 입력단자(IN)가 고전위(High)상태라고 가정하면, 게이트 단자가 전원(Vcc)에 접속된 NMOS 트랜지스터(N1)가 턴온되어 노드(K1)는 고전위(Vcc)가 되어 상기 노드(K1)를 입력으로 하는 PMOS 트랜지스터(P2) 및 NMOS 트랜지스터(N2)중 NMOS 트랜지스터가 턴온되어 노드(K2)의 전위가 저전위(LOW)로 된다. 이때 노드(K2)를 입력으로 하는 PMOS 트랜지스터(P1)가 턴온되어 고전압 입력단자(HV)로부터 입력되는 고전압(VHV)이 상기 PMOS 트랜지스터(P1)를 통해 노드(K1)로 공급되어 노드(K1)의 전위가 고전압(VHV)으로 상승된다. 이때 노드(K2)를 입력으로 하는 PMOS 트랜지스터(P3) 및 NMOS 트랜지스터중 PMOS 트랜지스터(P3)가 턴온되어 고전압 입력단자(HV)로부터 입력되는 고전압(VHV)이 출력(OUT)으로 큰 전압차를 갖는 클럭신호를 출력되게 된다.The output signal is large due to the clock signal supplied from the clock signal generator 1 input to the input terminal IN and the high voltage supplied from the positive charge pump circuit 3 input to the high voltage input terminal HV. Clock signals PH1 and PH2 having a voltage difference are output. That is, assuming that the input terminal IN is in the high state, the NMOS transistor N1 having the gate terminal connected to the power supply Vcc is turned on, so that the node K1 becomes the high potential Vcc. The NMOS transistors of the PMOS transistor P2 and the NMOS transistor N2 that take (K1) as inputs are turned on so that the potential of the node K2 becomes low potential (LOW). At this time, the PMOS transistor P1 having the node K2 as input is turned on, and the high voltage V HV input from the high voltage input terminal HV is supplied to the node K1 through the PMOS transistor P1, thereby providing a node K1. ) Is raised to a high voltage (V HV ). At this time, among the PMOS transistor P3 and the NMOS transistor P3 having the node K2 as input, the PMOS transistor P3 is turned on so that the high voltage V HV input from the high voltage input terminal HV causes a large voltage difference to the output OUT. The clock signal having the same is outputted.
제 3 도는 제 1 도에서의 포지티브 챠지 펌프회로의 상세회로도로서 동작을 설명하면 다음과 같다.FIG. 3 is a detailed circuit diagram of the positive charge pump circuit in FIG. 1 and the operation thereof is as follows.
클럭신호발생기(1)로부터 출력되는 다수의 클럭신호(PPH1, PPH2, PPH3)를 입력으로 하며 입력되는 클럭신호(PPH1, PPH2, PPH3)에 따라 고전위 출력단자(HV)로 고전압(VH)이 출력되게 된다. 즉, 다수의 클럭신호(PPH1, PPH2,PPH3)가 다수의 캐패시터용 트랜지스터(N4 내지 N7)로 챠지되어 최종단에 있는 NMOS 트랜지스터(N8)를 통해 고전압(VHV)으로 출력되게 된다.A plurality of clock signals PPH1, PPH2, and PPH3 output from the clock signal generator 1 are input, and a high voltage V H is applied to the high potential output terminal HV according to the input clock signals PPH1, PPH2, and PPH3. Will be output. That is, the plurality of clock signals PPH1, PPH2, and PPH3 are charged by the plurality of capacitor transistors N4 to N7 and are outputted to the high voltage V HV through the NMOS transistor N8 at the final stage.
제 4 도는 제 1 도에서의 네가티브 챠지펌프회로의 상세회로도로서 동작을 설명하면 다음과 같다.4 is a detailed circuit diagram of the negative charge pump circuit in FIG.
고전압 드라이버(2)로부터 출력되는 큰 전압차를 갖는 클럭신호(PH1 및 PH2)를 입력으로 하며, 상기 포지티브 챠지펌프회로(3)의 고전압 출력단자(HV)로부터 고전압(VHV)을 입력으로 하는 네가티브 챠지펌프회로(4)에서 트랜스터 트랜지스터부(5)에 웰 바이어스(Well Bias)를 걸기위한 바이어스 전압(WBIAS)을 걸어주므로써 상기 큰 전압차를 갖는 클럭신호(PH1 및 PH2) 및 고전압(VHV)에 의해 캐패시터 트랜지스터부(6)가 작동하여 상기 네가티브 챠지 펌프회로(4)의 출력(NQP)으로 빠른 펌핑 속도를 갖는 네가티브 챠지 펌핑전압이 출력되게 된다.The clock signals PH1 and PH2 having a large voltage difference output from the high voltage driver 2 are input, and the high voltage V HV is input from the high voltage output terminal HV of the positive charge pump circuit 3. In the negative charge pump circuit 4, the bias voltage WBIAS is applied to the transistor transistor 5 to apply the well bias to the transistor B. Thus, the clock signals PH1 and PH2 having the large voltage difference and the high voltage ( The capacitor transistor unit 6 is operated by V HV ) to output a negative charge pumping voltage having a high pumping speed to the output NQP of the negative charge pump circuit 4.
제 5 도는 종래 및 본 발명에 따른 챠지 펌프회로의 파형도로서 기존의 네가티브 챠지 펌프회로를 동작시켰을 때의 파형(x)과 본 발명에 다른 높은 전압차를 갖는 클럭신호를 펌핑동작시켰을 때의 파형(y)을 비교한 파형도이다.5 is a waveform diagram of a charge pump circuit according to the related art and the present invention. The waveform when the negative charge pump circuit is operated and the clock signal having a high voltage difference different from the present invention are pumped. It is a waveform chart comparing (y).
상술한 바와같이 본 발명에 의하여 클럭신호 발생기로부터 입력되는 입력퍼스의 전압차를 증가시켜 네가티브 챠지펌프회로의 펌핑전압을 빠른 시가내에 얻을 수 있도록 하므로써 칩면적이 감소되고, 빠른 펌핑시간을 갖는 펌핑회로에 의해 소거모드시 소요되는 시간을 줄이는데 탁월한 효과가 있다.As described above, the pump area of the negatively charged pump circuit can be obtained within a short time by increasing the voltage difference between the input pulses input from the clock signal generator, thereby reducing the chip area and providing a fast pumping time. It has an excellent effect in reducing the time required in the erase mode.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940038582A KR0143035B1 (en) | 1994-12-29 | 1994-12-29 | Charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940038582A KR0143035B1 (en) | 1994-12-29 | 1994-12-29 | Charge pump circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960025760A KR960025760A (en) | 1996-07-20 |
| KR0143035B1 true KR0143035B1 (en) | 1998-08-17 |
Family
ID=19404806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940038582A Expired - Fee Related KR0143035B1 (en) | 1994-12-29 | 1994-12-29 | Charge pump circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0143035B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100842744B1 (en) * | 2006-11-20 | 2008-07-01 | 주식회사 하이닉스반도체 | Clock control circuit and voltage pumping device using same |
| KR100922681B1 (en) * | 2007-02-28 | 2009-10-19 | 산요덴키가부시키가이샤 | Charge pump circuit |
-
1994
- 1994-12-29 KR KR1019940038582A patent/KR0143035B1/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100842744B1 (en) * | 2006-11-20 | 2008-07-01 | 주식회사 하이닉스반도체 | Clock control circuit and voltage pumping device using same |
| US7772914B2 (en) | 2006-11-20 | 2010-08-10 | Hynix Semiconductor Inc. | Clock control circuit and voltage pumping device using the same |
| US7969234B2 (en) | 2006-11-20 | 2011-06-28 | Hynix Semiconductor Inc. | Clock control circuit and voltage pumping device using the same |
| KR100922681B1 (en) * | 2007-02-28 | 2009-10-19 | 산요덴키가부시키가이샤 | Charge pump circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960025760A (en) | 1996-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100259784B1 (en) | Voltage booster circuit | |
| US7208996B2 (en) | Charge pump circuit | |
| KR100273278B1 (en) | Pumping circuit of semiconductor device | |
| US20020014908A1 (en) | Device for voltage multiplication with high efficiency, combination of the device with a battery-operated apparatus, and low-power loss generation of a programming voltage | |
| KR100419925B1 (en) | Voltage multiplier with an output voltage practically independent of the supply voltage | |
| JPH09198887A (en) | High voltage generation circuit | |
| US6184594B1 (en) | Multi-stage charge pump having high-voltage pump control feedback and method of operating same | |
| KR100725380B1 (en) | Voltage generating circuit of semiconductor memory device, semiconductor memory device comprising same and voltage generating method of semiconductor memory device | |
| JPH06153493A (en) | Charge pump circuit | |
| KR100279296B1 (en) | Step-up voltage generator circuit | |
| US5952851A (en) | Boosted voltage driver | |
| KR19990050472A (en) | Step-up Voltage Generation Circuit | |
| KR0143035B1 (en) | Charge pump circuit | |
| US7053689B2 (en) | High voltage switch circuit | |
| US5587956A (en) | Semiconductor memory device having function of generating boosted potential | |
| US5670908A (en) | Circuit for controlling output voltage from charge pump | |
| US20020181310A1 (en) | Semiconductor memory device internal voltage generator and internal voltage generating method | |
| JP3764176B2 (en) | Semiconductor device | |
| JPH08237938A (en) | Internal voltage generation circuit | |
| US7221573B2 (en) | Voltage up converter | |
| KR20010004448A (en) | An Invertor for outputting a high voltage | |
| KR100349349B1 (en) | Charge pump circuit | |
| US20240097564A1 (en) | Charge pump circuit and drive device | |
| KR100576504B1 (en) | Charge Pump Circuit | |
| KR100245088B1 (en) | High voltage generator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-3-3-R10-R17-oth-X000 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U11-oth-PR1002 Fee payment year number: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 5 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 6 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 7 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 8 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 9 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 10 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 11 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-5-5-R10-R17-oth-X000 |
|
| FPAY | Annual fee payment |
Payment date: 20090327 Year of fee payment: 12 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 12 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
St.27 status event code: A-4-4-U10-U13-oth-PC1903 Not in force date: 20100407 Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 20100407 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |