JPWO2022168803A1 - - Google Patents

Info

Publication number: JPWO2022168803A1
Authority: JP; Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

JP2022579538A

Other versions

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2021-02-05

Filing date

2022-01-31

Publication date

2022-08-11

2022-01-31 Application filed filed Critical

2022-08-11 Publication of JPWO2022168803A1 publication Critical patent/JPWO2022168803A1/ja

2026-01-08 Application granted granted Critical

2026-01-08 Publication of JP7795724B2 publication Critical patent/JP7795724B2/ja

Status Active legal-status Critical Current

2042-01-31 Anticipated expiration legal-status Critical

Classifications

- H10W90/00—
- H10W20/20—
- H10W70/611—
- H10W70/614—
- H10W70/618—
- H10W70/65—
- H10W70/685—
- H10W70/69—
- H10W70/695—
- H10W72/20—
- H10W90/401—
- H10W42/121—
- H10W70/63—
- H10W70/635—
- H10W70/652—
- H10W72/60—
- H10W72/823—
- H10W74/15—
- H10W90/22—
- H10W90/297—
- H10W90/701—
- H10W90/722—
- H10W90/724—
- H10W90/734—

JP2022579538A 2021-02-05 2022-01-31 半導体パッケージ及び半導体パッケージの製造方法並びにインターポーザ群 Active JP7795724B2 (ja)

Applications Claiming Priority (3)

Application Number	Priority Date	Filing Date	Title
JP2021017623		2021-02-05
JP2021017623		2021-02-05
PCT/JP2022/003672 WO2022168803A1 (ja)	2021-02-05	2022-01-31	半導体パッケージ及び半導体パッケージの製造方法並びにインターポーザ群

Publications (2)

Publication Number	Publication Date
JPWO2022168803A1 true JPWO2022168803A1 (ja)	2022-08-11
JP7795724B2 JP7795724B2 (ja)	2026-01-08

Family

ID=82741348

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
JP2022579538A Active JP7795724B2 (ja)	2021-02-05	2022-01-31	半導体パッケージ及び半導体パッケージの製造方法並びにインターポーザ群

Country Status (5)

Country	Link
US (1)	US20240096808A1 (ja)
JP (1)	JP7795724B2 (ja)
KR (1)	KR20230144557A (ja)
CN (1)	CN116888735A (ja)
WO (1)	WO2022168803A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
KR20230063143A (ko) *	2021-11-01	2023-05-09	삼성전자주식회사	반도체 패키지
KR20250099432A (ko) *	2023-12-24	2025-07-01	앱솔릭스 인코포레이티드	패키징 기판의 제조 방법 및 이를 이용한 패키징 기판

Citations (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH11177020A (ja) *	1997-12-11	1999-07-02	Oki Electric Ind Co Ltd	半導体実装構造およびその実装方法
US20140048928A1 (en) *	2012-08-17	2014-02-20	Cisco Technology, Inc.	Multi-Chip Module with Multiple Interposers
JP2015507372A (ja) *	2012-02-08	2015-03-05	ザイリンクスインコーポレイテッドＸｉｌｉｎｘＩｎｃｏｒｐｏｒａｔｅｄ	複数のインターポーザを伴うスタックドダイアセンブリ
JP2016149556A (ja) *	2013-02-13	2016-08-18	クアルコム，インコーポレイテッド	スタックされたメモリ要素を有する半導体デバイスおよび半導体デバイス上にメモリ要素をスタックする方法
JP2018164066A (ja) *	2017-03-28	2018-10-18	京セラ株式会社	複合配線基板
US20200395313A1 (en) *	2019-06-11	2020-12-17	Intel Corporation	Heterogeneous nested interposer package for ic chips

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS6014907U (ja)	1983-07-12	1985-01-31	日本ゼニスパイプ株式会社	コンクリ−ト製曲がり管製造用の内側型枠
JPS6159820U (ja)	1984-09-25	1986-04-22

2022
- 2022-01-31 JP JP2022579538A patent/JP7795724B2/ja active Active
- 2022-01-31 WO PCT/JP2022/003672 patent/WO2022168803A1/ja not_active Ceased
- 2022-01-31 US US18/264,281 patent/US20240096808A1/en active Pending
- 2022-01-31 KR KR1020237029682A patent/KR20230144557A/ko active Pending
- 2022-01-31 CN CN202280013254.XA patent/CN116888735A/zh active Pending

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH11177020A (ja) *	1997-12-11	1999-07-02	Oki Electric Ind Co Ltd	半導体実装構造およびその実装方法
JP2015507372A (ja) *	2012-02-08	2015-03-05	ザイリンクスインコーポレイテッドＸｉｌｉｎｘＩｎｃｏｒｐｏｒａｔｅｄ	複数のインターポーザを伴うスタックドダイアセンブリ
US20140048928A1 (en) *	2012-08-17	2014-02-20	Cisco Technology, Inc.	Multi-Chip Module with Multiple Interposers
JP2016149556A (ja) *	2013-02-13	2016-08-18	クアルコム，インコーポレイテッド	スタックされたメモリ要素を有する半導体デバイスおよび半導体デバイス上にメモリ要素をスタックする方法
JP2018164066A (ja) *	2017-03-28	2018-10-18	京セラ株式会社	複合配線基板
US20200395313A1 (en) *	2019-06-11	2020-12-17	Intel Corporation	Heterogeneous nested interposer package for ic chips

Also Published As

Publication number	Publication date
JP7795724B2 (ja)	2026-01-08
KR20230144557A (ko)	2023-10-16
TW202247372A (zh)	2022-12-01
WO2022168803A1 (ja)	2022-08-11
CN116888735A (zh)	2023-10-13
US20240096808A1 (en)	2024-03-21

Publication	Publication Date	Title
BR112023005462A2 (ja)	2023-05-30
BR112023012656A2 (ja)	2023-10-03
BR112021014123A2 (ja)	2021-12-07
BR112023009656A2 (ja)	2023-07-11
BR112022009896A2 (ja)	2023-06-27
BR112023008622A2 (ja)	2023-10-03
BR112022024743A2 (ja)	2023-06-27
JPWO2022168803A1 (ja)	2022-08-11
BR112022026905A2 (ja)	2023-06-27
BR112023011738A2 (ja)	2023-07-04
BR112023004146A2 (ja)	2023-06-27
BR112023006729A2 (ja)	2023-05-16
BR102021018859A2 (ja)	2021-11-30
BR102021015500A2 (ja)	2021-11-09
BR112021017747A2 (ja)	2023-06-06
BR112023016292A2 (ja)	2023-09-05
BR112023011539A2 (ja)	2023-07-04
BR112023011610A2 (ja)	2023-07-04
BR112023008976A2 (ja)	2023-06-27
BR102021020147A2 (ja)	2021-12-28
BR102021018926A2 (ja)	2021-11-30
BR102021018167A2 (ja)	2021-09-13
BR102021017576A2 (ja)	2021-11-30
BR102021016837A2 (ja)	2021-11-09
BR102021016551A2 (ja)	2021-11-09

Legal Events

Date	Code	Title	Description
2024-09-10	A621	Written request for application examination	Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20240910
2025-06-27	A131	Notification of reasons for refusal	Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20250627
2025-08-04	A521	Request for written amendment filed	Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20250804
2025-11-18	TRDD	Decision of grant or rejection written
2025-11-21	A01	Written decision to grant a patent or to grant a registration (utility model)	Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20251121
2025-12-24	A61	First payment of annual fees (during grant procedure)	Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20251204
2026-01-07	R150	Certificate of patent or registration of utility model	Ref document number: 7795724 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150