JPWO2001029814A1 - display device - Google Patents

Abstract

(57) [Abstract] A display device is obtained that takes into consideration layout efficiency, etc., when peripheral circuits are integrally formed on a glass substrate. An active matrix LCD section (2) forms a grid of multiple scanning lines and multiple data lines corresponding to dots, with active elements provided at each intersection, and controls display using liquid crystal by driving the scanning lines and data lines; a row decoder (31) selects the scanning lines; a memory cell section (56) in which memory cells sufficient in number to store image signals for at least one row of dots in the display driver section are allocated in accordance with the length of the row direction of the display driver section; a column decoder section (51) selects memory cells in which to store input image signals; a column selection switch section (53) that switches based on the selection of the column decoder section (51) and the image signal to store the image signal in the selected memory cell; and a k-bit DAC section (41) that drives the data lines based on the image signal stored in the memory cell section.

Description

Detailed Description of the Invention

TECHNICAL FIELD The present invention relates to a display device. In particular, the present invention relates to a liquid crystal display (LCD).
Liquid Crystal Display) or Organic EL Display (O
ELD: Organic Electro Luminescent Disp
This relates to a drive circuit for displaying an image (lay). BACKGROUND ART Recently, display devices using liquid crystal (hereinafter referred to as displays) have been rapidly gaining popularity. This type of display consumes less power and takes up less space than CRT displays. Therefore, it is important to take advantage of the advantages of such displays to create displays that consume less power and take up less space. Figure 11 is a block diagram of a system for displaying images using a TFT display. This system is composed of an image signal source 100 and a TFT liquid crystal display panel 101. The image signal source 100 is connected to at least a CPU 10
0A, RAM 100B, frame memory 100C, and LCD controller 100
The CPU 100A is a calculation control means that transmits display data while exchanging data with the RAM 100B, which is a general-purpose memory.
AM 100B is not exclusively used as display memory; therefore, a new memory for storing display data is required. This is frame memory 100C. Frame memory 100C temporarily stores data for displaying one screen of liquid crystal panel 101C (hereinafter, one pixel's worth of data is referred to as display data, and each binary signal constituting the display data is referred to as an image signal). LCD controller 100D controls the transmission of display data stored in frame memory 100C to display the data at each display position on liquid crystal panel 101C at each timing. While a CRT requires the display data to be converted to analog data before transmission, this LCD display transmits the display data as digital image signals, assuming that the LCD display interface supports digital data. If the image signal is digital, D/A conversion is not required on the TFT liquid crystal display panel 101 side. Meanwhile, TFT liquid crystal display panel 101 is comprised of scan line driver 101A, digital data driver 101B, and liquid crystal panel 101C. The scanning line driver 101A controls the display in the scanning line (row) direction based on timing data transmitted from the LCD controller 100D.
The digital data driver 101B can receive and process digital image signals. The digital data driver 101B controls the display in the data line (column) direction based on timing data sent from the LCD controller 100D.
The liquid crystal panel 101C also controls the display gradation.
The LCD panel has a 100-nm film transistor (nFMT) and displays images under the control of a scan line driver 101A and a digital data driver 101B. In such a system, an LCD controller 100D must transmit image signals for the entire screen's worth of display data temporarily stored in a frame memory 100C to the digital data driver 101B. Furthermore, because the transmission timing is fixed for sequential scanning, image signals must be transmitted in accordance with the timing, even for display data for pixels whose display does not change. This not only results in a large amount of wasted data transmission, but also consumes a large amount of power, making it difficult to achieve low power consumption. Therefore, an object of the present invention is to provide a display device with a structure that achieves low power consumption, yet also with a space-saving design that takes into account layout efficiency, etc., especially when peripheral circuits are integrally formed on a glass substrate. Disclosure of the Invention A display device according to the invention of claim 1 comprises a display drive section which forms a plurality of scanning lines and a plurality of data lines in a lattice pattern corresponding to dots, which are the smallest unit of display, and provides active elements corresponding to each intersection, and which controls display using liquid crystal by driving the scanning lines and data lines; a scanning line driver section which is allocated corresponding to the length of the display drive section in the column direction and which selects and drives the scanning lines; a memory cell section which is allocated corresponding to the length of the display drive section in the row direction and which has a number of memory cells which are capable of storing image signals for at least performing display control for one row of dots of the display drive section, and which is allocated corresponding to the length of the display drive section in the row direction; a column decoder section which is allocated corresponding to the length of the display drive section in the row direction and which selects the memory cells which will store input image signals; a column selection switch section which is allocated corresponding to the length of the display drive section in the row direction and which performs switching based on the selection by the column decoder section and the image signal, causing the image signal to be stored in the memory cell selected by the column decoder section; and a data line driver section which is allocated corresponding to the length of the display drive section in the row direction and which drives the data lines based on the image signal stored in the memory cell section, all of which are integrated and formed integrally on a semiconductor or insulator substrate. In the present invention, when polycrystalline silicon TFTs are used to integrally form peripheral circuits on an insulating substrate such as a glass substrate or a quartz substrate, in order to save space, not only the column decoder section, the column selection switch section, and the data line driver section, but also the following sections are formed.
The memory cells of the memory cell unit are allocated in a number sufficient to store image signals for at least one row of dots of the display driver unit, in accordance with the row length of the display driver unit. Note that "allocated in accordance with the column length" and "allocated in accordance with the row length" in this invention mean, for example, that in the case of a memory cell unit, the row length thereof corresponds to the row length of the display driver unit, and more specifically, as defined in the invention of claim 2, "the row length is equal to or less than the row length of the display driver unit.""Equal to or less" means that the two are equal, or the former is smaller than the latter, but in this invention, for example, the row length of the memory cell unit is
It is acceptable for the length to be slightly (for example, by a few percent) larger than the row direction length of the display driver unit. The point is that, for example, in the case of a memory cell unit, when integrated on a substrate together with the display driver unit, the dimensions of the memory cell unit do not correspond to the dimensions of the display driver unit, resulting in wasted space on the substrate. The occurrence of wasted space means, for example, that the row direction length of the memory cell unit is significantly longer than the row direction length of the display driver unit, resulting in a relatively large space on the substrate along the row direction side edge of the display driver unit where no circuitry or the like is provided. The display device according to the invention of claim 2 includes a display drive section that forms a plurality of scanning lines and a plurality of data lines in a lattice pattern corresponding to dots, which are the smallest units of display, and provides active elements corresponding to each intersection, and controls display using liquid crystal by driving the scanning lines and data lines; a scanning line driver section that is allocated so that the length in the column direction is equal to or less than the length in the column direction of the display drive section and selects and drives the scanning lines; a memory cell section that is allocated so that the length in the row direction of memory cells is equal to or less than the length in the row direction of the display drive section, and that has a number of memory cells that can store image signals for at least controlling display of one row of dots of the display drive section; a column decoder section which is allocated so that its length in the row direction is equal to or less than the length of the display driver section in the row direction and which selects the memory cells in which to store an input image signal, a column selection switch section which is allocated so that its length in the row direction is equal to or less than the length of the display driver section in the row direction and which switches based on the selection of the column decoder section and the image signal to store the image signal in the memory cell selected by the column decoder section, and a data line driver section which is allocated so that its length in the row direction is equal to or less than the length of the display driver section in the row direction and which drives the data lines based on the image signal stored in the memory cell section, are integrated and formed integrally on a semiconductor or insulator substrate.
The memory cells of the memory cell unit are allocated in a number sufficient to store image signals for at least one row of dots of the display driver unit, and the row length of the memory cells is equal to or less than the row length of the display driver unit. A display device according to the invention of claim 3 comprises a display driver unit which forms a plurality of scanning lines and a plurality of data lines in a lattice pattern corresponding to dots which are the smallest unit of display, and provides active elements corresponding to each intersection thereof, and controls display by driving the scanning lines and data lines to cause organic EL elements connected to the active elements to emit light, a scanning line driver unit which is allocated in a number sufficient to store image signals for at least one row of dots of the display driver unit, and which selects and drives the scanning lines, a memory cell unit which is allocated in a number sufficient to store image signals for at least one row of dots of the display driver unit, and which is allocated in a number sufficient to store image signals for at least one row of dots of the display driver unit, and which is allocated in a number sufficient to store image signals for at least one row of dots of the display driver unit, and which selects the memory cells to store input image signals, and a column selection switch unit which is allocated in a number sufficient to store image signals for at least one row of dots of the display driver unit, and which switches based on the selection of the column decoder unit and the image signal, and causes the image signal to be stored in the memory cell selected by the column decoder.
a data line driver section that is allocated in accordance with the length of the display drive section in the row direction and drives the data lines based on the image signals stored in the memory cell section;
These are integrated and integrally formed on a semiconductor or insulating substrate. In the present invention, when a display driver circuit for controlling display using organic EL elements is integrally formed on, for example, polycrystalline silicon, together with peripheral circuits, in order to save space, not only the column decoder section, column selection switch section, and data line driver section, but also memory cells of a memory cell section, the number of which is sufficient to store image signals for controlling display for at least one row of dots in the display driver section, are allocated in accordance with the row length of the display driver section. Note that, in the present invention, "allocated in accordance with the column length" and "allocated in accordance with the row length" mean, for example, that in the case of a memory cell section, its row length corresponds to the row length of the display driver section. More specifically, as defined in claim 4, "its row length is equal to or less than the row length of the display driver section.""Equal to or less than" means that the two are equal or the former is smaller than the latter. In the present invention, for example, the row length of the memory cell section is
It is acceptable for the length to be slightly (for example, by a few percent) larger than the row direction length of the display driver unit. The point is that, for example, in the case of a memory cell unit, when integrated on a substrate together with the display driver unit, the dimensions of the memory cell unit do not correspond to the dimensions of the display driver unit, resulting in wasted space on the substrate. The occurrence of wasted space means, for example, that the row direction length of the memory cell unit is significantly longer than the row direction length of the display driver unit, resulting in a relatively large space on the substrate along the row direction side edge of the display driver unit where no circuitry or the like is provided. The display device according to the invention of claim 4 comprises a display drive section which forms a plurality of scanning lines and a plurality of data lines in a lattice pattern corresponding to dots which are the smallest units of display, provides active elements corresponding to each intersection, and controls display by driving the scanning lines and data lines to cause organic EL elements connected to the active elements to emit light; a scanning line driver section which is allocated so that the length in the column direction is equal to or less than the length in the column direction of the display drive section and which selects and drives the scanning lines; and a memory cell array which has a number of memory cells which can store image signals for at least one row of dots of the display drive section and is allocated so that the length in the row direction is equal to or less than the length in the row direction of the display drive section. a column decoder section allocated so that its row length is equal to or less than the row length of the display driver section and for selecting the memory cells in which to store an input image signal, a column selection switch section allocated so that its row length is equal to or less than the row length of the display driver section and for switching based on the selection of the column decoder section and the image signal to store the image signal in the memory cell selected by the column decoder section, and a data line driver section allocated so that its row length is equal to or less than the row length of the display driver section and for driving the data lines based on the image signal stored in the memory cell section, in order to save space when a display driver circuit for controlling display using organic EL elements is integrally formed on, for example, polycrystalline silicon, not only the column decoder section, column selection switch section, and data line driver section but also memory cells of a memory cell section in a number sufficient to store an image signal for controlling display of at least one row of dots of the display driver section are allocated so that their row length is equal to or less than the row length of the display driver section. A display device according to the invention of claim 5 comprises a display drive section provided with a plurality of scanning lines and a plurality of bit lines, and liquid crystals controlled for display by driving the corresponding scanning lines and bit lines are provided for each dot, which is the smallest unit of display control, and formed in a matrix; a memory cell section in which memory cells sufficient in number to store image signals for at least controlling the display of one row of dots of the display drive section are allocated in accordance with the length of the row direction of the display drive section and each memory cell is connected to a bit line; a column decoder section allocated in accordance with the length of the row direction of the display drive section and selecting the memory cells in which to store input image signals; and a column selection switch section allocated in accordance with the length of the row direction of the display drive section and switching based on the selection of the column decoder section and the image signal, causing the image signal to be stored in the memory cell selected by the column decoder section, all of which are integrated and formed as a single unit on a semiconductor or insulator substrate. In the present invention, when a display driver circuit for controlling display using liquid crystal, for example, using polycrystalline silicon TFTs, is integrally formed together with peripheral circuits, in order to save space, not only the column decoder section and the column selection switch section but also memory cells of a memory cell section in a number sufficient to store image signals for controlling display of at least one row of dots of the display driver section are allocated in accordance with the length in the row direction of the display driver section.
For example, in the case of a memory cell unit, the row length corresponds to the row length of the display driver unit. More specifically, as defined in claim 6, "the row length is equal to or less than the row length of the display driver unit." While "equal to or less" means either that the two are equal or that the former is smaller than the latter, in the present invention, the row length of the memory cell unit may be slightly (e.g., by a few percent) longer than the row length of the display driver unit. The point is that, for example, when a memory cell unit is integrated on a substrate together with a display driver unit, it is sufficient to avoid the occurrence of wasted space on the substrate due to the memory cell unit's dimensions not corresponding to the display driver unit's dimensions. The occurrence of wasted space means, for example, that the row length of the memory cell unit is significantly longer than the row length of the display driver unit, resulting in a relatively large space on the substrate along the row-direction side edge of the display driver unit where no circuitry or the like is provided. A display device according to the invention of claim 6 comprises a display driver section provided with a plurality of scanning lines and a plurality of bit lines, and liquid crystals controlled for display by driving the corresponding scanning lines and bit lines are provided for each dot, which is the smallest unit of display control, and formed in a matrix; a memory cell section in which memory cells, the number of which is sufficient to store image signals for at least controlling the display of one row of dots of the display driver section, are allocated so that the row length of the memory cells is equal to or less than the row length of the display driver section and each memory cell is connected to a bit line; a column decoder section, allocated so that the row length is equal to or less than the row length of the display driver section and which selects the memory cells in which to store input image signals; and a column selection switch section, allocated so that the row length is equal to or less than the row length of the display driver section and which switches based on the selection of the column decoder section and the image signal, causing the image signal to be stored in the memory cell selected by the column decoder section, all integrated and formed as one unit on a semiconductor or insulator substrate. In the present invention, when a display driver circuit for controlling display using liquid crystal, for example using polycrystalline silicon TFTs, is integrally formed together with peripheral circuits, in order to save space, not only the column decoder section and the column selection switch section but also memory cells of a memory cell section in a number sufficient to store image signals for controlling display of at least one row of dots of the display driver section are allocated so that the row length thereof is equal to or less than the row length of the display driver section. A display device according to the invention of claim 7 comprises a display driver section provided with a plurality of scanning lines and a plurality of bit lines, and an organic EL element for light emission control by driving the corresponding scanning lines and bit lines, which is provided for each dot, which is the smallest unit of display control, and formed in a matrix;
The present invention integrates and forms integrally on a semiconductor or insulating substrate a memory cell section in which a number of memory cells capable of storing an image signal for display control of a row of dots are allocated in correspondence with the row length of the display driver section, and each memory cell is connected to the bit line, a column decoder section allocated in correspondence with the row length of the display driver section and selecting the memory cell for storing an input image signal, and a column selection switch section allocated in correspondence with the row length of the display driver section and switching based on the selection of the column decoder section and the image signal to store the image signal in the memory cell selected by the column decoder section. In the present invention, when a display driver circuit for controlling display using organic EL elements using, for example, polycrystalline silicon TFTs is integrally formed together with peripheral circuits, in order to save space, not only the column decoder section and the column selection switch section but also the memory cells of the memory cell section in which a number of memory cells capable of storing an image signal for display control of at least one row of dots of the display driver section are allocated in correspondence with the row length of the display driver section. Note that the phrase "allocated in correspondence with the row length" in the present invention means that
For example, in the case of a memory cell unit, the row length corresponds to the row length of the display driver unit. More specifically, as defined in claim 8, "the row length is equal to or less than the row length of the display driver unit." While "equal to or less" means either that the two are equal or that the former is smaller than the latter, in the present invention, the row length of the memory cell unit may be slightly (e.g., by a few percent) longer than the row length of the display driver unit. The point is that, for example, when a memory cell unit is integrated on a substrate together with a display driver unit, it is sufficient to avoid the occurrence of wasted space on the substrate due to the memory cell unit's dimensions not corresponding to the display driver unit's dimensions. The occurrence of wasted space means, for example, that the row length of the memory cell unit is significantly longer than the row length of the display driver unit, resulting in a relatively large space on the substrate along the row-direction side edge of the display driver unit where no circuitry or the like is provided. The display device according to the invention of claim 8 is provided with a plurality of scanning lines and a plurality of bit lines, and an organic EL element that is controlled to emit light by driving the corresponding scanning lines and bit lines is provided for each dot, which is the minimum unit of display control, and the display device comprises a display driver formed in a matrix, and at least one of the display drivers
The number of memory cells that can store image signals for display control of the dots in a row is
a column select switch section allocated to have a row length equal to or less than the row length of the display driver section and for switching based on the selection of the column decoder section and the image signal to cause the image signal to be stored in the memory cell selected by the column decoder section, and a column select switch section allocated to have a row length equal to or less than the row length of the display driver section and for switching based on the selection of the column decoder section and the image signal to cause the image signal to be stored in the memory cell selected by the column decoder section, are integrated on a semiconductor or insulating substrate and formed as an integral unit. In the present invention, in order to save space when a display driver circuit that controls display using organic EL elements using, for example, polycrystalline silicon TFTs is integrally formed together with peripheral circuits, not only the column decoder section and the column select switch section but also memory cells of the memory cell section, the number of which is sufficient to store an image signal for controlling display of at least one row of dots of the display driver section, are allocated so that the row length of the memory cell section is equal to or less than the row length of the display driver section. A display device according to the invention of claim 9 is configured so that the memory cells are allocated in accordance with the length of the row direction of the display driver, and the number of memory cells is configured redundantly to a number sufficient to store image signals for performing display control for one row of dots of the display driver. In the present invention, even if the number of memory cells is configured redundantly to a number sufficient to store image signals for performing display control for one row of dots of the display driver, they are allocated based on the length of the row direction of the display driver (for example, so that the length of the row direction is equal to or less than the length of the row direction of the display driver). A display device according to the invention of claim 10 is configured so that the memory cell section is:
The display device is configured to have a memory array corresponding to the dot arrangement of the display driver, with memory cells connected to each of the word lines, the number of which is equal to the number of scanning lines, and a word line driver section for selecting and driving the word lines being integrated and formed on the substrate. In the present invention, the memory cell section is configured as a memory array corresponding to the dot arrangement of the display driver, and image signals required to display one screen are stored, thereby reducing the amount of data exchanged with the outside and achieving low power consumption. In addition, in order to perform storage using an array configuration, a word line driver section for selecting and driving word lines, the number of which is equal to the number of scanning lines, is integrated and formed on the substrate. In the display device according to the invention of claim 11, the scanning line driver section selects the scanning lines based on address signals indicating the display position and the storage position,
Further, the word line driver unit selects the word line. In the present invention, scanning lines and word lines can be selected randomly by an address signal, ensuring flexibility in storage or display in the column direction. In a display device according to claim 12, the same address signal is input to the scanning line driver unit and the word line driver unit. In the present invention, in order to simplify wiring, the scanning line driver unit and the word line driver unit can share the same lines. As a result, the same address signal is input at the same timing. In a display device according to claim 13, independent address signals are input to the scanning line driver unit and the word line driver unit. In the present invention, in order to increase flexibility in storage and display operations, independent address signals are input to the scanning line driver unit and the word line driver unit, allowing, for example, different operation timings. In a display device according to the invention of claim 14, the scanning line driver section performs a selective drive operation of the scanning lines based on the address signal only while a scanning line driver control signal is being input, and the word line driver section performs a selective drive operation of the word lines based on the address signal only while a word line driver control signal is being input. In this invention, in order to simplify wiring while increasing the degree of freedom in storage and display operations, the scanning line driver section performs a selective drive operation of the scanning lines based on the address signal only while a scanning line driver control signal is being input, and the word line driver section can perform a selective drive operation of the word lines based on the address signal only while a word line driver control signal is being input. In a display device according to the invention of claim 15, the column decoder section
The address signal is used to select a memory cell for storing an input image signal. In the present invention, the column decoder unit can randomly select a memory cell for storing an image signal based on the address signal, ensuring flexibility in storage or display in the row direction. In a display device according to claim 16, three dots provided for displaying the light source colors red, blue, and green are considered to be one pixel, the image signal is input in pixel units, and the column decoder unit selects memory cells for one pixel. In the present invention, when the display device performs color display, three dots provided for displaying the light source colors red, blue, and green are considered to be one pixel, and image signals are input in pixel units, which are the display change units, and the column decoder unit selects memory cells for one pixel based on the input. In a display device according to claim 17, three dots provided for displaying the light source colors red, blue, and green are considered to be one pixel, the image signal is input in units of multiple pixels, and the column decoder unit selects memory cells for multiple pixels. In the present invention, when the display device performs color display, in order to reduce the drive frequency, an image signal is input in units of multiple pixels, with three dots provided to display the light source colors red, blue, and green as one pixel, and the column decoder unit selects memory cells for multiple pixels based on the input. In the display device according to the invention of claim 18, the input wiring for the image signal to be stored in the memory cell unit and the column selection switch unit are formed on the opposite side of the memory cell unit from the display driver unit. In the present invention, in order to reduce power consumption by reducing the number of wiring intersections and to prevent noise superposition due to the effects of switching, etc., the input wiring for the image signal and the column selection switch unit are formed on the opposite side of the memory cell unit from the display driver unit. In the display device according to the invention of claim 19, the memory cell unit is
The memory cells are allocated in accordance with the row length of the display driver, and are formed in a multi-stage configuration. In the present invention, when the memory cells cannot be allocated in accordance with the row length of the display driver, for example, due to an increase in the number of memory cells equivalent to one dot caused by an increase in the number of gradations, the memory cells are formed in a multi-stage configuration. A display device according to the invention of claim 20 has word lines whose number is an integer multiple of the number of scanning lines, and the memory cell section is formed in a memory array in which memory cells sufficient to store image signals for controlling the display of one row of dots of the display driver are divided and connected to the integer multiple of word lines. In the present invention, when the memory cells cannot be allocated in accordance with the row length of the display driver, for example, due to an increase in the number of memory cells equivalent to one dot caused by an increase in the number of gradations, the memory cells are formed in a plurality of rows. In a display device according to the invention of claim 21, the memory cell section is
The display device is configured to be composed of a memory array in which memory cells of a number sufficient to store image signals for performing display control for multiple rows of dots of the display driver are allocated in accordance with the length of the row direction of the display driver. In the present invention, when multiple rows of memory cells are allocated in accordance with the length of the row direction of the display driver, in order to save space, the display device is configured to be composed of a memory array in which memory cells of a number sufficient to store image signals for performing display control for multiple rows of dots of the display driver are allocated in accordance with the length of the row direction of the display driver.
The display device is configured with a memory array in which memory cells sufficient to store image signals for controlling the display of multiple rows of dots of the display driver are allocated so that the row length is equal to or less than the row length of the display driver. In the present invention, when multiple rows of memory cells are allocated to correspond to the row length of the display driver, in order to save space, the memory array is configured with memory cells sufficient to store image signals for controlling the display of multiple rows of dots of the display driver, allocated so that the row length is equal to or less than the row length of the display driver. In a display device according to claim 23, a timing controller unit that controls the timing of transmitting the address signal and a memory controller unit that controls the transmission of the image signal are further integrated and formed on the substrate. In the present invention, all peripheral circuits required for display control are systematically formed integrally on the same substrate. In a display device according to claim 24, a D/A converter is provided between the display driver and the memory cell unit, so that the image signal, which is a digital signal stored in the memory cell unit, is converted into an analog signal before being supplied to the display driver. In the present invention, in order to display using a display driver compatible with analog signals, a D/A converter is provided between the display driver and the memory cell unit, and the image signal converted into an analog signal by the D/A converter is supplied to the display driver. A display device according to the invention of claim 25 directly connects the display driver and the memory cell unit, thereby supplying the image signal, which is a digital signal stored in the memory cell unit, to the display driver. In the present invention, in order to display using a display driver compatible with digital signals, no D/A converter or the like is provided between the display driver and the memory cell unit, and the image signal is supplied to the display driver as a digital signal. In the display device according to the invention of claim 26, the display driver performs digital driving using area gradation, time-division gradation, or a combination thereof. In the present invention, the digital signal-compatible display driver performs display using area gradation, time-division gradation, or a combination of both. Best Mode for Carrying Out the Invention Embodiment 1. FIG. 1 is a block diagram showing the concept of a system including a display device according to a first embodiment of the present invention. FIG. 1 shows a concept called a system-on-panel (SOP). SOP is a display device that has peripheral circuits etc. mounted on a glass substrate, and is also
This is a concept of integrating TFTs and peripheral circuits using polycrystalline silicon or the like, without using chips such as C. This allows the panel to be directly connected to the CPU, and also allows for low cost, high reliability, and space saving. In FIG. 1, the image signal source 110 is made up of a CPU 110A that transmits display data. Here too, as with the conventional configuration shown in FIG. 11, the display data is transmitted as an image signal, which is digital data. If the image signal is digital data,
There is no need for D/A conversion on the panel 1 side, which contributes to miniaturization and low power consumption. The panel 1 also includes an active matrix LCD section 2, a scanning line driver 3, a digital data driver 4, a frame memory section 5, a memory controller 6, and a digital data driver 7.
and a timing controller 7. Active matrix LC
The D section 2 corresponds to the display driver section in the present invention. Figure 2 is a diagram showing the panel 1 in detail. Active matrix LCD section 2
is the part that actually displays images using active elements such as TFTs and diodes. The active matrix LCD part 2 has an array of i x j pixels. Since this embodiment is intended for a color display, the light source color R (R
ed), G (Green) and B (Blue) dots (also called sub-pixels)
In the case of a monochrome display, a pixel is equal to a dot.
Each dot area includes data lines, scanning lines, and active elements (e.g., switching elements such as transistors and diodes) arranged at their intersections. Each active element has a pixel electrode, which forms a capacitance between the pixel electrode and the opposing electrode via liquid crystal. The voltage applied between the pixel electrode and the opposing electrode controls the optical rotation of the liquid crystal molecules, thereby controlling the display of each dot. Furthermore, even when the active element is switched off, the pixel electrode can maintain its display state until the next refresh (when the display data is rewritten) thanks to the stored charge. The switching operation of the active elements and the supply of charge to the pixel electrode are controlled by driving (supplying current to) the data lines and scanning lines. The scanning line driver 3 controls the driving of the scanning lines. The scanning line driver 3 is composed of a row decoder 31 and a scanning line driving buffer 32. The row decoder 31 selects the scanning line to be driven based on input address data. The scanning line driving buffer 32 actually drives the scanning line selected by the row decoder 31. The digital data driver 4 controls the driving of the data lines. The digital data driver 4 is composed of a k-bit DAC unit 41 as a D/A converter. Before describing the operation of the k-bit DAC unit 41, the frame memory unit 5 will be described. The frame memory unit 5 is composed of a column decoder 51, an input control circuit 52, a column selection switch unit 53, a memory row decoder 54, a word driver 55, a memory cell unit 56, and a sense amplifier unit 57. The column decoder 51 selects one pixel from one row (line) of pixels (j pixels) based on input address data. This also selects the data line to be driven. The input control circuit 52 controls the image signal (k×3) for one pixel transmitted in parallel from the memory controller 6. The column selection switch unit 53 is provided in units of one pixel image signal (k×3), and the number of column selection switch units 53 is the same as the number of pixels in one line (i.e., k×3×j). Each column selection switch switches based on the selection of the column decoder 51 and the image signal to drive a bit line. Here, the input control circuit 52 and the column selection switch section 53 are arranged on the opposite side of the active matrix LCD section 2 with the memory cell section 56 in between. This reduces the number of crossings of wiring, resulting in a simple and low power consumption. Moreover, the operation of the input control circuit 52 and the column selection switch section 53
Since noise is not superimposed on the analog-driven LCD 2, a low-noise display can be achieved. The memory row decoder 54 selects a word line based on input address data to store data in an arbitrary memory cell of the memory cell section 56 that constitutes a memory array, as will be described later. The word driver 55 actually drives the word line selected by the memory row decoder 54. Therefore, an image signal is stored as display data for a pixel in k×3 memory cells that are connected to the word line selected by the memory row decoder 54 and that correspond to the pixel selected by the column decoder 51. The memory cell section 56 has k×3×i×j memory cells, with i rows×k
The memory array is composed of 3×j columns. The number of memory cells is i
This is the number of memory cells required to display each of the R, G, and B dots at 2k levels of brightness on a display with 2×j pixels. In Figure 2, k = 3, allowing for 8 levels of brightness. This number of memory cells is the minimum number required to store one screen's worth of image signals. For example, some circuits are configured with redundant memory cells to ensure operational stability. The closer the size of the glass substrate is to the size of the active matrix LCD section 2, which is the actual display area, the more space can be saved. In other words, arranging the memory cells so that the row length of the memory cell section 56 is equal to or less than the row length of the active matrix LCD section 2 allows for the most efficient arrangement of one column of memory cells in a minimal space. Therefore, if the row length of the memory cells required to control the display of one dot is equal to or less than the pitch of each dot, the row length of the entire frame memory section 5 will be equal to or less than the row length of the active matrix LCD section 2. Therefore, in Figure 2, the row length of k-bit memory cells is designed to be equal to the pitch of each dot. Furthermore, each sense amplifier (or selection switch) of the sense amplifier section 57 and each k-bit DAC of the k-bit DAC section 41 are also designed based on the pitch of each dot. The number of rows in the memory array is set to be the same as the number of scanning lines, i, so that the frame memory section 5 can store one screen's worth of display data. Therefore, pixels at each display position can be stored in correspondence with memory cells provided for each dot. If space saving is the only goal, it is sufficient to have at least one row of memory cells; there is no need to configure a memory array with the number of rows corresponding to the number of scanning lines. However, in order to reduce the amount of data transmitted throughout the system and achieve low power consumption, memory cells sufficient to store one screen's worth of display data in correspondence with each other are required. Therefore, the CPU 110A only needs to transmit image signals for the number of display data for the pixels to be rewritten, and if no rewriting is to be performed, the memory cell section 5
The digital data driver 4 can handle the image signal data stored in the memory cell section 56 as is. Each sense amplifier constituting the sense amplifier section 57 is connected to each column (bit line). Here, sense amplifiers are used when each memory cell in the memory cell section 56 is composed of a dynamic memory. When each memory cell is composed of a static memory, a selection switch is used instead of a sense amplifier. The k-bit DAC section 41 constituting the digital data driver 4 has 3×j k
Each k-bit DAC receives digital data based on image signals stored in k memory cells via k bit lines.
The k-bit DAC converts the value based on the data into a gradation and drives the data line in accordance with that gradation. In LCDs, AC drive is necessary for the purpose of extending the life of the liquid crystal. Therefore, digital data cannot be used as is and must be converted to analog. In this way, display control based on display data is performed at the dots at the intersections of the driven scanning lines and data lines. Here, the digital data driver 4 and frame memory unit 5 in the present invention are directly connected (integrated), and the stored digital data is directly used to drive the data line. Therefore, for convenience (in relation to Figure 1), the digital data driver 4 is configured with a k-bit DAC unit 41, and the frame memory unit 5 is configured with a column decoder 51,
The memory controller 6 controls the display data sent from the CPU 110A as k×3 image signals to be stored in the frame memory 5. The timing controller 7 has at least an address buffer 71, and controls the data sent from the CPU 110A as k×3 image signals to be stored in the frame memory 5.
A sends address signals to the row decoder 31, column decoder 51, and memory row decoder 54 to store and display the display data sent from A. When the memory is configured as a chip, the problem is how densely packed it can be within the chip and how well it can be laid out taking into account wiring, etc. When peripheral circuits such as memory are configured on a glass substrate, the concept is different. The largest area on the glass substrate is occupied by the active matrix LC which is the actual display part.
D section 2. Moreover, the pixel pitch (and therefore the overall size) is fixed. Therefore, the issue is how to efficiently layout the system, including peripheral circuits, in accordance with that size. If space saving is considered without considering power consumption, the number of memory cells can be reduced, but to achieve low power consumption, memory cells sufficient to store one screen's worth of data are required. Therefore, in this embodiment,
This aims to provide the most efficient layout after configuring peripheral circuits to achieve low power consumption. Next, the display operation will be described with reference to FIG. 2. The CPU 110A transmits display data when changing the display. Therefore, if the image does not change, display data is not transmitted. When changing the display, it transmits an address signal indicating the position (pixel) where the display is to be changed. It also transmits an image signal of the display data. The frame memory unit 5 is provided with a number of word lines corresponding to the number of scan lines, so that one screen's worth of display data (image signal) corresponding to each dot can be stored. Furthermore, a row decoder 31 and a memory row decoder 54 are provided to enable selection of scan lines and word lines. Therefore, sequential scanning is not required, and random scan lines can be selected and driven in response to address signals, which is convenient when rewriting display data as needed. Furthermore, to simplify wiring and reduce circuit area to save space, the same address signal is transmitted to the row decoder 31 and the memory row decoder 54.
are input to the frame memory unit 5, and are stored and displayed at the same timing in the corresponding parts. The column decoder 51 can also select pixels at random according to the address signal, so there is no need to write sequentially to pixels (dots) on the same scanning line, and random writing can be performed. When the display is not changed, the digital data of the image signal stored in the frame memory unit 5 is used as is for display, and no data is exchanged with the CPU 110A. However, since the LCD must be AC driven as mentioned above,
It is necessary to drive the display while refreshing it at least at the minimum required frequency using pixel inversion driving. This control is performed by the scanning line driver 3 and the digital data driver 4. Lowering the frequency can reduce power consumption, but
Flicker occurs due to penetration voltage, etc. Therefore, in order to reduce power consumption while making flicker less noticeable, for example, a 30 Hz frequency is required for still images.
(The liquid crystal is driven at 15 Hz) to maintain the display state. As for the frame memory section 5, if the memory cells are configured as static memories, there is no need to rewrite (refresh) data, but if they are configured as dynamic memories, they need to be refreshed at a timing that allows the stored data to be maintained. As described above, according to the first embodiment, when a system including not only the display section but also the peripheral circuits is to be formed integrally on a substrate, as in the SOP, the length in the row direction of the memory cell section 56 of the frame memory section 5 when the number of memory cells required to control the display of one dot is arranged is set to be equal to or less than the pitch of each dot, that is, the length in the row direction of the memory cell section 56 is set to be equal to or less than the pitch of each dot.
The memory cells are arranged so that their row length is less than the D section 2, allowing for efficient, space-saving arrangement of one row of memory cells. The same is true for the sense amplifier section 57 and the k-bit DAC section 41, resulting in space-saving design. The number of rows in the memory array is set to the same number (i) of scanning lines, allowing the frame memory section 5 to store one screen's worth of display data (image signals). This allows pixels at each position to correspond to memory cells in the memory cell section 56, allowing for one screen's worth of data to be stored. The CPU 110A only needs to transmit image signals for the display data of the pixels to be rewritten. This reduces the amount of data transmitted throughout the system, achieving low power consumption and achieving the most efficient, space-saving design. Furthermore, the row decoder 31 and memory row decoder 54 are provided, allowing for selection of scanning lines and word lines to be driven based on address signals. This eliminates the need for sequential scanning, allowing random selection and driving of scanning lines in response to address signals, making it convenient for rewriting display data as needed. Furthermore, since the same address signal is input to the row decoder 31 and the memory row decoder 54, and the corresponding parts store and display data at the same timing, space can be saved by simplifying the wiring and reducing the circuit area. Furthermore, the column decoder 51 can also select pixels randomly according to the address signal, eliminating the need to write data sequentially to pixels (dots) on the same scanning line. This allows random writing, which is convenient for rewriting display data as needed. Furthermore, since the input control circuit 52 and the column selection switch section 53 are arranged on the opposite side of the memory cell section 56 from the active matrix LCD section 2, crossing of the wiring is reduced, resulting in a simpler design and lower power consumption. Furthermore, the operation of the input control circuit 52 and the column selection switch section 53 allows the analog-driven LCD 2 to select pixels (dots) sequentially.
No noise is superimposed on the display, thereby achieving low noise in the display. Furthermore, the memory controller 6 and timing controller 7 are also formed integrally with the panel 1, so that the panel 1 can be directly connected to the CPU 110A, making the entire system low cost, highly reliable, and space-saving. Embodiment 2. Figure 3 is a detailed diagram of a panel 1A according to a second embodiment of the present invention.
The panel 1A of FIG. 3 differs from the panel 1 of FIG. 2 in that address signals are input to the row decoder 31 and the memory row decoder 54 independently of each other.
Therefore, the timing of the storage operation and the timing of the display operation can be made different. Although the drive frequency is higher than when the storage and display operations are performed simultaneously, various drive operations can be performed, such as sending address data to the memory row decoder 54 at a certain timing to perform a storage operation, and then sending address data to the row decoder 31 at the next timing to perform display. As described above, according to the second embodiment, address signals are input independently to the row decoder 31 and the memory row decoder 54, thereby increasing the flexibility in selecting a drive method. Embodiment 3. Figure 4 is a diagram showing in detail a panel 1B according to a third embodiment of the present invention.
The panel 1B in FIG. 4 differs from the panel 1 in FIG. 2 in that the address buffer 7
1 to the row decoder 31A and the memory row decoder 54A, respectively, and a scanning line selection control signal line and a word line selection control signal line are wired to transmit the scanning line selection control signal and the word line selection control signal.
The same address signal is input to each of the row decoder 31A and the memory row decoder 54A. However, the row decoder 31A can select a scan line only while the scan line selection control signal is ON. Similarly, the memory row decoder 54A can select a word line only while the word line selection control signal is ON. Therefore, by controlling the ON/OFF of these signals, the storage operation and the display operation can be performed at different timings. As described above, according to the third embodiment, the scan line selection period of the row decoder 31A is limited based on the scan line selection control signal, and the word line selection period of the memory row decoder 54A is limited based on the word line selection control signal. This increases the flexibility in selecting the drive method for the storage operation and the display operation. Therefore, various drive control methods can be performed. Embodiment 4. FIG. 5 is a detailed diagram of a panel 1C according to a fourth embodiment of the present invention.
The panel 1C of FIG. 5 differs from the panel 1B of FIG. 4 in that the column selection switch section 53A, the sense amplifier section 57A, and the memory cell section 56A are laid out in consideration of the case where k=6.
Since k=6, panel 56A handles twice as many signals as column decoder 51 and input control circuit 52, respectively (it differs from panel 1 of FIG. 2 in that it also has scan line selection control signal lines and word line selection control signal lines). As mentioned above, arranging memory cells so that the row length of memory cell section 56 is equal to or less than the row length of active matrix LCD section 2 allows for the most efficient, space-saving arrangement of one column of memory cells. Therefore, it is ideal to arrange k-bit memory cells so that the row length of memory cell section 56A is equal to or less than the pitch of each dot. However, the value of k increases when the gradation range is increased (k=6 results in 64 gradations, allowing for the display of approximately 260,000 colors). In other words, the number of memory cells required to store one dot of data increases. Therefore, if k-bit memory cells were simply arranged, the resulting layout would be wider than the dot pitch. Therefore, in this embodiment, memory cell section 56A has a multi-stage memory array, and the memory cells are arranged so that the row length of memory cell section 56A is equal to or less than the row length of active matrix LCD section 2, and they are integrally formed. Alternatively, the number of rows in the memory array may be an integer multiple of the number of scan lines, with each dot consisting of multiple rows of memory cells. In this case, the k-bit DAC unit 41 processes the digital data in a time-division manner to drive the data lines. As described above, according to the fourth embodiment, when the row length of k-bit memory cells cannot be made equal to or less than the pitch of each dot, the memory array is configured in multiple stages, and the layout is such that the row length of the memory cell unit 56A is equal to or less than the row length of the active matrix LCD unit 2, and the memory cell unit 56A and the k-bit DAC unit 41 are integrally formed. This facilitates wiring between the memory cell unit 56A and the k-bit DAC unit 41 while saving space. Embodiment 5. FIG. 6 is a detailed diagram of a panel 1D according to a fifth embodiment of the present invention.
The panel 1D of FIG. 6 differs from the panel 1B of FIG. 4 in that the memory cell unit 56
The fourth embodiment is characterized by the arrangement of memory cells in the pixel array 51B. Also, image signals for two pixels are input simultaneously, and the column decoder 51B can select two pixels simultaneously. Furthermore, the input control circuit 52A and the column selection switch section 53A handle twice as many signals as the input control circuit 52 and the column selection switch section 53A, respectively. In the fourth embodiment, a case was described in which the length of memory cells arranged for k bits is longer than the pixel pitch. Conversely, if the length of memory cells arranged for multiple pixels (dots) is equal to or less than the pitch of one pixel (dot), the length of memory cells arranged for multiple pixels (dots) is equal to or less than the pitch of one pixel (dot).
By arranging and laying out memory cells corresponding to a pitch of one pixel (dot) and forming them integrally, it is possible to further save space. However, even in this case, word lines are not shared, but rather the same number of word lines as the number of scanning lines are provided, and memory cells corresponding to each dot are provided. In this case, however, it is possible to share the sense amplifier section 57. Also, as shown in Figures 2 to 5, in the first to fourth embodiments, the column decoder 51 is a single
In the fifth embodiment, however, when the length of memory cells for a plurality of pixels (dots) arranged is equal to or less than the pitch of one pixel (dot), the memory cells for a plurality of pixels (dots) are arranged in a layout corresponding to the pitch of one pixel (dot) and are integrally formed, thereby further saving space.
Moreover, the sense amplifier section 57 can be shared. Also, since the column decoder 511 is designed to be able to select two pixels simultaneously, the driving frequency can be lowered, and power consumption can be reduced, although the wiring becomes more complex. Furthermore, sufficient operation can be obtained even when driven by active elements with inferior characteristics to single-crystal FETs. Embodiment 6. Figure 7 is a detailed diagram of a panel 1E according to a sixth embodiment of the present invention.
The panel 1E in FIG. 7 differs from the panel 1 in FIG. 2 in that the actual display section is a digital-compatible active matrix OEL section 8 as a display driver. Also, it does not use a k-bit DAC section 41. OEL (Organic Electro Luminescent) is,
This refers to an organic EL element. Unlike liquid crystal, this OEL element is a self-emitting element. Therefore, it has the following characteristics and is an element that is expected to be used in the fields of displays and other fields. (1) Wide viewing angle (2) Lightweight and thin design possible (3) High contrast ratio (4) Low power consumption (no need for backlight) (5) Possibility of multicolor by molecular design (6) High resolution display possible due to current driving Figure 8 is a diagram showing the circuit layout of the active matrix OEL section 8. Figure 8 shows the circuit layout of the active matrix OEL section 8.
The figure shows the arrangement of pixels. As mentioned above, in LCDs, AC driving is necessary to extend the life of the liquid crystal. Therefore, digital data is generally not used as is, but is converted to analog. Normally, when OEL is made to emit light, digital data is converted to analog, and the converted analog signal (data) is stored in a capacitor or the like using, for example, a two-transistor system. Then, the output current of the transistor amplifier is controlled by the converted analog data, and the OE
However, the OEL is driven by direct current (DC drive).
As shown above, digital data such as image signals stored in each memory cell can be handled as they are. Next, a method for displaying display data stored in the frame memory will be described.
An example will be given for the dot (R in the first pixel column). Seven OEL elements are provided in R1 to represent eight gradations. These seven OEL elements are divided into one OEL element, two OEL elements, and four OEL elements, respectively, and are connected to the corresponding bit lines R1S, R1T, and R1U. The difference in gradation is represented by the light-emitting area. Therefore, at gradation 0, R1S, R1T, and R1U are not driven, and none of the elements emit light. At gradation 1, R1S is driven, causing one OEL element to emit light. Similarly, at gradation 2, R1T is driven, causing two OEL elements to emit light, and at gradation 3, R1S and R1T are driven, causing three OEL elements to emit light.
Gradation is expressed by this combination. The same applies to G and B dots. Here, since the OEL can be DC driven, if there is no need to change the display, there is usually no need to refresh by inversion driving or the like. However, since a dynamic circuit is used in FIG. 8, even if there is no change in the display, it is necessary to refresh based on the data stored in each memory cell of the frame memory unit 5 at regular intervals to maintain the display. FIG. 7 is written in correspondence with FIG. 2, which is the first embodiment, but the second to fifth embodiments are also different.
In the display device employing the panel of each of the embodiments, an active matrix optical
It goes without saying that the EL unit 8 can be applied. In addition, in the sixth embodiment, an example of digital driving by so-called area gradation is shown, but even if the configuration is such that digital driving is performed by time division driving, for example,
Alternatively, a digital drive configuration combining area gradation and time-division gradation may be used. To achieve time-division drive, an on/off signal may be applied to the OEL elements for different periods corresponding to the digital signal for each bit of each pixel, synchronized with a timing signal repeated at a constant cycle. As described above, the sixth embodiment uses self-luminous OEL elements for display, thereby not only achieving the effects of the first to fifth embodiments but also achieving low power consumption and weight reduction by eliminating the need for a backlight. Moreover, since the digital data stored in the frame memory unit 5 can be used directly without analog conversion to display gradations, a circuit such as a DAC is not required, thereby reducing the space required for peripheral circuits and power consumption. Embodiment 7. FIG. 9 is a detailed diagram of a panel 1F according to a seventh embodiment of the present invention.
The panel 1F of FIG. 9 differs from the panel 1E of FIG. 7 in that the part that actually displays is an active matrix LCD section 2A that serves as a display driver. The panel 1F of FIG. 9 differs from the panel 1 of FIG. 2 in that the part that actually displays is a digital-compatible active matrix LCD section 2A. Also, the panel 1F of FIG. 9 does not use a k-bit DAC section 41. FIG. 10 is a diagram showing the circuit layout of the active matrix LCD section 2A.
0 indicates the arrangement of two pixels. As mentioned above, in LCDs, AC driving is required to extend the life of the liquid crystal, so digital data is generally not used as is but is converted to analog. As will be described later, the configuration of Figure 10 allows the LCD to handle digital data such as image signals stored in each memory cell as is. Next, R1 will be used to explain the method of displaying display data stored in the frame memory.
An example of the dot (R in the first pixel row) will be described below. R1 has three liquid crystal regions, each covered by an independent pixel electrode, to represent eight gray levels.
The three liquid crystal regions have an area ratio of 1:2:4, and are connected to R1S, R1T, and R1U corresponding to each bit line. Furthermore, all areas of the active matrix LCD section 2A other than the liquid crystal regions, i.e., all areas other than the pixel electrodes, are light-shielded. Therefore, the difference in gradation is expressed by the area of the liquid crystal regions in a transparent state. Therefore, at gradation 0, R1S, R1T, and R1U are not driven, and all liquid crystal regions are in a light-shielding state. At gradation 1, R1S is driven, and the liquid crystal region with an area ratio of 1 is in a transparent state. Similarly, at gradation 2, R1T is driven, and the liquid crystal region with an area ratio of 2 is in a transparent state, and at gradation 3, R1S and R1T are driven, and the liquid crystal regions with an area ratio of 1 and 2 are in a transparent state. The gradation is expressed by this combination. The same applies to the G and B dots. In this embodiment, a common power supply line V is used to apply voltage to each liquid crystal region.
A square wave is supplied to the LC. The square wave voltage supplied to the common power supply line VLC is a voltage that can fully activate the liquid crystal at both positive and negative potentials, and the frequency of the square wave is the same as the frequency of AC drive in a normal liquid crystal display device. This realizes a digital-compatible active matrix LCD section 2A. Note that, in FIG. 10 of this embodiment, as in FIG. 8 of the sixth embodiment, a dynamic circuit is used, so that it is necessary to refresh the display based on the data stored in each memory cell of the frame memory section 5 at regular intervals to maintain the display. Also, although FIG. 9 is written in correspondence with FIG. 2 of the first embodiment, it is different from the second embodiment in that a dynamic circuit is used.
It goes without saying that the digital-compatible active matrix LCD section 2A can be applied to the display devices employing the panels of the seventh to fifth embodiments. And, although the seventh embodiment has been described assuming a transmissive LCD, the same concept can be applied to a reflective LCD.
In this case, devices can be arranged under the pixel electrodes, so that more complex circuits can be realized, which is advantageous in achieving a multi-bit configuration.
Alternatively, a configuration may be adopted in which area gradation and time-division gradation are combined to perform digital driving. To achieve time-division driving, an on/off signal is applied to the liquid crystal in a different period for each bit corresponding to the digital signal for each bit of each pixel, synchronized with a timing signal repeated at a constant cycle. As described above, according to the seventh embodiment, gradation display can be performed using the digital data stored in the frame memory unit 5 as is without analog conversion, eliminating the need for circuits such as a DAC, thereby reducing the space required for peripheral circuits and reducing power consumption. Embodiment 8. While the above-described embodiments have been described assuming a color display, the present invention can also be used with monochrome displays. According to the inventions of claims 1 and 2, when not only TFTs but also peripheral circuits are integrally formed on polycrystalline silicon, not only the column decoder section, column selection switch section, and data line driver section, but also the memory cells of the memory cell section, the number of which is sufficient to store image signals for at least one row of dots for display control of the display driver section, are allocated in accordance with the row length of the display driver section (for example, the column decoder section, column selection switch section, data line driver, and memory cell section are allocated so that their row length is equal to or less than the row length of the display driver section), so that one column of memory cells can be arranged efficiently and in a space-saving width. Also, according to the inventions of claims 3 and 4, when a display driver circuit for controlling display using organic EL elements is integrally formed on polycrystalline silicon, not only the column decoder section, column selection switch section, and data line driver section, but also the memory cells of the memory cell section, the number of which is sufficient to store image signals for at least one row of dots for display control of the display driver section, are allocated in accordance with the row length of the display driver section (for example, the column decoder section, column selection switch section,
The data line driver section and the memory cell section are allocated so that their row direction lengths are equal to or less than the row direction length of the display driver section), so that one column of memory cells can be arranged efficiently in a space-saving width. Also, according to the inventions of claims 5 and 6, when a display driver circuit that controls display using liquid crystal is integrally formed on polycrystalline silicon together with peripheral circuits, not only the column decoder section and the column selection switch section but also memory cells of the memory cell section in a number sufficient to store image signals for controlling display of at least one row of dots of the display driver section are allocated in accordance with the row direction length of the display driver section (for example, the column decoder section, the column selection switch ... in accordance with the row direction length of the display driver section), so that one column of memory cells can be arranged efficiently in a space-saving width.
Since the EL elements are DC-driven, digital image signals can be directly used, eliminating the need for circuits such as DACs. Furthermore, according to the inventions of claims 7 and 8, when a display driver circuit for controlling display using organic EL elements is integrally formed on polycrystalline silicon, including peripheral circuits, not only the column decoder unit and column selection switch unit but also memory cells in a memory cell unit sufficient to store image signals for controlling display of at least one row of dots in the display driver unit are allocated in accordance with the row length of the display driver unit (e.g., the column decoder unit, column selection switch unit, and memory cell unit are allocated so that their row lengths are equal to or shorter than the row length of the display driver unit), thereby enabling an efficient, space-saving arrangement of one column of memory cells. Furthermore, since the organic EL elements are DC-driven, digital image signals can be directly used, eliminating the need for circuits such as DACs. According to the invention of claim 9, even if the number of memory cells is redundantly configured to store enough image signals to control the display of one row of dots in the display driver, the memory cells are allocated based on the row length of the display unit (e.g., the row length of the memory cell unit is allocated so that it is equal to or shorter than the row length of the display driver), thereby efficiently saving space. According to the invention of claim 10, a word line driver unit that selects and drives word lines provided in the same number as the scan lines is further integrated and formed on the substrate, and the memory cell unit is configured as a memory array corresponding to the dot arrangement of the display driver unit, and stores the image signals necessary to display one screen. This reduces the amount of data exchanged with the outside and reduces power consumption. According to the invention of claim 11, the scan line driver unit and word line driver unit can select the scan lines and word lines to be driven based on address signals, eliminating the need for sequential scanning and allowing random selection and driving of scan lines in response to address signals, which is convenient for rewriting display data as needed. According to the invention of claim 12, the scanning line driver section and the word line driver section share the same lines, thereby simplifying the wiring and reducing the circuit area, thereby saving space. According to the invention of claim 13, independent address signals are input to the scanning line driver section and the word line driver section, thereby increasing the flexibility of storage and display operations. According to the invention of claim 14, the scanning line driver section performs a selective drive operation of the scanning lines based on the address signal only while the scanning line driver control signal is input, and the word line driver section performs a selective drive operation of the word lines based on the address signal only while the word line driver control signal is input, thereby increasing the flexibility of selection of drive methods for storage and display operations. Therefore, various drive control methods can be performed. According to the invention of claim 15, the column decoder section can randomly select memory cells for storing image signals based on the address signal, thereby eliminating the need to sequentially write to dots on the same scanning line and allowing random writing, which is convenient when rewriting display data as needed. According to the invention of claim 16, an image signal is input in units of one pixel, and the column decoder unit selects memory cells for one pixel, which is the unit for changing the display, based on the input, which is convenient. According to the invention of claim 17, an image signal is input in units of multiple pixels, and the column decoder unit selects memory cells for multiple pixels based on the input. This makes the wiring more complex, but it allows for a lower drive frequency and reduced power consumption. Furthermore, sufficient operation can be achieved even when driven by active elements with inferior characteristics to single-crystal FETs. According to the invention of claim 18, the image signal input wiring and column selection switch unit are formed on the opposite side of the memory cell unit from the display driver unit, thereby reducing wiring intersections and reducing power consumption, and preventing noise superimposition on the display screen due to switching effects, etc. According to the invention of claim 19, a multi-stage configuration is used.
Since the memory cells are formed in multiple rows, even when the memory cells cannot be allocated to correspond to the row length of the display driver due to an increase in memory cells by one dot due to an increase in the number of gradations, for example, the length in the column direction increases, but the length in the row direction can be reduced. Furthermore, according to the inventions of claims 21 and 22, when multiple rows of memory cells are allocated to correspond to the row length of the display driver, memory cells are allocated in a number sufficient to store image signals for display control of multiple rows of dots of the display driver (for example, the memory cells are allocated so that the row length is equal to or less than the row length of the display driver).
Since the display device is configured with a memory array, further space savings can be achieved. Furthermore, according to the invention of claim 23, a timing controller that controls the timing of sending address signals and a memory controller that controls the sending of image signals are further integrated and formed on a substrate, and all peripheral circuits required for display control are systematically formed on the same substrate, thereby achieving low cost, high reliability, and space savings for the entire system. Furthermore, according to the invention of claim 24, a D/A converter is provided between the display driver and the memory cell unit, and image signals converted into analog signals are supplied to the display driver. This allows display to be performed using a display driver compatible with analog signals. Furthermore, according to the inventions of claims 25 and 26, the display driver and the memory cell unit are directly connected, and digital image signals are directly supplied to the display driver. This allows display to be performed using a display driver compatible with digital signals, while also reducing power consumption.

[Brief explanation of the drawings]

FIG. 1 is a block diagram showing the concept of a system including a display device according to a first embodiment of the present invention. FIG. 2 is a diagram showing details of panel 1. FIG. 3 is a diagram showing details of panel 1A according to a second embodiment of the present invention. FIG. 4 is a diagram showing details of panel 1B according to a third embodiment of the present invention. FIG. 5 is a diagram showing details of panel 1C according to a fourth embodiment of the present invention. FIG. 6 is a diagram showing details of panel 1D according to a fifth embodiment of the present invention. FIG. 7 is a diagram showing details of panel 1E according to a sixth embodiment of the present invention. FIG. 8 is a diagram showing the circuit layout of an active matrix OEL section 8. FIG. 9 is a diagram showing details of panel 1F according to a seventh embodiment of the present invention. FIG. 10 is a diagram showing the circuit layout of an active matrix LCD section 2A. FIG. 11 is a block diagram of a system for displaying images using a display device based on a TFT display.

───────────────────────────────────────────────────── (Note) This publication is based on the publication published internationally by the International Bureau of Patents (WIPO). The effect of the international publication of the Japanese patent application (Japanese utility model registration application) related to this publication arises pursuant to Article 184-10, Paragraph 1 of the Patent Act (Article 48-13, Paragraph 2 of the Utility Model Act) and is unrelated to this publication.

Claims (26)

[Claims] a memory cell section allocated to the length of the row direction of the display driver section and having a number of memory cells allocated to the length of the row direction of the display driver section, the number of which is sufficient to store an image signal for at least one row of dots of the display driver section; a column decoder section allocated to the length of the row direction of the display driver section and selecting the memory cells for storing an input image signal; a column selection switch section allocated to the length of the row direction of the display driver section and performing switching based on the selection of the column decoder section and the image signal, causing the image signal to be stored in the memory cell selected by the column decoder section; and a data line driver section allocated to the length of the row direction of the display driver section and driving the data lines based on the image signal stored in the memory cell section, the [Claim 2] A display drive section which forms a plurality of scanning lines and a plurality of data lines in a lattice pattern corresponding to dots which are the smallest unit of display, and provides active elements corresponding to each intersection, and controls display using liquid crystal by driving the scanning lines and data lines; a scanning line driver section which is allocated so that its column length is equal to or less than the column length of said display drive section, and which selects and drives said scanning lines; a memory cell section which is allocated so that its row length is equal to or less than the row length of said display drive section, and which has a number of memory cells which can store an image signal for at least performing display control for one row of dots of said display drive section; a column decoder section which is allocated so that its row length is equal to or less than the row length of said display drive section, and which selects said memory cells which will store an input image signal; a column selection switch section which is allocated so that its row length is equal to or less than the row length of said display drive section, and which switches based on the selection of the column decoder section and the image signal, and causes the image signal to be stored in a memory cell selected by the column decoder section; and a data line driver section which is allocated so that its row length is equal to or less than the row length of said display drive section, and which drives said data lines based on the image signal stored in said memory cell section. and a display device comprising: a display element; a display device including: a display element; a display element; a memory cell section allocated to the length of the display driver in the row direction and having a number of memory cells allocated to the length of the display driver in the row direction, the number of which is sufficient to store an image signal for at least one row of dots of the display driver; a column decoder section allocated to the length of the display driver in the row direction and selecting the memory cells for storing an input image signal; a column selection switch section allocated to the length of the display driver in the row direction and performing switching based on the selection of the column decoder section and the image signal, causing the image signal to be stored in the memory cell selected by the column decoder section; and a data line driver section allocated to the length of the display driver in the row direction and having a number of memory cells allocated to the length of the display driver in the row direction and having a number of memory cells allocated to the length of the display driver in the row direction, the number of which is sufficient to store an image signal for at least one row of dots of the display driver; [Claim 4] A display drive section which forms a plurality of scanning lines and a plurality of data lines in a lattice pattern corresponding to dots which are the smallest unit of display, provides active elements corresponding to each intersection, and controls display by driving the scanning lines and data lines to cause organic EL elements connected to the active elements to emit light; a scanning line driver section which is allocated so that its column length is equal to or less than the column length of the display drive section and which selects and drives the scanning lines; a memory cell section which is allocated so that its row length is equal to or less than the row length of the display drive section and which has a number of memory cells which can store an image signal for at least performing display control for one row of dots of the display drive section; a column decoder section which is allocated so that its row length is equal to or less than the row length of the display drive section and which selects the memory cells which will store an input image signal; and a column selection switch section which is allocated so that its row length is equal to or less than the row length of the display drive section and which performs switching based on the selection of the column decoder section and the image signal, causing the image signal to be stored in a memory cell selected by the column decoder section. a data line driver section that is allocated so that the length in the row direction is equal to or less than the length in the row direction of the display drive section and that drives the data lines based on image signals stored in the memory cell section, and [Claim 5] A display device comprising: a display driver section formed in a matrix, the display driver section having a plurality of scanning lines and a plurality of bit lines, and a liquid crystal for each dot, which is the smallest unit of display control, and the liquid crystal is provided for each dot, which is the smallest unit of display control, and the display driver section has a memory cell section, the memory cell section being allocated to correspond to the row length of the display driver section and having a number of memory cells capable of storing an image signal for at least controlling the display of one row of dots of the display driver section, the memory cells being connected to the bit lines; a column decoder section, the column decoder section being allocated to correspond to the row length of the display driver section and selecting the memory cells for storing an input image signal; and a column selection switch section being allocated to correspond to the row length of the display driver section and performing switching based on the selection of the column decoder section and the image signal, causing the image signal to be stored in the memory cell selected by the column decoder section, and [Claim 6] A display device comprising: a display driver section formed in a matrix, the display driver section having a plurality of scanning lines and a plurality of bit lines, and a liquid crystal for each dot, which is the smallest unit of display control, and the liquid crystal is provided for each dot, which is the smallest unit of display control, and the display driver section has a memory cell section in which memory cells, the number of which is sufficient to store an image signal for at least one row of dots of the display driver section, are allocated so that the row length of the memory cells is equal to or less than the row length of the display driver section, and each memory cell is connected to a bit line; a column decoder section, the row length of which is equal to or less than the row length of the display driver section, and which selects the memory cells for storing an input image signal; and a column selection switch section, the row length of which is equal to or less than the row length of the display driver section, and which switches based on the selection of the column decoder section and the image signal, and causes the image signal to be stored in the memory cell selected by the column decoder section, [Claim 7] A display device comprising: a display drive section formed in a matrix, the display drive section having a plurality of scanning lines and a plurality of bit lines, and an organic EL element for light emission control by driving the corresponding scanning lines and bit lines, provided for each dot, which is the smallest unit of display control; a memory cell section, the number of memory cells being sufficient to store an image signal for at least one row of dots of the display drive section, allocated in accordance with the row length of the display drive section, and each memory cell being connected to a bit line; a column decoder section, the display drive section being allocated in accordance with the row length of the display drive section, for selecting the memory cells in which to store an input image signal; and a column selection switch section, the display drive section being allocated in accordance with the row length of the display drive section, for switching based on the selection of the column decoder section and the image signal, and for storing the image signal in the memory cell selected by the column decoder section, [Claim 8] A display device comprising: a display drive section formed in a matrix, the display drive section having a plurality of scanning lines and a plurality of bit lines, and an organic EL element for each dot, which is the smallest unit of display control and whose light emission is controlled by driving the corresponding scanning lines and bit lines; a memory cell section, the number of memory cells being sufficient to store an image signal for at least one row of dots of the display drive section, the memory cells being allocated so that the row length of the memory cells is equal to or less than the row length of the display drive section, and the memory cells being connected to the bit lines; a column decoder section, the row length of which is equal to or less than the row length of the display drive section, for selecting the memory cells in which to store an input image signal; and a column selection switch section, the row length of which is equal to or less than the row length of the display drive section, which switches based on the selection of the column decoder section and the image signal, and causes the image signal to be stored in the memory cell selected by the column decoder section, all integrated and formed on a semiconductor or insulator substrate. [Claim 9] A display device described in any of claims 1 to 8, characterized in that the number of memory cells allocated in accordance with the row length of the display drive unit and capable of storing image signals sufficient to perform display control for one row of dots of the display drive unit is configured redundantly. [Claim 10] The display device described in any one of claims 1 to 8, characterized in that the memory cell section is composed of a memory array corresponding to the dot arrangement of the display drive section, with memory cells connected to each word line, the number of which is equal to the number of scanning lines, and the number of memory cells being sufficient to store image signals for display control of one row of dots, and further a word line driver section for selecting and driving the word lines is further integrated and formed integrally on the substrate. 11. The display device according to claim 10, wherein the scanning line driver section selects the scanning lines and the word line driver section selects the word lines based on address signals indicating display positions and storage positions. 12. The display device according to claim 11, wherein the same address signal is input to said scanning line driver section and said word line driver section. 13. The display device according to claim 11, wherein independent address signals are input to said scanning line driver section and said word line driver section. [Claim 14] A display device as described in claim 11, characterized in that the scanning line driver section performs a selective drive operation of the scanning lines based on the address signal only while a scanning line driver control signal is input, and the word line driver section performs a selective drive operation of the word lines based on the address signal only while a word line driver control signal is input. 15. The display device according to claim 11, wherein said column decoder section selects a memory cell for storing an input image signal based on said address signal. 16. Three light sources for displaying red, blue, and green light.
16. The display device according to claim 15, wherein a dot is one pixel, the image signal is input in units of one pixel, and the column decoder section selects memory cells for one pixel. 17. Three light sources for displaying red, blue, and green light.
16. The display device according to claim 15, wherein a dot is one pixel, the image signal is input in units of a plurality of pixels, and the column decoder section selects memory cells for a plurality of pixels. [Claim 18] A display device described in any one of claims 1 to 8, characterized in that the input wiring for the image signal to be stored in the memory cell section and the column selection switch section are formed on the opposite side of the memory cell section from the display drive section. [Claim 19] A display device described in any one of claims 1 to 8, characterized in that the memory cell section is formed in a multi-stage configuration with memory cells allocated in accordance with the row length of the display drive section. [Claim 20] A display device as described in claim 10, characterized in that word lines are provided in an integer multiple of the number of scanning lines, and the memory cell section is composed of a memory array in which memory cells in a number sufficient to store image signals for controlling the display of one row of dots in the display drive section are divided and connected to the integer multiple of the number of word lines. [Claim 21] A display device described in any of claims 1 to 8, characterized in that the memory cell section is composed of a memory array in which memory cells are allocated in a number sufficient to store image signals for display control of multiple rows of dots in the display drive section in accordance with the row length of the display drive section. [Claim 22] A display device described in any of claims 1 to 8, characterized in that the memory cell section is composed of a memory array in which memory cells are allocated in such a way that the row length is less than the row length of the display drive section, and the number of memory cells is sufficient to store image signals sufficient to perform display control for multiple rows of dots of the display drive section. [Claim 23] A display device described in any one of claims 11 to 22, characterized in that a timing controller section that controls the timing of transmitting the address signal and a memory controller section that controls the transmission of the image signal are further integrated and formed integrally on the substrate. [Claim 24] A display device described in any of claims 1 to 8, wherein a D/A converter is provided between the display driving unit and the memory cell unit, so that the image signal, which is a digital signal stored in the memory cell unit, is converted into an analog signal before being supplied to the display driving unit. [Claim 25] A display device described in any one of claims 1 to 8, wherein the image signal consisting of a digital signal stored in the memory cell unit is supplied to the display drive unit by directly connecting the display drive unit and the memory cell unit. 26. A display device according to claim 25, wherein said display driver performs digital driving using area gradation, time division gradation, or a combination thereof.