JPWO2008078566A1 - Capacitor layer forming material for multilayer printed wiring board and method for manufacturing capacitor layer forming material - Google Patents

Abstract

An object of the present invention is to provide a capacitor layer forming material containing copper as a main component in a conductive layer for forming a lower electrode circuit, which exhibits good and stable dielectric characteristics. In order to achieve this object, a capacitor layer forming material comprising a dielectric layer between an upper electrode circuit forming conductive layer and a lower electrode circuit forming conductive layer, wherein the lower electrode circuit forming conductive layer is a copper layer In addition, a capacitor layer forming material or the like for forming a built-in capacitor layer of a multilayer printed wiring board, which includes a zinc-containing layer on a surface in contact with the dielectric layer, is employed. In addition, as a method of manufacturing the capacitor layer forming material, a zinc layer is provided on the conductive layer for forming the upper electrode circuit, heat-treated in an oxidizing atmosphere, and the zinc component is converted into zinc oxide to form the conductive layer for forming the lower electrode circuit. Then, a method of forming a dielectric layer on the zinc-containing layer and forming a conductive layer for forming an upper electrode circuit on the dielectric layer to obtain a capacitor layer forming material is employed.

Description

  The present invention relates to a capacitor layer forming material for a multilayer printed wiring board, a method for manufacturing the capacitor layer forming material, and a multilayer printed wiring board including a built-in capacitor layer obtained using the capacitor layer forming material.

  2. Description of the Related Art Conventionally, a multilayer printed wiring board having a built-in capacitor layer uses one or more insulating layers positioned as inner layers as dielectric layers, and an upper electrode and a lower electrode as capacitor circuits on both sides of the dielectric layer. Has taken the structure of confronting each other. Therefore, the capacitor circuit is referred to as a built-in capacitor circuit, and a layer in which the built-in capacitor circuit exists has been referred to as a built-in capacitor layer.

  For the production of a multilayer printed wiring board provided with this built-in capacitor layer, a capacitor layer forming material provided with conductors on both sides of a dielectric as shown in Patent Document 1 has been used. The capacitor circuit of the multilayer printed wiring board has been required to have a large electric capacity, a low dielectric loss, etc. in order to save power and improve the operational stability of the mounted electronic component. Therefore, an effort has been made to secure a thinner and wider electrode area by selecting a material having a good dielectric constant for the dielectric layer of the capacitor circuit. Among them, in order to obtain a thin dielectric layer, a sol-gel method as disclosed in Patent Document 2 has been adopted.

  However, in the sol-gel method, an inorganic oxide layer that uniformly applies a sol-gel solution containing an inorganic oxide precursor to a base material, and finally heats at a temperature of usually 600 ° C. or higher to function as a dielectric layer. Is what you get. Therefore, in the case of a capacitor layer forming material having a dielectric layer between the upper electrode circuit forming conductive layer and the lower electrode circuit forming conductive layer, as disclosed in Patent Document 2, the lower electrode circuit forming conductive layer is used. A dielectric layer is directly formed by a sol-gel method on a metal layer (including a metal foil). At this time, since it is finally fired at a temperature of 600 ° C. or higher, it is necessary to select and use a material having excellent heat resistance for the metal layer constituting the conductive layer for forming the lower electrode circuit. For example, the use of nickel foil as disclosed in Patent Document 2. When a general copper foil is used as the conductive layer for forming the lower electrode circuit, the copper component is oxidized during the heating process in the sol-gel method, and the adhesion between the conductive layer for forming the lower electrode circuit and the dielectric layer can be maintained. There was a tendency that there was no phenomenon or the copper component diffused to the dielectric layer side by heating, and the ability as a capacitor was likely to vary.

  Patent Document 3 discloses a multilayer wiring board material with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of a metal foil. And in this patent document 3, providing the oxidation protection film | membrane of copper on the surface of the conductor layer which contacts a dielectric thin film is disclosed. The metal used to form this oxidation protective film is one or more selected from the group consisting of platinum, gold, silver, palladium, ruthenium and iridium, or a metal that forms a stable self-oxidation film on the surface of copper. It is disclosed to use one or more selected from the group consisting of certain chromium, molybdenum, titanium, and nickel.

JP 2002-539634 Gazette JP 2006-135036 A WO 2004/084597

  However, when a nickel foil is used for the lower electrode circuit forming conductive layer as in the invention disclosed in Patent Document 2, the nickel foil is expensive and has poor etching characteristics. And it was difficult to manufacture with high precision.

  As another method disclosed in Patent Document 3, a protective function for the purpose of preventing oxidation of copper serving as an electrode can be achieved, but most of the metal used as a protective film is a noble metal component and is expensive, and a nickel foil is used. In some cases, the cost may be increased. Further, a metal that forms a stable self-oxidation film has a problem that a physical film forming method such as sputtering vapor deposition needs to be used, resulting in an increase in manufacturing cost.

  On the other hand, the capacitor circuit is a part of the built-in circuit of the printed wiring board, and the main circuit of the printed wiring board is generally formed of copper, ensuring the consistency of electrical resistance as a circuit, It has been desired to improve characteristics as a high-frequency substrate. Accordingly, it has been desired to use a capacitor circuit including an electrode mainly using a copper component as to the capacitor circuit.

  As a result, it is a capacitor layer forming material that contains copper as a main component in the conductive layer for forming the lower electrode circuit and forms a thin dielectric layer by utilizing the usefulness of the sol-gel method. There has been a demand for a material that exhibits dielectric properties.

  Thus, as a result of earnest research, the present inventors have come up with the idea that the above-described problems can be solved by adopting the following technical idea. Hereinafter, the present invention will be described.

Capacitor layer forming material according to the present invention: The capacitor layer forming material according to the present invention is a capacitor layer forming material comprising a dielectric layer between the upper electrode circuit forming conductive layer and the lower electrode circuit forming conductive layer, The conductive layer for forming the lower electrode circuit is a copper layer, and includes a zinc-containing layer containing 50 mg / m ^{2 to} 1000 mg / m ² of zinc per unit area on a surface facing the dielectric layer. A capacitor layer forming material for forming a built-in capacitor layer of a multilayer printed wiring board.

The zinc-containing layer of the capacitor layer forming material according to the present invention preferably contains 50 mg / m ² or more of zinc in a region from the outermost surface to a depth of 0.5 μm.

  Furthermore, in the zinc-containing layer of the capacitor layer forming material according to the present invention, it is preferable that 80 atomic% or more of zinc on the surface facing the dielectric layer is zinc oxide.

Method for Producing Capacitor Layer Forming Material According to Present Invention: A method for producing a capacitor layer forming material for forming a built-in capacitor layer of a multilayer printed wiring board according to the present invention includes the following steps A to D: .

Step A: A zinc layer is formed on the surface of the copper foil to obtain a copper foil with a zinc layer provided with the zinc layer.
Process B: The said copper foil with a zinc layer is heat-processed in an oxidizing atmosphere as needed, and the conductive layer for lower electrode circuit formation provided with the zinc content layer by making at least one part of a zinc component into zinc oxide is obtained.
Step C: A dielectric layer is formed on the zinc-containing layer of the lower electrode circuit forming conductive layer to form a lower electrode circuit forming conductive layer with a dielectric layer.
Step D: An upper electrode circuit forming conductive layer is formed on a dielectric layer of the dielectric layer-attached lower electrode circuit forming conductive layer to obtain a capacitor layer forming material.

  The formation of the zinc layer in the step A of the method for producing a capacitor layer forming material according to the present invention preferably uses an electrochemical plating method or a physical vapor deposition method.

  The heat treatment in Step B of the method for producing a capacitor layer forming material according to the present invention preferably employs an oxygen-containing atmosphere and is heated so that the atmosphere temperature is 150 ° C. to 400 ° C.

  In the heat treatment in the step B of the method for producing a capacitor layer forming material according to the present invention, when the oxygen-containing atmosphere is used, the oxygen concentration in the atmosphere is preferably 20 vol% to 27 vol%.

Capacitor layer forming material with electrode circuit according to the present invention: A capacitor layer forming material with an electrode circuit for constituting a built-in capacitor layer of a multilayer printed wiring board according to the present invention has a conductive layer for forming a lower electrode circuit on one surface side of a dielectric layer. A capacitor layer forming material with an electrode circuit having an upper electrode circuit on the other side, wherein the conductive layer for forming the lower electrode circuit is a copper layer and has a unit area on a surface facing the dielectric layer characterized in that it comprises a zinc-containing layer containing zinc ^{50mg / m 2 ~1000mg / m 2} .

Multilayer printed wiring board according to the present invention: The multilayer printed wiring board according to the present invention is characterized in that a built-in capacitor layer is formed using the capacitor layer forming material with electrode circuit described above.

  In this invention, the copper layer provided with a zinc containing layer is employ | adopted for the said conductive layer for lower electrode circuit formation, and it has arrange | positioned so that this zinc containing layer and a dielectric layer may contact | connect. With such an arrangement, even when heat treatment is performed as a subsequent step, copper oxidation due to heating is suppressed, and good adhesion between the lower electrode circuit forming conductive layer and the dielectric layer can be maintained. Further, the diffusion of the copper component into the dielectric layer due to the heat during the heating and firing is suppressed, and stable dielectric characteristics are exhibited as a capacitor circuit. Furthermore, zinc contained in the zinc-containing layer is less expensive than other metal components, and there is an advantage that a high-quality capacitor layer forming material can be provided at low cost.

  In addition, by using the capacitor layer forming material according to the present invention, it is possible to form a capacitor circuit having excellent dielectric characteristics. Since this capacitor circuit mainly uses a copper component for the capacitor electrode, it has a low electrical resistance equivalent to that of the copper foil constituting the signal circuit, power circuit, etc. of the multilayer printed wiring board, and has a charge / discharge response performance. Excellent for high-frequency substrate applications.

  Furthermore, since the manufacturing method of the capacitor layer forming material according to the present invention uses an electrochemical plating method for forming the zinc-containing layer, the manufacturing cost is low, mass production is possible, and the capacitor is high quality and inexpensive. The production of the layer forming material is made possible.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In each drawing, the layer configuration and the like are shown as a schematic cross-sectional view, but are shown for easy understanding of the description, and clearly indicate that the thickness of each layer is different from the actual one. Keep it.

Form of the capacitor layer forming material according to the present invention: The capacitor layer forming material according to the present invention is used for forming a built-in capacitor layer of a multilayer printed wiring board, and is an upper electrode circuit forming conductive layer and a lower electrode circuit forming conductive. The capacitor layer forming material includes a dielectric layer between the layers. The conductive layer for forming the lower electrode circuit is a copper layer, and a zinc-containing layer is provided on a surface in contact with the dielectric layer. FIG. 1 shows a schematic cross-sectional view of the capacitor layer forming material 1 according to the present invention. The capacitor layer forming material 1 includes a lower electrode circuit forming conductive layer 3 on one surface side of a dielectric layer 2 and an upper electrode circuit forming conductive layer 4 on the other surface side. A zinc-containing layer 5 is provided on the surface of the lower electrode circuit forming conductive layer 3 in contact with the dielectric layer 2.

  The presence of this zinc-containing layer is obtained by forming a dielectric layer on the surface thereof by a sol-gel method, but the presence of the zinc-containing layer on the copper layer allows for subsequent processes, Capacitor oxidation due to heating is suppressed, good adhesion between the conductive layer for forming the lower electrode circuit and the dielectric layer can be secured, and at the same time, diffusion of the copper component into the dielectric layer due to heat during the heating and firing is suppressed, and the capacitor The circuit exhibits stable dielectric characteristics. That is, the zinc-containing layer referred to here preferably has a zinc oxide layer on the outermost surface. And it is preferable to equip the lower part of a zinc content layer with a brass layer. The brass layer is considered to function as a diffusion barrier to the dielectric layer side of the copper component constituting the conductive layer for forming the lower electrode circuit.

Then, the zinc-containing layer of the capacitor layer forming material according to the present invention, per unit ^area, it is preferable to contain zinc ^{50mg / m 2 ~1000mg / m 2} . This weight thickness is used as an alternative index of the thickness of the zinc-containing layer, and indicates a range necessary for maintaining good adhesion between the dielectric layer and the conductive layer for forming the lower electrode circuit. . When the amount of zinc per unit area is less than 50 mg / m ² , the copper surface cannot be uniformly coated, and the adhesiveness between the dielectric layer and the lower electrode circuit forming conductive layer tends to vary. On the other hand, if the amount of zinc per unit area exceeds 1000 mg / m ² , the tendency of decreasing the electric capacity when forming a capacitor circuit becomes prominent and the value of dielectric loss tends to increase. If the amount of zinc exceeds the upper limit, a thick brass layer will be formed, and the electrical resistance will increase compared to copper, so the speed of the capacitor circuit operation will be slow and it will not be possible to follow high-speed signals. Therefore, it is not preferable.

Furthermore, the zinc-containing layer of the capacitor layer forming material according to the present invention preferably has 50 mg / m ² or more of zinc in a region from the outermost surface to a depth of 0.5 μm. That is, since the minimum necessary amount of zinc per unit area of the zinc-containing layer is 50 mg / m ² , the value of this zinc amount is used as a reference. When a certain amount or more of zinc is present near the surface, the effect of providing the zinc-containing layer can be sufficiently exhibited. In the case of the capacitor layer forming material according to the present invention, it is important that zinc is present on the outermost surface of the lower electrode circuit forming conductive layer in contact with the dielectric layer. Here, when zinc in the region from the outermost surface of the zinc amount to a depth of 0.5 μm is less than 50 mg / m ² , the adhesion between the dielectric layer and the lower electrode circuit forming conductive layer is likely to vary. . The depth said here is the depth calculated by the following method. That is, information at an arbitrary depth is obtained by using the depth profile of the hole formed in the depth direction by analysis by the GDS method. In general data obtained by measurement by the GDS method, the horizontal axis represents time, and the vertical axis represents the emission intensity of zinc in an arbitrary unit. The relationship between the time and the emission intensity is converted into the depth from the surface of the sample and the total amount of zinc detected so far. That is, the depth at which a sample is dug by measurement and the measurement time are usually in a linear relationship. Therefore, when the depth of the measurement portion of the sample measured until the zinc signal disappears is measured with a roughness meter, the processing time on the horizontal axis in the GDS data can be converted as the depth from the surface. Furthermore, since the integrated value of the emission intensity in the GDS data corresponds to the total amount of zinc, if the total amount of zinc is analyzed in advance by emission spectroscopy or the like, along with the depth calculated from the conversion result of the above time axis, The total amount of zinc detected up to an arbitrary depth can be calculated.

  In the capacitor layer forming material according to the present invention, it is preferable that 80 atomic% or more of zinc in the surface in contact with the dielectric layer of the zinc-containing layer is zinc oxide from the viewpoint of increasing the capacitance density as a capacitor. Further, in order to enhance the effect of preventing oxidation of the copper layer by providing the zinc-containing layer, the value of [zinc (atomic%)] / [copper (atomic%)] in the surface portion of the zinc-containing layer is 5 or more. It is preferable to do.

Manufacturing method of capacitor layer forming material according to the present invention: A method for manufacturing a capacitor layer forming material for forming a built-in capacitor layer of a multilayer printed wiring board according to the present invention includes the following steps A to D: . Hereinafter, it demonstrates for every process.

In Step A, a zinc layer is formed on the surface of the copper foil, and a copper foil with a zinc layer provided with the zinc layer is obtained. Here, in order to form the zinc layer on the surface of the copper foil, either an electrochemical method or a physical vapor deposition method may be used. However, it is preferable to provide the zinc layer by employing an electrochemical plating method. This is because the manufacturing cost is low compared with the physical vapor deposition method. Although an electroplating method or an electroless plating method can be employed, in the case of electroless plating, a catalytic metal is required, and therefore it is preferable to use an electroplating method. When the electrolytic plating method is adopted, for example, a sulfuric acid plating bath is used as an electrolytic bath, zinc sulfate is contained at a concentration of 150 g / l to 450 g / l, and a sulfate such as sodium sulfate or magnesium sulfate is used as a buffer. And, if necessary, a brightening agent or the like is added, and electrolysis is performed at a liquid temperature of 40 ° C. to 65 ° C. and a current density of 20 A / dm ^{2 to} 60 A / dm ² for a predetermined thickness.

  The zinc layer can be formed by a physical vapor deposition method such as a sputtering vapor deposition method or an electron beam vapor deposition method. This physical vapor deposition method has a drawback that the production cost is higher than that of the above-described electrochemical plating method, but if the physical vapor deposition method is used, it is also possible to directly form a zinc oxide layer.

  In Step B, the copper foil with zinc layer obtained in Step A is heat-treated in an oxidizing atmosphere to obtain a conductive layer for forming a lower electrode circuit having a zinc component as zinc oxide and a zinc-containing layer. In this step, the main purpose is to convert at least the outermost surface of the metal zinc layer formed on the surface of the copper foil layer into zinc oxide. At this time, a part of the metallic zinc is considered to diffuse into the underlying copper layer and become brass. That is, the zinc-containing layer obtained in this step B includes a zinc oxide layer on the surface layer and a brass layer on the inside. In this step, if the heating is carried out for a too long time, mutual diffusion proceeds and a copper oxide layer appears on the surface side of the zinc-containing layer. Therefore, it is necessary to employ appropriate heating conditions.

In the present invention, as described above, it is preferable that 50 mg / m ² or more of zinc is present in a thickness range from the outermost surface on the zinc layer side of the copper foil with a zinc layer to 0.5 μm. It is known that interdiffusion due to metal heating is affected by heating temperature and heating time, and the diffusion rate is an exponential function of absolute temperature. Therefore, under conditions where the temperature is below the lower limit of 150 ° C., the heating time is long and the productivity is poor. And when heating temperature exceeds 400 degreeC, since the mutual diffusion rate of zinc and copper will become quick rapidly, even if heating time becomes a little long, since a copper component appears on the surface, it is unpreferable. And although heating time should just be set according to the set heating temperature, it is preferable to set it as 5 to 30 minutes in the said heating temperature range.

  The heat treatment here uses an oxygen-containing atmosphere for the purpose of forming zinc oxide. The oxygen-containing atmosphere here is described as a concept including an air atmosphere. The oxygen partial pressure in the atmosphere is preferably 20 vol% to 27 vol%. By satisfying the conditions mentioned here, an appropriate amount of zinc oxide can be formed on the surface of the metal zinc layer, and good adhesion between the lower electrode circuit forming conductive layer and the dielectric layer can be obtained.

  Here, the change in the depth direction profile of zinc and copper in the depth direction of the copper foil with a zinc layer before and after heating will be described. The depth of the copper foil with a zinc layer (hereinafter simply referred to as “sample 7”) of Sample 7 and the copper foil with a zinc layer of Sample 8 (hereinafter simply referred to as “Sample 8”) in Examples described later. The description will be made by comparing the depth profiles of zinc and copper in the direction. Here, the profile in the depth direction of zinc and copper is the abundance ratio (atomic%) of zinc and copper at a predetermined depth by sputtering etching using argon ions by XPS (X-ray photoelectron spectroscopy) method. ) Was performed by semi-quantitative analysis. The results are shown in Table 1.

  As can be understood from Table 1, when the sputtering time is 6000 seconds (depth of about 150 μm in terms of silicon oxide), the detection of zinc in the sample 7 without heating is almost eliminated. On the other hand, in the case of the sample 8 after heating, a slight amount of zinc is detected at the same depth. When the measured values of sputtering time 0 seconds (outermost surface layer: depth of 0 μm in terms of silicon oxide) and sputtering time 20 seconds (depth of about 0.5 μm in terms of silicon oxide) are compared, It can be said that the sample 8 after heating has a more homogeneous zinc distribution than the sample 7. Furthermore, from the observation results of the surface of the zinc layer before and after heating by X-ray photoelectron spectroscopy analysis, it was found that the outermost zinc was converted to zinc oxide after heating compared to before heating.

In step C, a dielectric layer is formed on the zinc-containing layer of the lower electrode circuit forming conductive layer to form a lower electrode circuit forming conductive layer with a dielectric layer. There is no particular limitation on the method of forming the dielectric layer. For example, a physical vapor deposition method such as an MO-CVD method, a sol-gel method, or a sputtering vapor deposition method may be used, or a method in which a dielectric filler-containing resin solution is applied and formed. However, it is preferable to use a sol-gel method from the viewpoint of forming a thin and uniform dielectric film with a large area. The sol-gel method here is not particularly limited with respect to the type of dielectric layer to be formed and the formation method. However, as an example, the dielectric layer formed by the sol-gel method includes Pb (Zr, Ti) O ₃ , (Pb, La) (Zr, Ti) O ₃ , Ba _x Sr _{1 − x TiO 3 (0 ≦ x ≦} 1), (Pb, Ca) (Zr, Ti) which is preferably a composite oxide having a perovskite structure of the _{O 3} and the like. Among these, the composite oxide having the Ba _x Sr _1-x TiO ₃ (0 ≦ x ≦ 1) composition is preferable in order to obtain a high capacity density without containing lead as a constituent component of the dielectric layer.

  A method of forming these dielectric layers will be described. First, a sol-gel solution containing these precursor components is prepared. Then, this sol-gel solution is applied to a metal foil to be a conductive layer for forming the lower electrode circuit using a spin coater or the like, and the process of drying and pyrolysis is defined as one unit process, and this one unit process is repeated. As a thickness, a dielectric layer having a desired thickness is formed by heating for final crystallization. In this process, it is also preferable to add a pre-baking step between one unit step and one unit step.

  In step D, a capacitor layer forming material is obtained by forming a conductive layer for forming an upper electrode circuit on a dielectric layer of the conductive layer for forming a lower electrode circuit with a dielectric layer. In order to form the conductive layer for forming the upper electrode circuit on the dielectric layer, any technique such as physical vapor deposition, electrochemical technique, and lamination of metal foil can be used, and there is no particular limitation. However, since the upper electrode circuit forming conductive layer may be thin, it is preferable to use physical vapor deposition.

  It should be noted that the method for producing a capacitor layer forming material employing the above steps A to D is a method for producing a capacitor layer forming material for constituting a built-in capacitor layer of a multilayer printed wiring board according to the present invention. As the most preferable production form. That is, the capacitor layer forming material according to the present invention can be obtained by omitting the heat treatment of the zinc layer in the step B. In particular, since the electrolytically deposited zinc layer is in an activated state, even if it is left in the air atmosphere, it binds to oxygen in the air and its surface layer tends to be converted to zinc oxide. It is. Therefore, in the following examples, the case where the heating of the zinc layer formed on the conductive layer for forming the lower electrode circuit is omitted is described. However, in order to form a stable amount of zinc oxide, it is preferable to perform the heat treatment of step B.

Form of capacitor layer forming material with electrode circuit according to the present invention: The capacitor layer forming material with electrode circuit for the built-in capacitor layer configuration of the multilayer printed wiring board according to the present invention is a conductive for forming a lower electrode circuit on one surface side of the dielectric layer. A capacitor layer forming material with an electrode circuit comprising an upper electrode circuit on the other surface side, wherein the lower electrode circuit forming conductive layer is a copper layer and contains zinc on the surface in contact with the dielectric layer It is characterized by comprising a layer and includes the same technical idea as the capacitor layer forming material.

  In this case, as shown in FIG. 1, when the upper electrode circuit forming conductive layer 4 covers the entire surface of the dielectric layer 2, an unnecessary portion of the upper electrode circuit forming conductive layer 4 is formed using an etching method or the like. Then, as shown in FIG. 2A, an upper electrode circuit 6 is formed to form a capacitor layer-forming material 7 with an electrode circuit. In the case of processing by an etching method, an etching resist layer is provided on the conductive layer using a dry film, a liquid resist, or the like that can be used as an etching resist. Then, a resist pattern is exposed and developed on the etching resist layer, and unnecessary portions are peeled and removed to form an etching resist pattern. Thereafter, an unnecessary portion of the conductive layer for forming the upper electrode circuit is dissolved and removed using an etching solution such as cupric chloride to form an upper electrode circuit, whereby the capacitor layer forming material 7 with electrode circuit is obtained. As shown in FIG. 2B, it is also preferable to remove the dielectric layer 2 exposed between the upper electrode circuit 6 and the upper electrode circuit 6 by using a blast method or the like.

  Further, the upper electrode circuit 6 can be formed directly on the dielectric layer 2. In this case, a deposition mask for forming an upper electrode circuit is placed, and the upper electrode circuit 6 is directly formed by a sputtering deposition method or the like. Thereafter, the capacitor layer forming material with electrode circuit 7 can be directly obtained by removing the evaporation mask.

Multilayer printed wiring board according to the present invention: The multilayer printed wiring board according to the present invention is characterized in that a built-in capacitor layer is formed using the capacitor layer forming material with electrode circuit described above. There is no particular limitation on the production of the multilayer printed wiring board, and a known production method for a multilayer printed wiring board can be applied. The manufacturing flow will be briefly described. Using the capacitor layer forming material 7 with an electrode circuit shown in FIG. 2, a prepreg 8 and a conductive foil 9 are hot press-molded on both sides as shown in FIG. Thus, a double-sided conductor-clad multilayer laminate 10 as shown in FIG. Then, a multilayer printed wiring board having a built-in capacitor layer is obtained by forming an interlayer connection between the outer layer conductor foil 9 and the upper electrode circuit 6 and performing an etching process using a known method.

  The multilayer printed wiring board including the built-in capacitor layer according to the present invention described above has a configuration including a zinc-containing layer containing zinc oxide at an interface in contact with the dielectric layer while using a copper layer as a lower electrode. With this configuration, even when a dielectric layer is formed by applying a high temperature as in the sol-gel method, the adhesion between the dielectric layer and the lower electrode forming conductor layer is excellent. In addition, such a dielectric layer exhibits excellent dielectric properties. As a result, a multilayer printed wiring board having a built-in capacitor layer obtained by using the capacitor layer forming material can achieve a long life, and the quality variation is reduced, and the high-performance application board exhibits good performance. To do.

In this example, in order to form various zinc-containing layers using copper foil as the lower electrode circuit forming conductive layer, the thickness of the zinc layer on the surface of the copper foil was changed, and eight types of capacitor layer forming materials were used. Manufactured and subjected to various evaluations. That is, the surface of the electrolytic copper foil of 35μm thickness, and forming the zinc layer with a thickness of 6 levels in the range of ^{50mg / m 2 ~1000mg / m 2} ( samples 1 to 8) in the embodiment, the zinc-containing Layered. Then, a Ba _0.7 Sr _0.3 TiO ₃ film was formed on the zinc-containing layer by a sol-gel method, and the capacitor capacity and dielectric loss were evaluated to see the stability of the dielectric characteristics. Table 2 shows the main preparation conditions of the conductive layer for forming the lower electrode circuit and the dielectric layer created here.

Formation of copper foil with zinc layer: An electroplating method was used to form a zinc layer on the copper foil. A zinc sulfate bath is used as the plating bath, and the SUS plate has a zinc pyrophosphate trihydrate concentration of 80 g / L, a potassium pyrophosphate concentration of 300 g / L, a pH of 10.7, a liquid temperature of 55 ° C., and a current density of 15 A / dm ^2. Was used as a cathode, and electrolysis was performed for the time required to obtain the zinc amounts shown in Table 2.

Preparation of conductive layer for forming lower electrode circuit: Among the copper foils with the zinc layer obtained as described above, Sample 6 and Sample 8 whose heating is “present” in Table 2 are heated at 300 ° C. for 15 minutes. The treatment was carried out to form each conductive layer for forming the lower electrode circuit. On the other hand, Sample 1, Sample 2, Sample 3, Sample 4, Sample 5, and Sample 7 are unheated samples. Hereinafter, the capacitor layer-forming material with electrode circuit is manufactured using Sample 1 to Sample 8, and is classified by the same designation as Sample 1 to Sample 8 at each stage.

Formation of dielectric layer: A dielectric layer was formed on the conductive layer for forming the lower electrode circuit by using a sol-gel method. The conductive layer for forming the lower electrode circuit before forming the dielectric layer by the sol-gel method was irradiated with ultraviolet rays for 1 minute for the purpose of cleaning the surface.

In the sol-gel method used here, an oxide dielectric layer having a composition of Ba _0.7 Sr _0.3 TiO ₃ can be obtained by using a trade name BST thin film forming agent 7 wt% BST manufactured by Mitsubishi Materials Corporation. Prepared. Then, the sol-gel solution is applied to the surface of the conductive layer for forming the lower electrode circuit, dried in an oxygen-containing atmosphere at 150 ° C. for 2 minutes, and then in an oxygen-containing atmosphere at 330 ° C. for 15 minutes. A series of processes for performing thermal decomposition was defined as one unit process, and this one unit process was repeated to form a dielectric. In Samples 1 to 5, this 1-unit process was repeated 6 times, and the film thickness was adjusted, and finally baked in a nitrogen-substituted atmosphere at 600 ° C. for 30 minutes to perform final crystallization to form a dielectric layer. In Sample 6 to Sample 8, this 1 unit process is repeated 9 times to adjust the film thickness, and after completion of the 1st, 3rd, and 6th 1 unit processes, 650 ° C. in a nitrogen-substituted atmosphere. A preliminary firing for 15 minutes was performed, and finally, a baking treatment was performed in a nitrogen substitution atmosphere at 800 ° C. for 30 minutes to perform final crystallization to form a dielectric layer.

Preparation of Capacitor Layer Forming Material with Electrode Circuit: An upper electrode circuit was directly formed on the dielectric layer formed as described above by sputtering deposition. Specifically, an evaporation mask for forming an upper electrode circuit is placed on the dielectric layer, a copper target material is used as a target, and the thickness is 0.5 μm and the size is 0.25 mm × 0.25 mm. An upper electrode circuit was formed to obtain a capacitor layer forming material 7 with an electrode circuit provided with the upper electrode circuit.

Evaluation results: Hereinafter, the evaluation method is described for each evaluation item, and the evaluation results are summarized in Table 3 so that the comparison with the comparative example is possible.

  The amount of zinc in the zinc-containing layer of the lower electrode circuit-forming conductive layer was determined by dissolving the zinc layer-forming surface of the lower electrode circuit-forming conductive layer with an acid solution, and measuring the solution by emission spectroscopy. The result is shown in Table 3 so that it can be compared with the comparative example.

  The depth profile of zinc, copper, etc. of the zinc-containing layer of the conductive layer for forming the lower electrode circuit was determined using a glow discharge emission analyzer (GD-OES: JY-5000RF, manufactured by HORIBA JOBIN YVON) with an analysis area of 4 mmφ. The amount of zinc from the outermost layer to a depth of 0.5 μm was measured. The result is shown in Table 3 so that it can be compared with the comparative example.

The initial capacity density was as high as 508 nF / cm ^{2 to} 1585 nF / cm ² . In detail, it shows in Table 3 so that a comparison with a comparative example is possible.

  When the dielectric loss of the capacitor circuit was measured, it was in the range of 0.042 (4.2%) to 0.084 (8.4%). In detail, it shows in Table 3 so that a comparison with a comparative example is possible.

Comparative example

In this comparative example, the lower the amount of said zinc is not heat treated and 50mg / m ² ~1000mg / m to form a zinc layer of two levels outside the range of ^2, the lower electrode circuit forming conductive layers in which the heat treatment Separately from the electrode circuit forming conductive layer, three types of comparative samples (Comparative Samples 1 to 3) were prepared. Hereinafter, the capacitor layer-forming material with an electrode circuit is manufactured using the comparative sample 1 to the comparative sample 3, and is classified by the same designation as the comparative sample 1 to the comparative sample 3 at each stage. The amount of zinc at this time is shown in Table 2 so that it can be compared with the examples.

  Since the manufacturing method of the comparative sample is basically the same as that of the example, only the different steps will be described. In the formation of the dielectric layer, in Comparative Sample 1 and Comparative Sample 2, the same unit process as in the example was repeated 6 times to adjust the film thickness, and finally baked in a nitrogen substitution atmosphere at 650 ° C. for 15 minutes. Final crystallization was performed to form a dielectric layer. And in the comparative sample 3, this 1 unit process is repeated 9 times, and film thickness adjustment is performed, and after completion | finish of the 1st unit process of the 1st time, the 3rd time, and the 6th time in the middle, it is 650 degreeC * 15 by nitrogen substitution atmosphere. Pre-baking was performed for a minute, and finally a baking treatment was performed in a nitrogen substitution atmosphere at 800 ° C. for 30 minutes to perform final crystallization to form a dielectric layer.

  The capacitor layer-forming material with electrode circuit was obtained in the same manner as in the example, and the same evaluation as in the example was performed. The results are shown in Table 3 so that they can be compared with the examples.

[Contrast between Example and Comparative Example]
First, the dielectric loss that is greatly different between the example and the comparative example is compared. Here, the dielectric loss of the capacitor circuits of Sample 1 to Sample 8 according to the example shows a value less than 0.1. On the other hand, the dielectric loss of the capacitor circuits of Comparative Sample 1 to Comparative Sample 3 according to the comparative example is 1 or more. Therefore, it can be seen that the example shows significantly better dielectric loss than the comparative example. More specifically, the maximum dielectric loss value among the samples according to the example is 0.084. Based on this value, the dielectric loss values obtained for Comparative Sample 1 and Comparative Sample 2 with a small amount of zinc show a large dielectric loss of 1.2, which is about 14 times. Further, the value of dielectric loss of comparative sample 3 having an excessively large amount of zinc is 2.5, which is about 30 times, indicating a further deteriorated dielectric loss. Then, comparison sample 3 is compared with sample 6 and sample 8 of the example. The conditions for preparing the dielectric layers of these samples are the same. When these capacity densities are compared, Sample 6 shows a value of 1585 nF / cm ² and Sample 8 shows a value of 1417 nF / cm ² , while Comparative Sample 3 shows a value of 968 nF / cm ² . Therefore, when the amount of zinc on the surface of the conductive layer for forming the lower electrode exceeds the range of the appropriate amount of zinc specified in the present invention, it can be confirmed that the capacity density tends to decrease.

Next, the influence of the conductive layer for forming the lower electrode on the dielectric characteristics due to heating of the zinc layer will be described. Sample 7 (without heating of the lower electrode forming conductive layer) and Sample 8 (with heating of the lower electrode forming conductive layer) will be described in comparison. First, in comparison with respect to the capacity density, sample 7 is 1293 nF / cm ² and sample 8 is 1417 nF / cm ² , and the capacity density is higher when the lower electrode forming conductive layer is heated. Next, when comparing the dielectric loss, the sample 7 is 0.073 and the sample 8 is 0.065, and the dielectric loss is lower when the lower electrode forming conductive layer is heated. Therefore, it can be said that it is more preferable to heat-treat in advance the lower electrode forming conductive layer provided with the zinc layer formed on the copper layer.

  The capacitor layer forming material according to the present invention is used for manufacturing a multilayer printed wiring board having a built-in capacitor layer, and is provided with a zinc-containing layer on the contact surface of the lower electrode forming layer with the dielectric layer, thereby forming a lower electrode. The adhesion between the layer and the dielectric layer is improved, and as a result, the dielectric properties such as capacitance density and dielectric loss are dramatically improved and stable performance is exhibited. In addition, the capacitor layer forming material according to the present invention does not require an expensive noble metal-based material such as platinum, gold, silver, or palladium, and thus is inexpensive and of high quality. Therefore, it is possible to provide a high-quality capacitor layer-forming material with an electrode circuit and a multilayer printed wiring board including a built-in capacitor circuit incorporating these. In addition, the production of the capacitor layer forming material according to the present invention does not require a special device, and the use of conventional equipment is preferable without causing an increase in production cost.

It is a schematic cross section of the capacitor layer forming material according to the present invention. It is a schematic cross section of the capacitor forming material with an electrode circuit according to the present invention. It is a schematic diagram for demonstrating the manufacture flow of a multilayer printed wiring board provided with the built-in capacitor layer which concerns on this invention. It is a schematic diagram for demonstrating the manufacture flow of a multilayer printed wiring board provided with the built-in capacitor layer which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Capacitor layer forming material 2 Dielectric layer 3 Lower electrode circuit forming conductive layer 4 Upper electrode circuit forming conductive layer 5 Zinc-containing layer 6 Upper electrode circuit 7 Capacitor layer forming material with electrode circuit 8 Prepreg 9 Conductive foil 10 Double-sided conductor-covered multilayer Laminated board

Claims (9)

A capacitor layer forming material comprising a dielectric layer between the upper electrode circuit forming conductive layer and the lower electrode circuit forming conductive layer,
The conductive layer for forming the lower electrode circuit is a copper layer, and includes a zinc-containing layer containing 50 mg / m ^{2 to} 1000 mg / m ² of zinc per unit area on a surface facing the dielectric layer. A capacitor layer forming material for forming a built-in capacitor layer of a multilayer printed wiring board. ^{2. The} capacitor layer formation for forming a built-in capacitor layer of a multilayer printed wiring board according to claim 1, wherein the zinc-containing layer has a zinc content of 50 mg / m ² or more in a region from the outermost surface to a depth of 0.5 μm. Wood. 3. The capacitor layer forming material for forming a built-in capacitor layer of a multilayer printed wiring board according to claim 1, wherein in the zinc-containing layer, 80 atomic% or more of zinc on the surface facing the dielectric layer is zinc oxide. A method for producing a capacitor layer forming material for forming a built-in capacitor layer of a multilayer printed wiring board, comprising the following steps A to D:
Step A: A zinc layer is formed on the surface of the copper foil to obtain a copper foil with a zinc layer provided with the zinc layer.
Process B: The said copper foil with a zinc layer is heat-processed in an oxidizing atmosphere as needed, and the conductive layer for lower electrode circuit formation provided with the zinc content layer by making at least one part of a zinc component into zinc oxide is obtained.
Step C: A dielectric layer is formed on the zinc-containing layer of the lower electrode circuit forming conductive layer to form a lower electrode circuit forming conductive layer with a dielectric layer.
Step D: An upper electrode circuit forming conductive layer is formed on a dielectric layer of the dielectric layer-attached lower electrode circuit forming conductive layer to obtain a capacitor layer forming material. The method for producing a capacitor layer forming material for forming a built-in capacitor layer of a multilayer printed wiring board according to claim 4, wherein the formation of the zinc layer in the step A uses an electrochemical plating method or a physical vapor deposition method. The built-in capacitor layer of the multilayer printed wiring board according to claim 4 or 5, wherein the heat treatment in the step B employs an oxygen-containing atmosphere and is heated so that the atmospheric temperature becomes 150 ° C to 400 ° C. Manufacturing method of capacitor layer forming material for forming. The method for producing a capacitor layer forming material for forming a built-in capacitor layer of a multilayer printed wiring board according to claim 6, wherein the oxygen-containing atmosphere has an oxygen concentration in the atmosphere of 20 vol% to 27 vol%. A capacitor layer forming material with an electrode circuit comprising a conductive layer for forming a lower electrode circuit on one side of a dielectric layer and an upper electrode circuit on the other side,
The conductive layer for forming the lower electrode circuit is a copper layer, and includes a zinc-containing layer containing 50 mg / m ^{2 to} 1000 mg / m ² of zinc per unit area on a surface facing the dielectric layer. A capacitor layer forming material with an electrode circuit for constituting a built-in capacitor layer of a multilayer printed wiring board. A multilayer printed wiring board, wherein a built-in capacitor layer is formed using the capacitor layer forming material with an electrode circuit according to claim 8.

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