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JPWO2004114508A1 - AC switch - Google Patents

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JPWO2004114508A1
JPWO2004114508A1 JP2005507191A JP2005507191A JPWO2004114508A1 JP WO2004114508 A1 JPWO2004114508 A1 JP WO2004114508A1 JP 2005507191 A JP2005507191 A JP 2005507191A JP 2005507191 A JP2005507191 A JP 2005507191A JP WO2004114508 A1 JPWO2004114508 A1 JP WO2004114508A1
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terminal
switch
electrode
diode
fet
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JP4123274B2 (en
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森田　浩一
浩一 森田
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Sanken Electric Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

入力される制御信号によりオン／オフし、第１端子１１及び第２端子１２間に入力された交流信号をオン／オフ制御させる交流スイッチであって、第１端子１１に第１主電極２１が接続され第２端子１２に第２主電極２２が接続されゲート信号を入力するゲートＧが接続されたノーマリオン型のＦＥＴＱ１と、第１端子１１及び第２端子１２の内の電位が低い端子とゲートＧとの間にゲート信号部１３のゲート信号を入力するダイオードＤ１，Ｄ２とを有する。This is an AC switch that is turned on / off by an input control signal and controls on / off of an AC signal input between the first terminal 11 and the second terminal 12, and the first main electrode 21 is connected to the first terminal 11. A normally-on FET Q1 connected to the second terminal 12 and connected to the second main electrode 22 and connected to a gate G for inputting a gate signal; and a terminal having a low potential among the first terminal 11 and the second terminal 12; Between the gate G, diodes D1 and D2 for inputting the gate signal of the gate signal section 13 are provided.

Description

本発明は、制御信号によりオン／オフして、入力された交流信号をオン／オフ制御させる交流スイッチに関する。  The present invention relates to an AC switch that is turned on / off by a control signal to control on / off of an input AC signal.

インバータやコンバータに使用される従来の交流スイッチとしては、例えば図１に示すようなものがある。図１に示す交流スイッチ１００には、第１端子１１と第２端子１２との両端に交流電源１１０からの交流信号が印加されるようになっている。
交流スイッチ１００は、第１端子１１と第２端子１２との両端に、逆直列接続されたノーマリオフ型のＭＯＳ ＦＥＴＱ４（以下、ＦＥＴＱ４と略称する。）とノーマリオフ型のＭＯＳ ＦＥＴＱ５（以下、ＦＥＴＱ５と略称する。）とが接続されている。ＦＥＴＱ４のドレインが第１端子１１に接続され、ＦＥＴＱ４のソースはＦＥＴＱ５のソースに接続され、ＦＥＴＱ５のドレインは第２端子１２に接続されている。ＦＥＴＱ４のゲートとＦＥＴＱ５のゲートとには、ゲート信号部１３からパルス信号からなるゲート信号が印加されるようになっている。
次に、このように構成された交流スイッチ１００の動作を説明する。まず、ゲート信号部１３からゲート信号が正電圧（例えば１０Ｖ）で、ＦＥＴＱ４及びＦＥＴＱ５のゲートに印加されると、ＦＥＴＱ４及びＦＥＴＱ５が共にオンする。
このため、ゲート信号が正電圧である期間においては、第１端子１１に交流電源１１０から正電圧が印加されている時には第１端子１１から第２端子１２に電流が流れ、第２端子１２に交流電源１１０から正電圧が印加されている時には第２端子１２から第１端子１１に電流が流れる。即ち、ＦＥＴＱ４とＦＥＴＱ５とが逆直列接続され且つ第１端子１１にＦＥＴＱ４のドレインが接続され、第２端子１２にＦＥＴＱ５のドレインが接続されているので、交流スイッチ１００に交流電流が流れる。
次に、ゲート信号部１３からゲート信号が零電圧で、ＦＥＴＱ４及びＦＥＴＱ５のゲートに印加されると、ＦＥＴＱ４及びＦＥＴＱ５が共にオフする。このため、交流スイッチ１００に電流が流れなくなる。
これにより、交流スイッチ１００は、ゲート信号の周波数に応じて交流スイッチ１００を流れる電流の周波数を変えることができる。また、この交流スイッチ１００によれば、ソースを共通にすることにより、１つのゲート信号でＦＥＴＱ４とＦＥＴＱ５とをオン／オフ制御できる。
一方、トライアックを交流スイッチとして用いることもある。しかし、トライアックに正電圧のゲート信号を印加することでオンすることができるが、トライアックに零電圧のゲート信号を印加してもオフすることはできない。即ち、トライアックを流れる電流が零近くにならなければトライアックをオフすることはできない。このため、トライアックを用いた場合、ゲート信号の周波数に応じてトライアックを流れる電流の周波数を変えることができず、交流電源１１０の周波数以上の周波数で、トライアックをオン／オフ制御することはできなかった。
従来の交流スイッチに関連する技術として特開平５−７５１１０号公報がある。As a conventional AC switch used for an inverter or a converter, for example, there is a switch as shown in FIG. In the AC switch 100 shown in FIG. 1, an AC signal from an AC power source 110 is applied to both ends of the first terminal 11 and the second terminal 12.
The AC switch 100 includes a normally-off type MOS FET Q4 (hereinafter abbreviated as FET Q4) and a normally-off type MOS FET Q5 (hereinafter abbreviated as FET Q5) connected in reverse series at both ends of the first terminal 11 and the second terminal 12. Connected). The drain of the FET Q4 is connected to the first terminal 11, the source of the FET Q4 is connected to the source of the FET Q5, and the drain of the FET Q5 is connected to the second terminal 12. A gate signal composed of a pulse signal is applied from the gate signal section 13 to the gate of the FET Q4 and the gate of the FET Q5.
Next, the operation of the AC switch 100 configured as described above will be described. First, when the gate signal is applied to the gates of the FETs Q4 and Q5 at a positive voltage (for example, 10 V) from the gate signal unit 13, both the FETs Q4 and FETQ5 are turned on.
For this reason, during a period in which the gate signal is a positive voltage, when a positive voltage is applied to the first terminal 11 from the AC power supply 110, a current flows from the first terminal 11 to the second terminal 12 and flows to the second terminal 12. When a positive voltage is applied from the AC power supply 110, a current flows from the second terminal 12 to the first terminal 11. That is, the FET Q4 and the FET Q5 are connected in reverse series, the drain of the FET Q4 is connected to the first terminal 11, and the drain of the FET Q5 is connected to the second terminal 12, so that an alternating current flows through the AC switch 100.
Next, when the gate signal is applied from the gate signal unit 13 to the gates of the FETs Q4 and Q5 with a zero voltage, both the FETs Q4 and Q5 are turned off. For this reason, no current flows through the AC switch 100.
Thereby, the AC switch 100 can change the frequency of the current flowing through the AC switch 100 according to the frequency of the gate signal. Further, according to the AC switch 100, by using a common source, the FET Q4 and the FET Q5 can be turned on / off by one gate signal.
On the other hand, a triac may be used as an AC switch. However, it can be turned on by applying a positive voltage gate signal to the triac, but it cannot be turned off even if a zero voltage gate signal is applied to the triac. That is, the triac cannot be turned off unless the current flowing through the triac becomes close to zero. For this reason, when a triac is used, the frequency of the current flowing through the triac cannot be changed according to the frequency of the gate signal, and the triac cannot be controlled on / off at a frequency higher than the frequency of the AC power supply 110. It was.
Japanese Patent Laid-Open No. 5-75110 discloses a technique related to a conventional AC switch.

しかしながら、図１に示す従来の交流スイッチにあっては、１素子ではなく、ＦＥＴＱ４とＦＥＴＱ５との２素子からなっている。また、ＦＥＴＱ４とＦＥＴＱ５とが直列に接続されているため、２素子のオン抵抗を加算した値が全体のオン抵抗になり、ロスが増大する。
本発明は、１素子で交流信号をオン／オフ制御することによりロスを低減し、電源周波数より高い周波数でもオン／オフでき、インバータやコンバータを大幅に小型化できる交流スイッチを提供することにある。
本発明は、上記課題を解決するためになされたものであり、本発明の主たる側面は、入力される制御信号によりオン／オフし、第１端子及び第２端子間に入力された交流信号をオン／オフ制御させる交流スイッチであって、前記第１端子に第１主電極が接続され前記第２端子に第２主電極が接続され前記制御信号を入力する制御電極が接続された半導体スイッチと、前記第１端子及び前記第２端子の内の電位が低い端子と前記制御電極との間に前記制御信号を入力する制御信号入力手段と、を有することを特徴とする。However, the conventional AC switch shown in FIG. 1 includes two elements, FETQ4 and FETQ5, instead of one element. Further, since the FET Q4 and the FET Q5 are connected in series, a value obtained by adding the on-resistances of the two elements becomes the entire on-resistance, and the loss increases.
An object of the present invention is to provide an AC switch that can reduce loss by controlling ON / OFF of an AC signal with one element, can be turned ON / OFF even at a frequency higher than a power supply frequency, and can greatly reduce the size of an inverter or converter. .
The present invention has been made to solve the above-described problems, and a main aspect of the present invention is to turn on / off an input AC signal between a first terminal and a second terminal according to an input control signal. An AC switch for on / off control, a semiconductor switch having a first main electrode connected to the first terminal, a second main electrode connected to the second terminal, and a control electrode for inputting the control signal; And control signal input means for inputting the control signal between a terminal having a low potential among the first terminal and the second terminal and the control electrode.

図１は、従来の交流スイッチの回路図である。
図２は、本発明の第１の実施の形態に係る交流スイッチの回路図である。
図３は、本発明の第２の実施の形態に係る交流スイッチの回路図である。
図４は、本発明の第３の実施の形態に係る交流スイッチの回路図である。
図５は、本発明の第４の実施の形態に係る交流スイッチの回路図である。
図６は、本発明の第５の実施の形態に係る交流スイッチの回路図である。
図７は、本発明の第６の実施の形態に係る交流スイッチの回路図である。FIG. 1 is a circuit diagram of a conventional AC switch.
FIG. 2 is a circuit diagram of an AC switch according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram of an AC switch according to the second embodiment of the present invention.
FIG. 4 is a circuit diagram of an AC switch according to the third embodiment of the present invention.
FIG. 5 is a circuit diagram of an AC switch according to the fourth embodiment of the present invention.
FIG. 6 is a circuit diagram of an AC switch according to the fifth embodiment of the present invention.
FIG. 7 is a circuit diagram of an AC switch according to the sixth embodiment of the present invention.

以下、本発明の実施の形態に係る交流スイッチを図面を参照しながら詳細に説明する。
（第１の実施の形態）
第１の実施の形態に係る交流スイッチは、１素子で交流信号をオン／オフ制御することによりロスを低減し、電源周波数より高い周波数でもオン／オフできることを特徴とする。図２は本発明の第１の実施の形態に係る交流スイッチの回路図である。
図２に示す交流スイッチは、第１端子１１と第２端子１２との両端に、ノーマリオン型のＦＥＴＱ１（以下、ＦＥＴＱ１と略称する。）が接続され、第１主電極２１と第２主電極２２とゲートＧとで構成されている。第１主電極２１は第１端子１１に接続され、第２主電極２２は第２端子１２に接続されている。このノーマリオン型のＦＥＴＱ１は、オン抵抗が小さく高耐圧であり、例えばＳｉＣやＧａＮ等の化合物半導体又はＭＥＳＦＥＴからなる。このノーマリオン型のＦＥＴＱ１は、ドレインとソースとが対称に形成されているので、第１端子１１と第２端子１２との内の電位の高い端子に接続された第１主電極２１又は第２主電極２２がドレインとなり、電位の低い端子に接続された他方の主電極がソースとなる。
また、パルス信号等からなるゲート信号を発生するゲート信号部１３の一端は、ＦＥＴＱ１のゲートＧに接続されている。ＦＥＴＱ１の第１主電極２１にはダイオードＤ１のカソードが接続され、ＦＥＴＱ１の第２主電極２２にはダイオードＤ２のカソードが接続されている。ダイオードＤ１のアノードとダイオードＤ２のアノードとはゲート信号部１３の他端に接続され、ダイオードＤ１のアノードとダイオードＤ２のアノードとの接続点とＦＥＴＱ１のゲートＧとの間にゲート信号が入力されるようになっている。
次に、このように構成された第１の実施の形態に係る交流スイッチの動作を説明する。
まず、第１端子１１及び第２端子１２間に交流信号が入力されると、第１端子１１の電位が高く第２端子１２の電位が低い場合には、ＦＥＴＱ１の第１主電極２１がドレインとなり、第２主電極２２がソースとなる。ソースである第２主電極２２の電位に対してゲートＧを高い電位又は零電位とするゲート信号が入力されると、ＦＥＴＱ１がオンし、ダイオードＤ２がオンする。また、このとき、ダイオードＤ１は逆バイアス状態となるので、オフとなる。
次に、第２端子１２の電位が高く第１端子１１の電位が低い場合には、ＦＥＴＱ１の第１主電極２１がソースとなり、第２主電極２２がドレインとなる。ソースである第１主電極２１の電位に対してゲートＧを高い電位又は零電位とするゲート信号が入力されると、ＦＥＴＱ１がオンし、ダイオードＤ１がオンする。また、このとき、ダイオードＤ２は逆バイアス状態となるので、オフとなる。
さらに、第１端子１１の電位が高く第２端子１２の電位が低い場合、及び第２端子１２の電位が高く第１端子１１の電位が低い場合でも、ソースとなる主電極の電位に対してゲートＧを低い電位とするゲート信号が入力されると、ＦＥＴＱ１はオフする。
このように、第１の実施の形態に係る交流スイッチによれば、第１端子１１及び第２端子１２間に交流信号が入力されると、第１端子１１の電位が第２端子１２の電位に対して高くなったり低くなったりするが、ダイオードＤ１，Ｄ２により電位の低い端子を選択し、選択された電位の低い端子（ソース）とゲートＧとの間にゲート信号を入力するので、ＦＥＴＱ１の１素子で交流信号をオン／オフ制御できる。従って、ロスを低減でき、電源周波数より高い周波数でもオン／オフでき、インバータやコンバータを大幅に小型化できる。
（第２の実施の形態）
図３は本発明の第２の実施の形態に係る交流スイッチの回路図である。第２の実施の形態に係る交流スイッチは、第１の実施の形態に係る交流スイッチのダイオードＤ１，Ｄ２に代えて、ＦＥＴＱ２，Ｑ３を設けて、ノイズや漏洩電流による誤動作を防止したことを特徴とする。
図３において、ＦＥＴＱ２，Ｑ３は、ノーマリオフ型のＭＯＳ ＦＥＴ等のスイッチであり、ＦＥＴＱ２のドレインは第１端子１１に接続され、ＦＥＴＱ３のドレインは第２端子１２に接続されている。ＦＥＴＱ２のソースとＦＥＴＱ３のソースとはゲート信号部１３の他端に接続されている。
また、ＦＥＴＱ２及びＦＥＴＱ３の内、電位の低い端子に接続されたＦＥＴのゲートに正電圧のゲート信号を入力することでオンし、電位の高い端子に接続されたＦＥＴのゲートに負電圧のゲート信号を入力することでオフするようになっている。
次に、このように構成された第２の実施の形態に係る交流スイッチの動作を説明する。
まず、第１端子１１の電位が高く第２端子１２の電位が低い場合には、ＦＥＴＱ１の第１主電極２１がドレインとなり、第２主電極２２がソースとなる。ソースである第２主電極２２の電位に対してゲートＧを高い電位又は零電位とするゲート信号が入力され、ＦＥＴＱ３のゲートに正電圧のゲート信号を入力することでオンし、ＦＥＴＱ２のゲートに零電圧又は負電圧のゲート信号を入力することでオフする。このため、ＦＥＴＱ１がオンする。
次に、第２端子１２の電位が高く第１端子１１の電位が低い場合には、ＦＥＴＱ１の第１主電極２１がソースとなり、第２主電極２２がドレインとなる。ソースである第１主電極２１の電位に対してゲートＧを高い電位又は零電位とするゲート信号が入力され、ＦＥＴＱ２のゲートに正電圧のゲート信号を入力することでオンし、ＦＥＴＱ３のゲートに零電圧又は負電圧のゲート信号を入力することでオフする。このため、ＦＥＴＱ１がオンする。
さらに、第１端子１１の電位が高く第２端子１２の電位が低い場合、及び第２端子１２の電位が高く第１端子１１の電位が低い場合でも、ソースとなる主電極の電位に対してゲートＧを低い電位とするゲート信号が入力されると、ＦＥＴＱ１はオフする。
このように第２の実施の形態に係る交流スイッチによれば、第１の実施の形態に係る交流スイッチの効果と同様な効果が得られるとともに、ＦＥＴＱ２，Ｑ３を安定にオンできるので、ノイズや漏洩電流による誤動作を防止できる。
（第３の実施の形態）
図４は本発明の第３の実施の形態に係る交流スイッチの回路図である。第３の実施の形態に係る交流スイッチは、電位の高い端子から抵抗を介してダイオードに電流を流し、ノイズや漏洩電流による誤動作を防止したことを特徴とする。
なお、図４において、図２に示す部分と同一部分には同一符号を付し、同一部分の説明は省略する。
第１端子１１にはダイオードＤ３のアノードが接続され、ダイオードＤ３のカソードは抵抗Ｒ１を介してダイオードＤ１のアノードとダイオードＤ２のアノードとに接続されている。第２端子１２にはダイオードＤ４のアノードが接続され、ダイオードＤ４のカソードは抵抗Ｒ１を介してダイオードＤ１のアノードとダイオードＤ２のアノードとに接続されている。ダイオードＤ１〜４はブリッジ構成されている。
次に、このように構成された第３の実施の形態に係る交流スイッチの動作を説明する。ここでは、ダイオードＤ１，Ｄ２の動作のみを説明する。
まず、第１端子１１の電位が高く第２端子１２の電位が低い場合には、ＦＥＴＱ１の第１主電極２１がドレインとなり、第２主電極２２がソースとなる。このとき、第１端子１１→ダイオードＤ３→抵抗Ｒ１→ダイオードＤ２→第２端子１２と電流が流れる。これにより、ダイオードＤ２がオンし、ダイオードＤ１がオフする。
次に、第２端子１２の電位が高く第１端子１１の電位が低い場合には、ＦＥＴＱ１の第１主電極２１がソースとなり、第２主電極２２がドレインとなる。このとき、第２端子１２→ダイオードＤ４→抵抗Ｒ１→ダイオードＤ１→第１端子１１と電流が流れる。これにより、ダイオードＤ１がオンし、ダイオードＤ２がオフする。
このように、第３の実施の形態に係る交流スイッチによれば、第１の実施の形態に係る交流スイッチの効果と同様な効果が得られるとともに、ダイオードＤ１，Ｄ２を安定にオンできるので、ノイズや漏洩電流による誤動作を防止できる。
（第４の実施の形態）
図５は本発明の第４の実施の形態に係る交流スイッチの回路図である。第４の実施の形態に係る交流スイッチは、ノイズや漏洩電流による誤動作を防止したことを特徴とする。
なお、図５において、図２に示す部分と同一部分には同一符号を付し、同一部分の説明は省略する。ダイオードＤ１と並列に抵抗Ｒ１が接続され、ダイオードＤ２と並列に抵抗Ｒ２が接続されている。
次に、このように構成された第４の実施の形態に係る交流スイッチの動作を説明する。ここでは、ダイオードＤ１，Ｄ２の動作のみを説明する。
まず、第１端子１１の電位が高く第２端子１２の電位が低い場合には、ＦＥＴＱ１の第１主電極２１がドレインとなり、第２主電極２２がソースとなる。このとき、第１端子１１→抵抗Ｒ１→ダイオードＤ２→第２端子１２と電流が流れる。これにより、ダイオードＤ２がオンし、ダイオードＤ１がオフする。
次に、第２端子１２の電位が高く第１端子１１の電位が低い場合には、ＦＥＴＱ１の第１主電極２１がソースとなり、第２主電極２２がドレインとなる。このとき、第２端子１２→抵抗Ｒ２→ダイオードＤ１→第１端子１１と電流が流れる。これにより、ダイオードＤ１がオンし、ダイオードＤ２がオフする。
このように、第４の実施の形態に係る交流スイッチによれば、第１の実施の形態に係る交流スイッチの効果と同様な効果が得られるとともに、ダイオードＤ１，Ｄ２を安定にオンできるので、ノイズや漏洩電流による誤動作を防止できる。
（第５の実施の形態）
図６は本発明の第５の実施の形態に係る交流スイッチの回路図である。第５の実施の形態に係る交流スイッチは、図４に示す第３の実施の形態に係る交流スイッチの構成にさらに、ゲート信号部１３とＦＥＴＱ１のゲートＧとの間に直流電源Ｅを設けたことを特徴とする。直流電源Ｅの正極はＦＥＴＱ１のゲートＧに接続され、直流電源Ｅの負極はゲート信号部１３の一端に接続されている。
このような構成によれば、直流電源Ｅの直流電圧がバイアス電圧としてＦＥＴＱ１のゲートＧに常に印加されるので、ゲート電圧不足が発生しなくなり、ＦＥＴＱ１が誤動作しなくなる。
（第６の実施の形態）
図７は本発明の第６の実施の形態に係る交流スイッチの回路図である。第６の実施の形態に係る交流スイッチは、図５に示す第４の実施の形態に係る交流スイッチの構成にさらに、ゲート信号部１３とＦＥＴＱ１のゲートＧとの間に直流電源Ｅを設けたことを特徴とする。直流電源Ｅの正極はＦＥＴＱ１のゲートＧに接続され、直流電源Ｅの負極はゲート信号部１３の一端に接続されている。
このような構成によれば、直流電源Ｅの直流電圧がバイアス電圧としてＦＥＴＱ１のゲートＧに常に印加されるので、ゲート電圧不足が発生しなくなり、ＦＥＴＱ１が誤動作しなくなる。
なお、第３乃至第６の実施の形態に係る交流スイッチでは、電流を流すために抵抗Ｒ１を用いたが、抵抗Ｒ１に代えて、例えば定電流素子や定電流回路等を用いても良く、これらによれば、低い電圧から高い電圧まで安定に順方向電流を流すことができる。Hereinafter, an AC switch according to an embodiment of the present invention will be described in detail with reference to the drawings.
(First embodiment)
The AC switch according to the first embodiment is characterized in that loss is reduced by ON / OFF control of an AC signal with one element, and ON / OFF can be performed even at a frequency higher than the power supply frequency. FIG. 2 is a circuit diagram of an AC switch according to the first embodiment of the present invention.
In the AC switch shown in FIG. 2, a normally-on type FET Q1 (hereinafter abbreviated as FET Q1) is connected to both ends of a first terminal 11 and a second terminal 12, and a first main electrode 21 and a second main electrode are connected. 22 and a gate G. The first main electrode 21 is connected to the first terminal 11, and the second main electrode 22 is connected to the second terminal 12. This normally-on type FET Q1 has a small on-resistance and a high withstand voltage, and is made of, for example, a compound semiconductor such as SiC or GaN or MESFET. Since the drain and source of the normally-on type FET Q1 are formed symmetrically, the first main electrode 21 or the second main electrode 21 connected to the higher potential terminal of the first terminal 11 and the second terminal 12 is used. The main electrode 22 serves as a drain, and the other main electrode connected to a terminal having a low potential serves as a source.
One end of the gate signal unit 13 for generating a gate signal composed of a pulse signal or the like is connected to the gate G of the FET Q1. The cathode of the diode D1 is connected to the first main electrode 21 of the FET Q1, and the cathode of the diode D2 is connected to the second main electrode 22 of the FET Q1. The anode of the diode D1 and the anode of the diode D2 are connected to the other end of the gate signal unit 13, and a gate signal is input between the connection point between the anode of the diode D1 and the anode of the diode D2 and the gate G of the FET Q1. It is like that.
Next, the operation of the AC switch according to the first embodiment configured as described above will be described.
First, when an AC signal is input between the first terminal 11 and the second terminal 12, when the potential of the first terminal 11 is high and the potential of the second terminal 12 is low, the first main electrode 21 of the FET Q1 is drained. Thus, the second main electrode 22 becomes the source. When a gate signal that makes the gate G higher or zero with respect to the potential of the second main electrode 22 as the source is input, the FET Q1 is turned on and the diode D2 is turned on. At this time, since the diode D1 is in a reverse bias state, it is turned off.
Next, when the potential of the second terminal 12 is high and the potential of the first terminal 11 is low, the first main electrode 21 of the FET Q1 becomes the source and the second main electrode 22 becomes the drain. When a gate signal that makes the gate G higher or zero with respect to the potential of the first main electrode 21 that is the source is input, the FET Q1 is turned on and the diode D1 is turned on. At this time, the diode D2 is in a reverse bias state, and thus is turned off.
Furthermore, even when the potential of the first terminal 11 is high and the potential of the second terminal 12 is low, and even when the potential of the second terminal 12 is high and the potential of the first terminal 11 is low, the potential of the main electrode serving as the source When a gate signal for lowering the gate G is input, the FET Q1 is turned off.
Thus, according to the AC switch according to the first embodiment, when an AC signal is input between the first terminal 11 and the second terminal 12, the potential of the first terminal 11 becomes the potential of the second terminal 12. However, since the low potential terminal is selected by the diodes D1 and D2 and the gate signal is input between the selected low potential terminal (source) and the gate G, the FET Q1 The AC signal can be turned on / off with one element. Therefore, the loss can be reduced, the frequency can be turned on / off at a frequency higher than the power supply frequency, and the inverter and the converter can be greatly downsized.
(Second Embodiment)
FIG. 3 is a circuit diagram of an AC switch according to the second embodiment of the present invention. The AC switch according to the second embodiment is characterized in that FETs Q2 and Q3 are provided in place of the diodes D1 and D2 of the AC switch according to the first embodiment to prevent malfunction due to noise or leakage current. And
In FIG. 3, FETs Q <b> 2 and Q <b> 3 are switches such as normally-off MOS FETs, the drain of the FET Q <b> 2 is connected to the first terminal 11, and the drain of the FET Q <b> 3 is connected to the second terminal 12. The source of the FET Q2 and the source of the FET Q3 are connected to the other end of the gate signal unit 13.
Also, the FET Q2 and the FET Q3 are turned on by inputting a positive voltage gate signal to the gate of the FET connected to the low potential terminal, and the negative voltage gate signal is connected to the FET gate connected to the high potential terminal. It is supposed to be turned off by entering.
Next, the operation of the AC switch according to the second embodiment configured as described above will be described.
First, when the potential of the first terminal 11 is high and the potential of the second terminal 12 is low, the first main electrode 21 of the FET Q1 serves as a drain and the second main electrode 22 serves as a source. A gate signal for setting the gate G to a high potential or zero potential with respect to the potential of the second main electrode 22 as a source is input, and is turned on by inputting a positive voltage gate signal to the gate of the FET Q3, and to the gate of the FET Q2. It is turned off by inputting a zero voltage or negative voltage gate signal. Therefore, the FET Q1 is turned on.
Next, when the potential of the second terminal 12 is high and the potential of the first terminal 11 is low, the first main electrode 21 of the FET Q1 becomes the source and the second main electrode 22 becomes the drain. A gate signal for setting the gate G to a high potential or zero potential with respect to the potential of the first main electrode 21 as a source is input, and is turned on by inputting a positive voltage gate signal to the gate of the FET Q2, and to the gate of the FET Q3. It is turned off by inputting a zero voltage or negative voltage gate signal. Therefore, the FET Q1 is turned on.
Furthermore, even when the potential of the first terminal 11 is high and the potential of the second terminal 12 is low, and even when the potential of the second terminal 12 is high and the potential of the first terminal 11 is low, the potential of the main electrode serving as the source When a gate signal for lowering the gate G is input, the FET Q1 is turned off.
Thus, according to the AC switch according to the second embodiment, the same effect as that of the AC switch according to the first embodiment can be obtained, and the FETs Q2 and Q3 can be stably turned on. Malfunction due to leakage current can be prevented.
(Third embodiment)
FIG. 4 is a circuit diagram of an AC switch according to the third embodiment of the present invention. The AC switch according to the third embodiment is characterized in that a current is passed from a terminal having a high potential through a resistor to a diode to prevent malfunction due to noise or leakage current.
In FIG. 4, the same parts as those shown in FIG. 2 are denoted by the same reference numerals, and the description of the same parts is omitted.
The anode of the diode D3 is connected to the first terminal 11, and the cathode of the diode D3 is connected to the anode of the diode D1 and the anode of the diode D2 via the resistor R1. The anode of the diode D4 is connected to the second terminal 12, and the cathode of the diode D4 is connected to the anode of the diode D1 and the anode of the diode D2 via the resistor R1. The diodes D1 to D4 are configured as a bridge.
Next, the operation of the AC switch according to the third embodiment configured as described above will be described. Here, only the operation of the diodes D1 and D2 will be described.
First, when the potential of the first terminal 11 is high and the potential of the second terminal 12 is low, the first main electrode 21 of the FET Q1 serves as a drain and the second main electrode 22 serves as a source. At this time, a current flows through the first terminal 11 → the diode D3 → the resistor R1 → the diode D2 → the second terminal 12. As a result, the diode D2 is turned on and the diode D1 is turned off.
Next, when the potential of the second terminal 12 is high and the potential of the first terminal 11 is low, the first main electrode 21 of the FET Q1 becomes the source and the second main electrode 22 becomes the drain. At this time, a current flows through the second terminal 12 → the diode D4 → the resistor R1 → the diode D1 → the first terminal 11. As a result, the diode D1 is turned on and the diode D2 is turned off.
Thus, according to the AC switch according to the third embodiment, the same effect as that of the AC switch according to the first embodiment can be obtained, and the diodes D1 and D2 can be stably turned on. Malfunctions due to noise and leakage current can be prevented.
(Fourth embodiment)
FIG. 5 is a circuit diagram of an AC switch according to the fourth embodiment of the present invention. The AC switch according to the fourth embodiment is characterized by preventing malfunction due to noise or leakage current.
5, the same parts as those shown in FIG. 2 are denoted by the same reference numerals, and the description of the same parts is omitted. A resistor R1 is connected in parallel with the diode D1, and a resistor R2 is connected in parallel with the diode D2.
Next, the operation of the AC switch according to the fourth embodiment configured as described above will be described. Here, only the operation of the diodes D1 and D2 will be described.
First, when the potential of the first terminal 11 is high and the potential of the second terminal 12 is low, the first main electrode 21 of the FET Q1 serves as a drain and the second main electrode 22 serves as a source. At this time, a current flows through the first terminal 11 → the resistor R 1 → the diode D 2 → the second terminal 12. As a result, the diode D2 is turned on and the diode D1 is turned off.
Next, when the potential of the second terminal 12 is high and the potential of the first terminal 11 is low, the first main electrode 21 of the FET Q1 becomes the source and the second main electrode 22 becomes the drain. At this time, a current flows through the second terminal 12 → the resistor R 2 → the diode D 1 → the first terminal 11. As a result, the diode D1 is turned on and the diode D2 is turned off.
Thus, according to the AC switch according to the fourth embodiment, the same effect as that of the AC switch according to the first embodiment can be obtained, and the diodes D1 and D2 can be stably turned on. Malfunctions due to noise and leakage current can be prevented.
(Fifth embodiment)
FIG. 6 is a circuit diagram of an AC switch according to the fifth embodiment of the present invention. In the AC switch according to the fifth embodiment, a DC power source E is provided between the gate signal unit 13 and the gate G of the FET Q1 in addition to the configuration of the AC switch according to the third embodiment shown in FIG. It is characterized by that. The positive electrode of the DC power source E is connected to the gate G of the FET Q 1, and the negative electrode of the DC power source E is connected to one end of the gate signal unit 13.
According to such a configuration, the DC voltage of the DC power source E is always applied as the bias voltage to the gate G of the FET Q1, so that the gate voltage is not insufficient and the FET Q1 does not malfunction.
(Sixth embodiment)
FIG. 7 is a circuit diagram of an AC switch according to the sixth embodiment of the present invention. In the AC switch according to the sixth embodiment, a DC power source E is provided between the gate signal unit 13 and the gate G of the FET Q1 in addition to the configuration of the AC switch according to the fourth embodiment shown in FIG. It is characterized by that. The positive electrode of the DC power source E is connected to the gate G of the FET Q 1, and the negative electrode of the DC power source E is connected to one end of the gate signal unit 13.
According to such a configuration, the DC voltage of the DC power source E is always applied as the bias voltage to the gate G of the FET Q1, so that the gate voltage is not insufficient and the FET Q1 does not malfunction.
In the AC switches according to the third to sixth embodiments, the resistor R1 is used to flow current, but instead of the resistor R1, for example, a constant current element, a constant current circuit, or the like may be used. According to these, the forward current can flow stably from a low voltage to a high voltage.

本発明によれば、第１端子及び第２端子間に交流信号が入力されると、第１端子の電位が高く第２端子の電位が低い場合には、第２端子と制御電極との間に制御信号が入力されて半導体スイッチがオンし、また、第２端子の電位が高く第１端子の電位が低い場合には、第１端子と制御電極との間に制御信号が入力されて半導体スイッチがオンする。また、制御信号が制御電極に入力されない場合には、半導体スイッチはオフする。このため、一素子で交流信号をオン／オフ制御することによりロスを低減し、電源周波数より高い周波数でもオン／オフでき、インバータやコンバータを大幅に小型化できる交流スイッチを提供することができる。  According to the present invention, when an AC signal is input between the first terminal and the second terminal, when the potential of the first terminal is high and the potential of the second terminal is low, the second terminal is connected to the control electrode. When the control signal is input to the semiconductor switch to turn on, and when the potential of the second terminal is high and the potential of the first terminal is low, the control signal is input between the first terminal and the control electrode and the semiconductor The switch turns on. When the control signal is not input to the control electrode, the semiconductor switch is turned off. For this reason, it is possible to provide an AC switch capable of reducing loss by controlling ON / OFF of an AC signal with a single element, enabling ON / OFF even at a frequency higher than the power supply frequency, and greatly reducing the size of an inverter or converter.

Claims (9)

入力される制御信号によりオン／オフし、第１端子及び第２端子間に入力された交流信号をオン／オフ制御させる交流スイッチであって、
前記第１端子に第１主電極が接続され前記第２端子に第２主電極が接続され前記制御信号を入力する制御電極が接続された半導体スイッチと、
前記第１端子及び前記第２端子の内の電位が低い端子と前記制御電極との間に前記制御信号を入力する制御信号入力手段と、
を有することを特徴とする。An AC switch that is turned on / off by a control signal that is input and that controls on / off of an AC signal input between the first terminal and the second terminal;
A semiconductor switch having a first main electrode connected to the first terminal, a second main electrode connected to the second terminal, and a control electrode for inputting the control signal;
Control signal input means for inputting the control signal between a terminal having a low potential among the first terminal and the second terminal and the control electrode;
It is characterized by having. 請求項１記載の交流スイッチであって、
前記制御信号入力手段は、
前記半導体スイッチの前記第１主電極に一方の電極が接続された第１ダイオードと、
前記半導体スイッチの前記第２主電極に一方の電極が接続され他方の電極が前記第１ダイオードの他方の電極に接続された第２ダイオードと、
を有し、
前記第１ダイオードの他方の電極と前記第２ダイオードの他方の電極との接続点と前記制御電極との間に前記制御信号を入力することを特徴とする。The AC switch according to claim 1,
The control signal input means includes
A first diode having one electrode connected to the first main electrode of the semiconductor switch;
A second diode having one electrode connected to the second main electrode of the semiconductor switch and the other electrode connected to the other electrode of the first diode;
Have
The control signal is input between a connection point between the other electrode of the first diode and the other electrode of the second diode and the control electrode. 請求項２記載の交流スイッチであって、
前記第１端子及び前記第２端子の内の電位が高い端子から電位が低い端子に接続された前記ダイオードに電流を流す電流供給手段、
を更に有することを特徴とする。The AC switch according to claim 2,
Current supply means for passing current to the diode connected to the low potential terminal from the high potential terminal of the first terminal and the second terminal;
It further has these. 請求項３記載の交流スイッチであって、
前記電流供給手段は、
前記第１ダイオードの他方の電極と前記第２ダイオードの他方の電極との接続点と前記第１端子との間に接続され、第３ダイオードと抵抗とが直列に接続された直列回路と、
前記第３ダイオードと前記抵抗との接続点と前記第２端子との間に接続された第４ダイオードと、
を有することを特徴とする。The AC switch according to claim 3,
The current supply means includes
A series circuit connected between a connection point of the other electrode of the first diode and the other electrode of the second diode and the first terminal, and a third diode and a resistor connected in series;
A fourth diode connected between a connection point between the third diode and the resistor and the second terminal;
It is characterized by having. 請求項３記載の交流スイッチであって、
前記電流供給手段は、
前記第１ダイオードに並列に接続された第１抵抗と、
前記第２ダイオードに並列に接続された第２抵抗と、
を有することを特徴とする。The AC switch according to claim 3,
The current supply means includes
A first resistor connected in parallel to the first diode;
A second resistor connected in parallel to the second diode;
It is characterized by having. 請求項４又は５記載の交流スイッチであって、
前記半導体スイッチの前記制御電極に直流電圧を印加する直流電源、
を更に有することを特徴とする。The AC switch according to claim 4 or 5,
A DC power supply for applying a DC voltage to the control electrode of the semiconductor switch;
It further has these. 請求項１記載の交流スイッチであって、
前記制御信号入力手段は、
前記半導体スイッチの前記第１主電極に第１電極が接続された第１スイッチと、
前記半導体スイッチの前記第２主電極に第３電極が接続され第４電極が前記第１スイッチの第２電極に接続された第２スイッチと、
を有し、
前記第１スイッチの第２電極と前記第２スイッチの第４電極との接続点と前記制御電極との間に前記制御信号を入力し、
前記第１スイッチ及び第２スイッチの内、前記電位の低い端子に接続されたスイッチをオンし、前記電位の高い端子に接続されたスイッチをオフすることを特徴とする。The AC switch according to claim 1,
The control signal input means includes
A first switch having a first electrode connected to the first main electrode of the semiconductor switch;
A second switch in which a third electrode is connected to the second main electrode of the semiconductor switch and a fourth electrode is connected to a second electrode of the first switch;
Have
The control signal is input between a connection point between the second electrode of the first switch and the fourth electrode of the second switch and the control electrode,
Of the first switch and the second switch, a switch connected to the low potential terminal is turned on, and a switch connected to the high potential terminal is turned off. 請求項１乃至請求項７のいずれか１項記載の交流スイッチであって、前記半導体スイッチは、ノーマリオン型のスイッチであることを特徴とする。8. The AC switch according to claim 1, wherein the semiconductor switch is a normally-on type switch. 請求項８記載の交流スイッチであって、
前記ノーマリオン型のスイッチは、化合物半導体からなることを特徴とする。The AC switch according to claim 8, wherein
The normally-on type switch is made of a compound semiconductor.
JP2005507191A 2003-06-23 2004-05-20 AC switch Expired - Fee Related JP4123274B2 (en)

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PCT/JP2004/007200 WO2004114508A1 (en) 2003-06-23 2004-05-20 Ac switch

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JP2009124667A (en) * 2007-01-25 2009-06-04 Panasonic Corp Bidirectional switch and driving method thereof
JP5369434B2 (en) 2007-12-21 2013-12-18 サンケン電気株式会社 Bidirectional switch
JP5130906B2 (en) 2007-12-26 2013-01-30 サンケン電気株式会社 Switch device
JP5407349B2 (en) * 2009-01-15 2014-02-05 ダイキン工業株式会社 Switch circuit
JP4893819B2 (en) * 2009-12-28 2012-03-07 サンケン電気株式会社 Bidirectional switch
JP5761656B2 (en) * 2011-06-27 2015-08-12 サンケン電気株式会社 Gate drive circuit
JP5183814B1 (en) * 2012-06-28 2013-04-17 株式会社アドバンテスト Switch device and test device
JP6306962B2 (en) * 2014-07-16 2018-04-04 株式会社アドバンテスト Semiconductor switch and test apparatus using the same

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JPH07336208A (en) * 1994-06-08 1995-12-22 Philips Electron Nv Logic circuit device
JPH08149826A (en) * 1994-11-25 1996-06-07 Matsushita Electric Works Ltd Power converter
JPH0934564A (en) * 1995-07-18 1997-02-07 Chiyoda:Kk Input waveform tracking type AC power supply
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