JPWO2004023559A1 - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

A tunnel insulating film (3) is formed in the element region partitioned by the element isolation insulating film (2). Thereafter, a floating gate (4) is formed for each memory cell, and an ONO antinode (5) and a control gate (6) are further formed. Next, a plasma insulating film (7) is formed on the surface of the stacked gate. The plasma insulating film is not affected by the surface orientation of the base film. Accordingly, since the thickness of the plasma insulating film (7) is substantially uniform throughout the entire film, hydrogen does not enter when the insulating film is subsequently formed without increasing the maximum film thickness as much as the thermal oxide film. In addition to preventing, it is possible to prevent the escape of electrons. By reducing the thickness of the insulating film, the bird's beak can be reduced, and the efficiency at the time of erasing and writing data can be improved.

Description

  The present invention relates to a semiconductor memory device suitable for a flash memory and a manufacturing method thereof.

A flash memory is a non-volatile semiconductor memory device that stores data by holding charges in a storage film such as a floating gate or a nitride film under a gate electrode. When charge is accumulated in the floating gate, charge is transferred between the channel and the floating gate through the gate insulating film. Further, when charge is accumulated in the nitride film in the ONO film as the storage film, the charge is accumulated in the insulating film itself. Therefore, the electrical characteristics of these insulating films need to be stable. If the characteristics of these insulating films are unstable, even if the same control voltage is applied, data “1” is stored in one memory cell, whereas “0” is stored in another memory cell. There is a possibility that the data will be stored, and the reliability is extremely low.
Further, not only these insulating films but also an insulating film formed around the floating gate or the gate electrode is required to have stable characteristics. This insulating film is formed for the following purpose. After the floating gate or gate electrode is formed, a side wall insulating film for forming an LDD structure later is formed on these sides, and an interlayer insulating film covering the floating gate or gate electrode is further formed. At this time, if the floating gate or the gate electrode is in direct contact with the sidewall insulating film or the interlayer insulating film, electrons may escape from the floating gate or the gate electrode to the sidewall insulating film or the like. As a result, the electrical characteristics of the floating gate or gate electrode will fluctuate. In the step for forming the sidewall insulating film and the interlayer insulating film, a gas containing hydrogen may be used. At this time, when the hydrogen reaches the gate insulating film or the storage film, hydrogen deterioration or the like occurs, and the characteristics of the gate insulating film or the storage film change.
In order to prevent such fluctuation, an insulating film is formed around the gate electrode. In order to achieve such an object, the insulating film is formed by thermal oxidation at about 900 ° C. so that the thickest portion has a thickness of 12 nm or more. The thickness of the insulating film is set to 12 nm or more in the thickest part. When the oxide film is formed by thermal oxidation, the growth of the oxide film depends on the plane orientation of the underlying film, for example, the silicon film constituting the gate electrode. The speed is different. Therefore, the thickness of the thermal oxide film is non-uniform, and this thickness is required to sufficiently prevent hydrogen from entering even at the thinnest portion.
FIG. 13 is a cross-sectional view showing a method of manufacturing a conventional floating gate type memory. In this conventional manufacturing method, a stacked gate including a tunnel oxide film 52, a floating gate 53, an intergate insulating film 54, and a control gate 55 is formed on a semiconductor substrate 51, and then thermal oxidation is performed. As a result, as shown in FIG. 13, a thermal oxide film 56 having large unevenness and non-uniform thickness is formed.
FIG. 14 is a cross-sectional view showing a conventional SONOS type memory manufacturing method. In this conventional manufacturing method, a bit line diffusion layer 62 is formed on the surface of a semiconductor substrate 61, and a storage insulating film 66 composed of a tunnel oxide film 63, a nitride film 64, and a top film 65 is formed thereon. Further, a gate electrode 67 is formed on the storage insulating film 66, and then thermal oxidation is performed. As a result, as shown in FIG. 14, a thermal oxide film 68 having large unevenness and non-uniform thickness is formed.
However, in the semiconductor memory device formed by the method as described above, the bird's beak is large and the coupling is lowered. Such a decrease in coupling leads to a problem that the erasing efficiency decreases. In particular, in the memory in which erasing is performed in the vicinity of the end portion of the gate electrode and in the memory in which erasing is performed on the entire channel, the erasing efficiency is significantly reduced. Further, as the bird's beak is generated, the insulating film in the portion becomes thick, so that not only the erasing efficiency but also the data writing efficiency is lowered.
Further, there is a problem that it is difficult to stabilize the characteristics of the finally manufactured semiconductor memory device. One of the causes is that when performing thermal oxidation, a plurality of wafers are processed at the same time. At this time, it is extremely difficult to keep the temperature in the heating furnace constant. It is done. Another possible cause is that impurities such as phosphorus introduced into the floating gate or the like as a result of thermal oxidation tend to segregate at the peripheral edge.
The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor memory device capable of improving efficiency at the time of erasing and writing data and stabilizing characteristics and a manufacturing method thereof. To do.

As a result of diligent study, the inventors of the present application have formed a large bird's beak and segregated impurities due to the thermal oxidation of the oxide film that covers the stacked gate and the like in the conventional semiconductor memory device manufacturing method. I found out. The inventor of the present application has found that the above-described problems can be solved by adopting plasma treatment as a method for forming a good and dense insulating film without performing thermal oxidation. I came up with various aspects.
According to the first method of manufacturing a semiconductor memory device of the present invention, after forming a stacked gate including a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate sequentially stacked on a semiconductor substrate, the stacked memory is formed. An insulating interlayer is formed on the surface of the gate by a plasma oxidation method, a plasma nitriding method, or a series of processes including any of these, and the buried gate covered with the covering insulating film is embedded. It is characterized by forming.
A first semiconductor memory device according to the present invention manufactured by such a method includes a semiconductor substrate and a stack including a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate sequentially stacked on the semiconductor substrate. A gate insulating film that covers the stacked gate, and an interlayer insulating film that embeds the stacked gate covered with the coating insulating film. In this semiconductor memory device, the covering insulating film is made of one kind of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film, and a plasma oxynitride film.
According to the second method of manufacturing the semiconductor memory device of the present invention, a storage insulating film including a nitride film having a charge trapping function is formed on a semiconductor substrate, and a gate is formed on the semiconductor substrate via the storage insulating film. After forming the electrode, a coating insulating film is formed on the surfaces of the storage insulating film and the gate electrode by a plasma oxidation method, a plasma nitriding method, or a series of steps including any of these, and further, the coating insulating film An interlayer insulating film is formed to fill the storage insulating film and the gate electrode, which are covered with metal.
A second semiconductor memory device according to the present invention manufactured by such a method includes a semiconductor substrate, a storage insulating film formed on the semiconductor substrate and including a nitride film having a charge trapping function, and the storage insulating film A gate electrode formed on the semiconductor substrate, a storage insulation film covering the storage insulation film and the gate electrode, and an interlayer insulation embedding the storage insulation film and the gate electrode covered by the coating insulation film And a membrane. In this semiconductor memory device, the covering insulating film is formed of one type of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film, and a plasma oxynitride film.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the first embodiment of the present invention.
2A and 2B are views showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the next process of the process shown in FIGS. 1A and 1B1.
3A and 3B are views showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the next step of the step shown in FIGS. 2A and 2B.
4A and 4B are views showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the next step of the step shown in FIGS. 3A and 3B.
5A and 5B are views showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the next step of the step shown in FIGS. 4A and 4B.
6A and 6B are views showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the next process after the process shown in FIGS. 5A and 5B.
FIG. 7 is a cross-sectional view showing a state of the plasma insulating film 7 in the first embodiment of the present invention.
8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the second embodiment of the present invention.
9A and 9B are views showing a method of manufacturing the semiconductor memory device according to the second embodiment of the present invention, and are cross-sectional views showing the next step of the step shown in FIGS. 8A and 8B.
10A and 10B are views showing the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention, and are cross-sectional views showing the next process of the process shown in FIGS. 9A and 9B.
FIG. 11 is a cross-sectional view showing the state of the plasma insulating film in the second embodiment of the present invention.
FIG. 12 is a schematic diagram showing a schematic configuration of a plasma processing apparatus including a radial line slot antenna that can be used in an embodiment of the present invention.
FIG. 13 is a cross-sectional view showing a method of manufacturing a conventional floating gate type memory.
FIG. 14 is a cross-sectional view showing a conventional SONOS type memory manufacturing method.

Hereinafter, a semiconductor memory device and a manufacturing method thereof according to embodiments of the present invention will be specifically described with reference to the accompanying drawings. For convenience, the structure of the semiconductor memory device will be described together with its formation method.
(First embodiment)
First, a first embodiment of the present invention will be described. In the first embodiment, the present invention is applied to a semiconductor memory device having a stacked gate structure. FIG. 1A, FIG. 1B thru | or FIG. 6A, FIG. 6B are sectional drawings which show the manufacturing method of the semiconductor memory device based on the 1st Embodiment of this invention in order of a process.
In the semiconductor memory device according to the first embodiment, a plurality of word lines and bit lines are formed in a lattice shape so as to be orthogonal to each other. One memory cell is formed in the vicinity of each lattice point. 1B to 6A correspond to cross sections orthogonal to the bit lines, and FIGS. 1B to 6B correspond to cross sections orthogonal to the word lines. Accordingly, FIGS. 1A and 1B show cross sections orthogonal to each other. The same applies to the other FIGS. 2A, 2B to 6A, and 6B.
In this embodiment, in manufacturing the semiconductor memory device having the layout configuration as described above, first, as shown in FIGS. 1A and 1B, the surface of the semiconductor substrate 1 such as a silicon substrate is formed by, for example, the LOCOS method. Then, the element isolation insulating film 2 is formed. Next, in order to prevent punch-through below the element isolation insulating film 2, an impurity such as boron is ion-implanted over the entire surface to form the diffusion layer 1a. Furthermore, in order to adjust the threshold voltage of the memory cell, an impurity such as boron is ion-implanted into the element region partitioned by the element isolation insulating film 2, thereby forming the diffusion layer 1b.
In forming these word lines, bit lines, and LOCOS, the smaller the minimum line width is, the more effective the present invention is. Specifically, the effect is effective when the thickness is 0.5 μm or less, and the effect is particularly remarkable when the thickness is 0.25 μm or less. This is because if the line width is narrow, the bird's beak width cannot be ignored. The same applies to the second embodiment.
Next, a tunnel insulating film 3 made of, for example, a silicon oxide film is formed in the element region partitioned by the element isolation insulating film 2. Thereafter, a floating gate 4 is formed for each memory cell, and an ONO film (inter-gate insulating film) 5 and a control gate (word line) 6 are further formed. In forming the floating gate 4, for example, after forming a polysilicon film, an impurity such as boron is introduced into the polysilicon film by, for example, ion implantation. The ONO film 5 includes a silicon nitride film, a silicon oxide film, and a silicon nitride film that are sequentially stacked. A stacked gate is composed of a stacked body of the tunnel insulating film 3, the floating gate 4, the ONO film 5 and the control gate 6.
At this time, the effect of the present invention is exhibited as the impurity concentration in the floating gate increases. Specifically, it is effective if it is 1 × 10 ¹⁸ / cm ³ or more, and particularly remarkable if it is about 1 × 10 ¹⁹ / cm ³ . This is because the segregation of impurities occurs in the high-temperature heat treatment and the quality deteriorates in the insulating film around the floating gate, whereas this occurs in the sidewall film formation by low-temperature oxidation / nitridation / oxynitridation, which is a feature of the present invention. Because there is no. This segregation is particularly noticeable when the impurity is phosphorus.
Furthermore, in the formation of the ONO film 5, the effect of the present invention is exhibited as the thickness is smaller. Specifically, it is effective if the total physical film thickness is 40 nm or less, and particularly remarkable if it is 20 nm or less. This is because if the ONO film is thin, the thickness of the bird's beak cannot be ignored compared to the thickness of the ONO film itself. More specifically, the bottom oxide film of the ONO film is noticeable at 10 nm or less, particularly 7 nm or less, the nitride film is noticeable at 20 nm or less, particularly 10 nm or less, and the top oxide film is noticeable at 10 nm or less, particularly 7 nm or less. It is. The same applies to the second embodiment.
Next, as shown in FIGS. 2A and 2B, the plasma insulating film (covering insulation) is formed on the upper and side surfaces of the control gate 6 and the side surfaces of the ONO film 5, the floating gate 4 and the tunnel insulating film 3, that is, on the surface of the stacked gate. Film) 7 is formed. At this time, the plasma insulating film 7 is also formed on the surface of the semiconductor substrate 1. As the plasma insulating film 7, a plasma oxide film, a plasma nitride film, or a plasma oxynitride film can be formed. The formation of the plasma insulating film 7 is preferably performed in a temperature range of 650 ° C. or less, and may be performed at, for example, about 450 ° C. The thickness of the plasma insulating film 7 is preferably 9 nm or less, for example, about 8 nm.
Subsequently, ion implantation is performed using the stacked gate as a mask, and further heat treatment is performed, thereby forming the low-concentration diffusion layer 9 in a self-aligned manner as shown in FIGS. 3A and 3B.
At this time, the low-concentration diffusion layer is diffused under the gate by heat treatment, but it is necessary to ensure that the reach distance from the edge of the gate exceeds at least the bird's beak. In the present invention, by suppressing the bird's beak, the wraparound of the low concentration diffusion layer under the gate can be reduced. Since device miniaturization is limited by the punch-through current from the diffusion layer, the present invention greatly contributes to device miniaturization.
Next, as shown in FIGS. 4A and 4B, a sidewall insulating film 10 is formed on the side surface of the stacked gate. The sidewall insulating film 10 is formed, for example, by forming an HTO film (high temperature oxide film) and then subjecting it to isotropic etching. By this isotropic etching, a portion of the plasma insulating film 7 formed on the surface of the semiconductor substrate 1 that is not finally covered with the sidewall insulating film 10 is removed, and a part of the surface of the semiconductor substrate 1 is exposed. To do.
Thereafter, as shown in FIGS. 5A and 5B, by using the stacked gate and sidewall insulating film 10 as a mask, ion implantation is performed at a higher concentration than when the low concentration diffusion layer 9 is formed, and further heat treatment is performed. Then, the high concentration diffusion layer 11 is formed.
Next, as shown in FIGS. 6A and 6B, an interlayer insulating film 12 is formed on the entire surface. The interlayer insulating film 12 is formed by depositing a silicon oxide film by, for example, the CVD method.
Subsequently, contact holes and wirings are formed and the semiconductor memory device is completed.
In such a first embodiment, as shown in FIGS. 2A and 2B, the insulating film covering the stacked gate is the plasma insulating film 7. Unlike the thermal oxide film, the plasma insulating film is not affected by the surface orientation of the base film. Therefore, as shown in FIG. 7, since the thickness of the plasma insulating film 7 is substantially uniform throughout, the side wall insulating film 10 or the interlayer insulating film does not have to be as thick as the thermal oxide film. In addition to preventing the entry of hydrogen when forming the film 12, it is also possible to prevent the escape of electrons. By reducing the thickness of the insulating film, the bird's beak can be reduced, and the efficiency at the time of erasing and writing data can be improved.
In a floating gate type semiconductor memory device, when data is written and erased, charge is transferred between the floating gate and the semiconductor substrate, and information is read depending on whether or not the charge is trapped in the floating gate. It is. Therefore, as described above, by reducing the bird's beak, charge transfer is facilitated, so that the efficiency of erasure and the like is improved.
Further, in forming the plasma insulating film 7, the plurality of wafers are not processed in one heating furnace. Therefore, it is not affected by the non-uniformity of the furnace temperature. Furthermore, the plasma insulating film 7 can be formed at an extremely low temperature compared to the thermal oxide film. Accordingly, segregation of impurities in the floating gate 4, such as phosphorus, is extremely difficult to occur. Therefore, it is possible to obtain a semiconductor memory device having stable characteristics among a plurality of wafers.
(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the second embodiment, the present invention is applied to a semiconductor memory device having a so-called SONOS structure. FIG. 8A, FIG. 8B thru | or FIG. 10A, FIG. 10B are sectional drawings which show the manufacturing method of the semiconductor memory device based on the 2nd Embodiment of this invention in order of a process. The SONOS structure is a structure of a nitride film charge storage memory having a source / drain also serving as a buried bit line and having a channel parallel to a word line (gate electrode), and has a buried bit line structure.
Also in the second embodiment, a plurality of word lines and bit lines are formed in a lattice shape so as to be orthogonal to each other. One memory cell is formed in the vicinity of each lattice point. As in the first embodiment, FIGS. 8A to 10A correspond to cross sections orthogonal to the bit lines, and FIGS. 8B to 10B correspond to cross sections orthogonal to the word lines. Therefore, FIGS. 8A and 8B show cross sections orthogonal to each other. The same applies to the other FIGS. 9A, 9B, 10A, and 10B.
In this embodiment, when manufacturing the semiconductor memory device having the layout configuration as described above, first, as shown in FIGS. 8A and 8B, a resist film is masked on the surface of the semiconductor substrate 21 such as a silicon substrate. As a result, a bit line diffusion layer (bit line) 22 is formed.
Next, a silicon oxide film, a silicon nitride film, a silicon oxide film, and a polysilicon film are sequentially stacked, and these are patterned to sequentially stack the tunnel insulating film 23, the silicon nitride film 24, the top film 25, and the control gate. A stacked body composed of (word lines (gate electrodes)) 26 is formed. When forming the control gate 26, for example, after forming a polysilicon film, impurities such as boron are introduced into the polysilicon film by, for example, ion implantation. The tunnel insulating film 23 is made of a silicon oxide film, and the top film 25 is made of a silicon oxide film. A storage insulating film 29 is composed of the tunnel insulating film 23, the silicon nitride film 24 and the top film 25. The control gate 26 is made of a polysilicon film.
Thereafter, as shown in FIGS. 9A and 9B, a plasma insulating film (covering insulating film) 27 is formed on the upper and side surfaces of the control gate 26 and the side surfaces of the tunnel insulating film 23, the storage film 24, and the top film 25. At this time, the plasma insulating film 27 is also formed on the surface of the semiconductor substrate 21. As the plasma insulating film 27, a plasma oxide film, a plasma nitride film, or a plasma oxynitride film can be formed in the same manner as the plasma insulating film 7 in the first embodiment. The formation of the plasma insulating film 27 is preferably performed in a temperature range of 650 ° C. or less, and may be performed at, for example, about 450 ° C. The thickness of the plasma insulating film 27 is preferably 9 nm or less, for example, about 8 nm.
The heat treatment at this time diffuses impurities in the buried bit line toward the center of the channel. However, in the present invention, diffusion of impurities in the buried bit line can be reduced by low-temperature treatment. Since device miniaturization is limited by the punch-through current from the diffusion layer, the present invention greatly contributes to device miniaturization.
Subsequently, as shown in FIGS. 10A and 10B, an interlayer insulating film 28 is formed on the entire surface. The interlayer insulating film 28 is formed, for example, by depositing a silicon oxide film by a CVD method.
Then, contact holes and wirings are formed to complete the semiconductor memory device.
Also in the second embodiment, as shown in FIGS. 9A and 9B, the insulating film covering the side surface of the storage film 24 is used as the plasma insulating film 27. Therefore, as shown in FIG. 11, since the thickness of the plasma insulating film 27 is substantially uniform throughout, the maximum film thickness does not have to be as thick as the thermal oxide film as in the first embodiment. In addition, it is possible to prevent hydrogen from entering and electrons to escape when forming the interlayer insulating film 28. As a result, the bird's beak can be kept small, and the efficiency in erasing and writing data can be improved.
In a SONOS type semiconductor memory device, in writing and erasing data, charge is transferred between a storage film made of a silicon nitride film and a semiconductor substrate, and an interface between the storage film and a tunnel insulating film below the storage film Information is read out depending on whether or not charges are trapped in the vicinity. Therefore, as described above, by reducing the bird's beak, charge transfer is facilitated, so that the efficiency of erasure and the like is improved.
In addition, as in the first embodiment, it is possible to avoid instability of characteristics due to non-uniform deposition temperature and phosphorus segregation.
In the second embodiment, the sidewall insulating film is not formed on the side of the control gate 26, but a sidewall insulating film may be formed. Such a sidewall insulating film may be formed at the same time as the sidewall insulating film of a transistor constituting a peripheral circuit, for example.
In the formation of the plasma oxide film, for example, radical O ^* , radical N ^* or radical NH ^* is generated in a plasma atmosphere of a gas containing O ₂ , N ₂ or NH ₃ . At this time, the source gas used during the growth of the plasma insulating film may contain a rare gas such as Kr or Ar, or H ₂ .
Further, the plasma oxynitride film and the plasma nitride film forming method and the plasma processing apparatus used for the formation are not particularly limited, but the following apparatus is used to form the plasma oxynitride film or plasma nitride film. May be formed.
Specifically, a plasma oxynitride film or a plasma nitride film is formed using a plasma processing apparatus provided with a radial line slot antenna as shown in FIG. In this plasma processing apparatus 100, a gate valve 102 communicated with a cluster tool 101 and a workpiece W (in this embodiment, a semiconductor substrate 1) are placed, and a cooling jacket 103 that cools the workpiece W during plasma processing. A processing chamber 105 that can accommodate the susceptor 104, a high vacuum pump 106 connected to the processing chamber 105, a microwave source 110, an antenna member 120, and a bias that constitutes ion plating together with the antenna member 120. The high-frequency power supply 107 and the matching box 108, gas supply systems 130 and 140 having gas supply rings 131 and 141, and a temperature control unit 150 that controls the temperature of the workpiece W are configured.
The microwave source 110 is made of, for example, a magnetron, and can usually generate a microwave of 2.45 GHz (for example, 5 kW). Thereafter, the transmission form of the microwave is converted into a TM, TE, or TEM mode by the mode converter 112.
The antenna member 120 includes a temperature control plate 122, a storage member 123, and (a dielectric plate 230). The temperature control plate 122 is connected to the temperature control device 121, and the storage member 123 stores a slow wave material 124 and a slot electrode (not shown) that contacts the slow wave material 124. This slot electrode is referred to as a radial line slot antenna (RLSA) or an ultra-high efficiency planar antenna. However, in this embodiment, other types of antennas such as a single-layer waveguide planar antenna, a dielectric substrate parallel plate slot array, and the like may be applied.
When film formation is performed using a plasma processing apparatus equipped with such a radial line slot antenna, the ion irradiation energy of plasma is preferably 7 eV or less, and the potential energy of plasma is preferably 10 eV or less.
Then, the plasma insulating film can be formed by a plasma oxidation method, a plasma nitridation method, or a series of steps including at least one of these using the above-described plasma processing apparatus.
In the above-described embodiment, the present invention is applied to a floating gate type or a SONOS type. However, forms to which the present invention is applicable are not limited to these. For example, the present invention can also be applied to an MNOS type semiconductor memory device. When the present invention is applied to an MNOS type semiconductor memory device, a silicon oxide film and a silicon nitride film are sequentially stacked on a semiconductor substrate to form a storage insulating film, and then a gate electrode is formed thereon. Subsequently, a plasma insulating film is formed on the surfaces of the storage insulating film and the gate electrode.

  According to the present invention, since the coating insulating film covering the floating gate or the gate electrode is formed by plasma processing, high-temperature heat treatment is unnecessary, bird's beak is suppressed, writing and erasing efficiency is high, and stable characteristics. Can be obtained.

Claims (34)

A semiconductor substrate;
A stacked gate including a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate sequentially stacked on the semiconductor substrate;
A coating insulating film covering the stacked gate;
An interlayer insulating film for embedding the stacked gate covered with the covering insulating film;
In a semiconductor memory device having
The semiconductor insulating device is characterized in that the covering insulating film is made of one kind of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film, and a plasma oxynitride film. The semiconductor memory device according to claim 1, wherein phosphorus is introduced into the floating gate. The semiconductor memory device according to claim 1, wherein a thickness of the covering insulating film is 9 nm or less. 2. The semiconductor memory device according to claim 1, wherein an impurity concentration in the floating gate is 1 × 10 ¹⁸ / cm ³ or more. 2. The semiconductor memory device according to claim 1, wherein a thickness of the inter-gate insulating film is 40 nm or less. The semiconductor memory device according to claim 1, further comprising a sidewall insulating film formed on a side of the covering insulating film. A semiconductor substrate;
A storage insulating film formed on the semiconductor substrate and including a nitride film having a charge trapping function;
A gate electrode formed on the semiconductor substrate via the storage insulating film;
A covering insulating film covering the storage insulating film and the gate electrode;
An interlayer insulating film embedded in the storage insulating film and the gate electrode covered with the covering insulating film;
In a semiconductor memory device having
The semiconductor insulating device is characterized in that the covering insulating film is made of one kind of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film, and a plasma oxynitride film. 8. The semiconductor memory device according to claim 7, wherein phosphorus is introduced into the gate electrode. The storage insulating film is
The nitride film;
A first oxide film formed between the nitride film and the semiconductor substrate;
8. The semiconductor memory device according to claim 7, further comprising: 10. The semiconductor memory device according to claim 9, wherein the storage insulating film further includes a second oxide film formed between the nitride film and the gate electrode. 8. The semiconductor memory device according to claim 7, further comprising a sidewall insulating film formed on a side of the covering insulating film. Forming a stacked gate including a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate sequentially stacked on a semiconductor substrate;
Forming a coating insulating film on the surface of the stacked gate by a plasma oxidation method, a plasma nitridation method, or a series of steps including any of these,
Forming an interlayer insulating film for embedding the stacked gate covered with the covering insulating film;
A method for manufacturing a semiconductor memory device, comprising: 13. The method of manufacturing a semiconductor memory device according to claim 12, further comprising a step of introducing phosphorus into the floating gate before the step of forming the covering insulating film. The method of manufacturing a semiconductor memory device according to claim 12, wherein a thickness of the covering insulating film is 9 nm or less. The method of manufacturing a semiconductor memory device according to claim 12, wherein an impurity concentration in the floating gate is 1 × 10 ¹⁸ / cm ³ or more. 13. The method of manufacturing a semiconductor memory device according to claim 12, wherein the thickness of the inter-gate insulating film is 40 nm or less. 13. The method of manufacturing a semiconductor memory device according to claim 12, further comprising a step of forming a sidewall insulating film on a side of the insulating film. 13. The step of forming the covering insulating film is performed in a plasma atmosphere of a source gas containing at least one kind of molecule selected from the group consisting of O ₂ , N ₂ and NH _3. A manufacturing method of the semiconductor memory device according to the above. The method of manufacturing a semiconductor memory device according to claim 12, wherein the step of forming the covering insulating film is performed within a temperature range of 650 ° C. or lower. Forming a storage insulating film including a nitride film having a charge trapping function on a semiconductor substrate;
Forming a gate electrode on the semiconductor substrate via the storage insulating film;
Forming a coating insulating film on the surfaces of the storage insulating film and the gate electrode by a series of processes including a plasma oxidation method, a plasma nitridation method, or any of these;
Forming an interlayer insulating film that embeds the storage insulating film and the gate electrode covered with the covering insulating film;
A method for manufacturing a semiconductor memory device, comprising: 21. The method of manufacturing a semiconductor memory device according to claim 20, further comprising a step of introducing phosphorus into the gate electrode before the step of forming the covering insulating film. The step of forming the storage insulating film includes:
Forming a first oxide film on the semiconductor substrate;
Forming the nitride film on the first oxide film;
21. The method of manufacturing a semiconductor memory device according to claim 20, further comprising: 23. The method of manufacturing a semiconductor memory device according to claim 22, wherein the step of forming the storage insulating film further includes a step of forming a second oxide film on the nitride film. 21. The method of manufacturing a semiconductor memory device according to claim 20, further comprising a step of forming a sidewall insulating film on a side of the insulating film. 21. The step of forming the covering insulating film is performed in a plasma atmosphere of a source gas containing at least one molecule selected from the group consisting of O ₂ , N _2, and NH _3. A manufacturing method of the semiconductor memory device according to the above. The step of forming the covering insulating film includes a step of generating at least one kind of radical selected from the group consisting of at least radical O ^* , radical N ^* and radical NH ^{* in the} atmosphere. 26. A method of manufacturing a semiconductor memory device according to claim 25. 26. The method of manufacturing a semiconductor memory device according to claim 25, wherein the source gas further contains a rare gas. 28. The method of manufacturing a semiconductor memory device according to claim 27, wherein the rare gas contains at least one molecule selected from the group consisting of Kr and Ar. The raw material gas, a method of manufacturing a semiconductor memory device according to claim 25, characterized by further containing H _2. 26. The method of manufacturing a semiconductor memory device according to claim 25, wherein, in the step of forming the covering insulating film, the ion irradiation energy of the plasma is set to 7 eV or less. 26. The method of manufacturing a semiconductor memory device according to claim 25, wherein in the step of forming the covering insulating film, the potential energy of the plasma is set to 10 eV or less. 26. In the step of forming the covering insulating film, the plasma is generated by exciting the source gas using a microwave radiated from a planar antenna in which a plurality of slits are formed. A manufacturing method of the semiconductor memory device according to the above. 33. The method of manufacturing a semiconductor memory device according to claim 32, wherein a radial line slot antenna is used as the planar antenna. 21. The method of manufacturing a semiconductor memory device according to claim 20, wherein the step of forming the covering insulating film is performed within a temperature range of 650 [deg.] C. or less.

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