JPS6338277A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the resistance of a buried layer and to increase its forbidden band width thereby to suppress a reactive current flowing to the buried layer by adding a crystal including aluminum, halogenated aluminum or both to a material crystal at the time of growing the buried layer by a mass transporting method. CONSTITUTION:A stripe is so etched with Br methanol (-2%) at both sides as to arrive at an n-type InP layer 2. A substrate, an Al0.48In0.52As as a crystal including aluminum, InP as a material crystal and AlI3 as halogenated aluminum are simultaneously sealed in vacuum in a quartz ampule, charged at the positions in a furnace of a temperature profile, and heated for 30-60 min. An active layer periphery can be buried in a crystal (Al1-xInxAs1-yPy) layer 7 including aluminum by a mass transporting method. An etching mask 6 is removed, a semiconductor layer structure is covered on its surface with an SiO2 layer as an insulating layer, or with an Si3N4 layer 8, a light emitting region is opened to form a Ti-Pt-Au layer 9 as a P-type side electrode and an AuGe-Au layer 10 as an N-type side electrode on the rear surface of the substrate.

Description

[Detailed Description of the Invention] [Summary] In manufacturing a compound IEI device having an embedded structure,
During the growth of the buried layer by the mass transfer method, by adding crystals containing aluminum (81), aluminum halides such as aluminum iodide J.(^II+), or both to the raw material crystals, By increasing the resistance of the layer and increasing its forbidden band width, the reactive current flowing through the forced layer is suppressed. - [Industrial Application Field] The present invention relates to a method for growing a buried layer in a compound semiconductor device.

Currently, m-v group compound semiconductors are used in operating areas such as light emitting,
Semiconductor devices used as light-receiving regions are often used in optical communication systems, and indium phosphorus/indium gallium (pore element phosphorus (InP/InGaAsP) system is used for IPM Obikawa, and gallium arsenide/aluminum gallium arsenide (G+iAs) system for 0.8 μrn band. /8IG to A s)
A system compound semiconductor is used.

[Conventional technology]

Conventionally, in many cases, a pn junction was formed in the buried layer of such a semiconductor device, but a reactive current flows through the junction capacitance, which hinders the speeding up of the semiconductor device.

Therefore, in order to reduce reactive current and parasitic capacitance, it has become common practice to form the buried layer with a high resistance layer.

Various methods have been studied to grow the quotient resistance indentation layer using conventional growth methods such as liquid phase epitaxy (LPE) to grow thickly until the substrate becomes flat without reducing the resistance value. Attempts have been made to use the mass transport method by processing the embedding part into a narrow gap so that embedding can be done with a small amount of growth.

The mass transport method is a growth mechanism in which the raw material crystal is directly transported onto the growth target using its own f-pressure and deposited on it without relying on rear gas, etc., so the growth rate is low.
Therefore, it is required to use a material with high vapor pressure.

In particular, mass transfer is one of the methods for forming buried layers in InP/InGaAsP devices1), 2).

1) Z. L. Liau et+]1. , 8 pages
Go to p1 Pt+y! ;, fete. .

4-0.5fi8 ("82).

2) T. R. Chen eL al. , 8pp
1. ．． Pby:;. LeLt. .

41, 1115 ('82).

Currently, this method uses both an open tube method and a closed tube method, but in each case, InP crystals are embedded.

Next, a conventional example using the mass 1 transport method will be explained using a semiconductor light emitting device as an example.

FIGS. 3 (1.1 to 4) are cross-sectional views of a buried semiconductor laser explaining a conventional method step by step.

In Fig. 3 (1), LPE method, vapor phase epitaxial growth (VPE) method, metal organic chemical vapor deposition (MOCν0
) method, etc., on an n-1nP substrate 1, an n-InP layer 2 as a nopanophore layer and a cladding layer, an undoped InGaAsP layer 3 as an active layer, and a CLI as a cladding layer.
An nP layer 4 and a p'-InGaAsP layer 5 are stubbornly grown as a contact layer, and a Dl+ structure is formed as a compound semiconductor layer structure that becomes an operating region.
form a structure).

Next, SiO2 is etched on the surface of the substrate as a notching mask 6.
A □ layer or a SiJs layer is grown, and a stripe of a predetermined width is left on the light emitting region, and openings of a predetermined width are opened on both sides using normal lamination lithography.

In FIG. 3(2), both sides of the stripe are etched with bromine (Br) methanol.

Next, the active layer 3 is side-etched by selective etching to make the remaining width of the active layer a predetermined value.

Next, place the processed substrate in a quartz ampoule,
- InP is simultaneously vacuum-sealed as a raw material crystal, placed in a furnace with the temperature profile shown in FIG. 4, and heated.

In FIG. 3(3), by the above growth, the area around the active layer can be filled with an InP layer 7'.

Note that the InP layer 7' is also embedded in the undercut portion of the contact layer 5.

In FIG. 3(4), the etching mask 6 is removed,
On the surface of the semiconductor layer structure, a Si02 layer as an insulating layer,
Alternatively, a SiJ4 layer 8 is deposited and an opening is formed over the light emitting region.
A Ti/PL/Au layer 9 is formed as a side electrode, and an AuGe/llu layer 10 is formed as an n-side electrode on the back surface of the substrate.

FIGS. 4(1) and 4(2) are a sectional view and a temperature distribution diagram of a mass transport growth apparatus illustrating a conventional example.

In FIG. 4 (1), the quartz ampoule 41 is
The substrate 42 that has gone through the steps up to 2) and the raw material crystal In
A quartz container 44 containing P 43 is vacuum sealed at the same time.

FIG. 4(2) is a diagram showing the temperature profile in the longitudinal direction of the furnace, with the substrate 42 placed in the temperature gradient area and the container 44 placed in the high temperature flat area.

[Problem that the invention seeks to solve]

In the conventional example, undoped Ink' is used for the buried layer in the mass transport I method, and the conductivity type, concentration, etc. are hardly controlled. That is, the resistance value of the grown buried layer decreases due to variations due to the loft of InP of the raw material crystal, diffusion of p-type impurities from the operating region, etc., and its reproducibility is poor.

Therefore, the reactive current flowing through the buried layer may become large (for example, a threshold current of 15 mA may become 40 mA).
mA, and deterioration of luminous efficiency may be observed.

[Means for solving problems]

The solution to the above problem is to form a compound semiconductor layer structure that becomes an operating region, and when growing a compound semiconductor as a buried layer in contact with the side surface of the layer structure, the raw material crystal is vaporized and the raw material crystal itself is vaporized. According to the present invention, a crystal containing aluminum as a constituent atom, an aluminum halide, or both are added to the raw material crystal using a mass transport method in which the raw material crystal is directly transported onto a growth target by pressure and grown on it. This is achieved by a method for manufacturing a semiconductor device.

The present invention is particularly effective when the compound semiconductor layer structure includes an indium phosphorous layer and an indium gallium arsenide phosphorus layer, and the raw material crystal is composed of indium phosphorous.

[Effect]

The present invention has the following advantages: (1) It is possible to embed the crystal with a larger forbidden band width than InP containing oxide, and the built-in voltage of the heterojunction formed by the embedding layer and the cladding layer can be increased.

■ In the buried layer, residual oxygen (O2) in the ampoule is easily oxidized and is taken into the crystal together with I and NAI.
It becomes a crystal with high resistance. Generally, a crystal with higher resistance can be obtained by adding an impurity such as oxygen that creates a deep energy range.

■ Although the detailed mechanism of mass transport is unknown,
When a halide (iodide, bromide, etc.) is added to the raw material crystal, an intermediate reaction appears to occur in an atmosphere containing the barber element, and it is possible to use a method beyond the mass transport method to transfer the halides (iodide, bromide, etc.) through the ζ buried layer. This is to reduce the reactive current that flows.

〔Example〕

FIGS. 1(1) to 1(4) are cross-sectional views of a buried semiconductor laser explaining the method of the present invention step by step.

Figure 1 (1) Niote, LPE method, VPE method, MOCV
By D method or the like, an n-rnP layer 2 is formed as a buffer layer and a lithographic layer on an n-1nP substrate 1, an undoped InGaAsP layer 3 is formed as an active layer, and p-InP is formed as a cladding layer.
A layer 4 and a p''-InGaAsP layer 5 as a contact layer are sequentially grown to form a 1111 structure as a compound semiconductor layer structure operating in the jJj region.

The conditions for forming each layer are shown below.

Layer thickness ・Dopant concentration (μm
) (cm-”)p” InGaA
sP layer 0.3 Zn > 1xlQ19
p-1nPJl 1.5-2 Cd(0,
5~3)xlO”InGaAsPN O,15~
0.2 7y Tope ~ IoI Man n-1n
P layer ~2 Sn 2X10"
n4nP substrate Sn (1~2) x
The mixed crystal ratio of InGaAsP N3 in the lQIll active layer is:
It is lattice matched with InP and the laser oscillation wavelength λ is I,3
, or jλ so that it becomes 1.55 μm.

The Inl' of the contact layer; the mixed crystal ratio of the aAsP layer 5 is usually the same as that of the active layer, but may be different. I n G
aA sP is used because it has a smaller forbidden band width than InP and is easier to make contact with.

Next, an etching mask [j is SiO
□ layer, or S+ 3N4 layer is grown and opened 10-50 μm wide on both sides using normal gluing lithography leaving a ~5 μm wide stripe over the light emitting region.

In FIG. 1(2), both sides of the stripe are etched with Brtutanol (~2%) so as to reach the n-InP layer 2.

At the same time, 2 KOII: I K3Fe (CN)
b: The active layer 3 is side-etched with G IIJ' to make the remaining width of the active layer 1 to 2 μm.

This etchant is a quaternary crystal of InGaAsP and InP.
The selection ratio of InP is large, and InP acts as an etching stopper.

Next, the substrate was placed in a quartz ampoule, and 8lo, ulno, 528S as a crystal containing AI/[nP as a raw material crystal]
/Hylide 1 and Al13 are vacuum sealed at the same time, placed in the respective positions of the furnace having the temperature profile shown in FIG. 2, and heated for 30 to 60 minutes.

The amount of crystals to be vacuum-sealed should be larger than the amount required to maintain equilibrium vapor pressure when the ampoule is held at a high temperature.

In FIG. 1(3), the periphery of the active layer can be filled with a crystal (AI+-JnJsl-yl'y) layer 7 containing ^l by the mass transfer growth described above.

Note that the AIInAsP layer 7 is also embedded in the undercut portion of the contact layer 5.

Further, during embedding, even if there is some lattice mismatch (≦1O-1) with respect to InP, AIInAsP can grow due to the entrainment effect of growth.

In FIG. 1(4), the etching mask 6 is removed,
On the surface of the semiconductor layer structure, a 5iOz layer as an insulating layer,
Alternatively, a 5iJn layer 8 is deposited, a Ti/I't/Au layer 9 is formed on the light emitting region as an n-side electrode, and a ^G e /^11 layer To is formed on the back surface of the substrate as an n-side electrode. do.

FIG. 2 (11, (2)) is a cross-sectional view and a temperature distribution diagram of a growth apparatus for mass transfer 1 for explaining the present invention.

Figure 2 (in 11, in the quartz ampoule 21,
The substrate 22 that has gone through the steps up to Figure (2) and ■ AlI
The quartz container 25 containing nAs/■NP 23 and the quartz container 26 containing 8llff2/I are vacuum sealed at the same time.

FIG. 2(2) is a diagram showing the temperature profile in the longitudinal direction of the furnace, in which the substrate 22 is placed in a temperature gradient region of 580 to 690° C., and the container 25 is placed in a high temperature flat region of 690° C.

Next, the forbidden band width Eg of each layer grown in the example will be compared.

Crystal E9 (eν) ■rnP 1.33 (cladding layer) ■^ITnASP 1.33 (InP) ~1.5
0 (8lo, nalno, 5zAs) (buried layer)
(λ-0,83μm)■InGaAsP
1.33 (InP) ~0.75 (Ino, s+G
ao, aq8) (active layer) (λ=
1.65 μm) As can be seen from the table above, the A of the buried layer
1!9 is large for IInAsP, so ^l1nAsP
The built-in voltage of the heterojunction formed with /InP layer is
It is larger than that of a pn junction formed by P, #nP layers.

Although the present invention has been described above using a closed tube method, similar results can be obtained using an open tube method.

In addition, aluminum iodide was used as a growth accelerator, but
Aluminum bromide may be used instead.

〔Effect of the invention〕

As described above in detail, according to the present invention, it is possible to suppress the reactive current flowing through the buried layer.

Therefore, it is possible to prevent the threshold current and luminous efficiency of the laser from deteriorating.

[Brief explanation of the drawing]

FIGS. 1 (1) to (4) are cross-sectional views of a buried semiconductor laser explaining the method of the present invention step by step; FIGS. 2 (1) and (2) are mass transport growth apparatuses explaining the present invention. Cross-sectional view and temperature distribution diagram, Figure 3+11~
(4) is a cross-sectional view of a buried semiconductor laser that explains the conventional method step by step; Figures 4 (1) and (2) are cross-sectional views of mass 1 to transport growth equipment that explain the conventional method. and temperature distribution map. In the figure, ① is an n-1nP substrate, 2 is a buffer layer and cladding layer, which is an n-In+' layer, 3 is an active layer, which is an 1'-amplified InGaAsr' layer, 4 is a cladding layer, which is a p-1n+' layer, 5 is a contact layer, which is a p'-1nGaAsP layer, 6 is an etching mask, which is a 5i02 layer or Si:+114 layer, and 7 is an indentation layer, which is a crystalline (AIInAsP) layer containing AI.
8 is an insulating layer, SiO□ layer, or Si, N, layer, 9 is p
The side electrode is a Ti/Pt 780 layer, and the n-side electrode is an AuGe/Au layer. 42, Substrate-distance

Claims (2)

[Claims] (1) When forming a compound semiconductor layer structure to serve as an operating region and growing a compound semiconductor as a buried layer in contact with the side surface of the layer structure, the raw material crystal is directly deposited onto the growing body using the vapor pressure of the raw material crystal itself. A method for manufacturing a semiconductor device, which uses a mass transport method of transporting and growing on the raw material crystal, and the method comprises adding a crystal containing aluminum as a constituent atom, an aluminum halide, or both to a raw material crystal. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor layer structure includes an indium phosphorous layer and an indium gallium arsenide phosphorous layer, and the raw material crystal is composed of indium phosphorus. .