JPS63279622A - Maximum correction limiting type echo canceller - Google Patents

Abstract

PURPOSE:To increase the stability by adding a signal to an output of a delay storage circuit by an adder circuit after a maximum/minimum value of a coefficient calculated by a coefficient correction counter circuit with respect to the correction value so as to reduce the converging speed. CONSTITUTION:A maximum/minimum value limit circuit 9 limits the maximum/ minimum value calculated by a coefficient correction calculation circuit 8. The adder circuit 10 adds the output of the maximum/minimum limit circuit 9 and the impulse response of the 2nd delay storage circuit 7 and outputs the added output to the 2nd delay storage circuit 7. Thus, the maximum correction of the impulse response is limited, and the converging speed is decreased thereby increasing the stability. Since a small correction is applied while the maximum value and the minimum value are limited, the adaptive operation of the echo canceller is kept constant.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an echo canceller in two-wire transmission or communication using a speaker and a microphone, and in particular to an echo canceller that can reduce disturbances in estimated impulse responses due to double talk, etc. This invention relates to a limited correction type echo canceller.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional echo canceller. In the figure, 1a and 1b are transmission input signals Fi
2a and 2b are the receiving input signal X,
5 is a multiplication/addition circuit, and 6 is a multiplication/addition circuit 5 and a coefficient correction value calculation circuit that delays the receiver's power input * 8 is a first delay memory circuit that outputs the impulse response hj to the addition circuit 4 and the multiplication/addition circuit 5; 8 is the transmission output signal 1 which is a residual signal and the first delay memory; This is a coefficient correction value calculation circuit that calculates a correction value of the coefficient by inputting the output signal x1-j of the circuit 6. Note that the multiplication/addition circuit 5, the first delay storage circuit 6, and the second delay storage circuit 7 constitute a filter.

Next, the operation of the echo canceller with the above configuration will be explained. First, a filter section consisting of a multiplier-adder circuit 5, a first delay memory circuit 6, and a second delay memory circuit 7 that performs convolution products is used to generate a pseudo-echo signal.On the other hand, the subtraction circuit 3 is △ Pseudo echo yi obtained from signal yt using equation (1) above
is subtracted, and a transmission output signal l, which is a residual signal, is output from the transmission output terminal 1b.

△ ・i = y i −y 1 (
2) Then, the impulse response hj is corrected using the transmission output signal @l of the subtraction circuit 3 by the coefficient correction value calculation circuit 8 and the addition circuit 3 which actually performs the correction according to the following equation (3).

However, 1=O, l, 2, 3... ・n-1
Here, α is a correction coefficient and is used in the range of 0<α<2. If this correction coefficient α is close to 1, the convergence speed will be faster, but it should be noted that the faster the convergence speed, the greater the disturbance will be if the correction is made incorrectly. Therefore, when it is desired to suppress the disturbance in the impulse response hj, the correction coefficient α is reduced to create a more stable echo canceller configuration.[Problems to be Solved by the Invention] The canceller has a configuration in which the correction coefficient α is small, and if it approaches zero, the correction amount becomes zero because the calculation accuracy and the accuracy of the storage circuit are finite. For this reason, there is a drawback that when the amount of correction becomes zero, the adaptive operation that has been following changes in the impulse response stops and the erasing ability deteriorates.

[Means for solving problems]

The maximum modification amount limiting type echo canceller of the present invention limits the maximum and minimum values of the coefficient modification values calculated by the coefficient modification value counting circuit, and then uses the addition circuit to calculate the second.
This is added to the output of the four extension memory circuits.

[Effect]

By limiting the maximum amount of impulse response modification, the present invention can reduce convergence speed and increase stability.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a maximum correction amount limited type echo canceler according to the present invention.

In the figure, 9 is a maximum/minimum value limiting circuit that limits the maximum and minimum values of the correction values calculated by the coefficient correction value calculation circuit 8 as shown in equation (4) below, and 10 is this maximum/minimum value limit. Output of circuit 9 and second delay memory circuit jl! +7 impulse responses h'' and outputs the addition output to the second delay storage circuit 7.

Next, the operation of the echo canceller with the above configuration will be explained. First, the multiplication/addition port that performs the convolution product lol! 15
, the pseudo echo Δ-yt can be obtained by the following equation (1) using the filter section consisting of the first delay storage circuit 6 and the second delay storage circuit 7.

On the other hand, the subtraction circuit 3 subtracts the pseudo echo Δ yl determined by the above equation α) from the transmission input signal y1 as shown in equation (2), and sends the transmission output signal ei, which is a residual signal, to the transmission output terminal 1b. Output from.

Δ・1=yl −yi (2) On the other hand, the coefficient correction value calculation circuit 8 calculates the transmission output signal width, which is a residual signal, and the first delay storage time w! Based on the input of the output signal X1-J of I6, the corrected value of the coefficient is calculated according to the following equation (5) and outputted to the maximum/minimum value limiting circuit 9.

However, l=Q, l, 2ases, H-1, and the maximum/minimum value limiting circuit 9 calculates the maximum and minimum values of the correction values calculated by the coefficient correction value calculation circuit 8 using the following equation (5). Restrict.

Then, the adder circuit 10 combines the output signal of the maximum/minimum value limiting circuit 9 with the second delay memory circuit J! The impulse response hJ shown in the following equation (6) can be corrected by adding the output signal of i37.

hJ(1+1)±hj(1) ΔhJ(1)
(6) In this way, the maximum correction amount of the impulse response hj is limited, the convergence speed is reduced, and stability can be increased. Moreover, although the maximum and minimum values are limited, it is possible to continue the adaptive operation of the echo canceller by adding a small amount of correction. [Effects of the Invention] As explained in detail above, the present invention The maximum correction amount limited type echo canceller has the effect of reducing disturbances in the impulse response of the echo canceller without increasing the period during which its adaptive operation is stopped, that is, without the correction amount becoming almost zero. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a maximum correction amount limited type echo canceler according to the present invention, and FIG. 2 is a block diagram showing a conventional echo canceller. 1a and 1b
・・Transmission input terminal and transmission output terminal, 2a and 2b ・・Reception input terminal and reception output terminal, 3・
...subtraction circuit, 5...0 multiplication/addition circuit, 6...first delay memory circuit, 7...second delay memory circuit, 8...
...Coefficient correction value calculation circuit, 9.. Maximum/minimum value restriction circuit, 10. Fist... Addition circuit.

Claims (1)

[Claims] A first delay memory circuit that delays and stores a received input signal, a second delay memory circuit that stores an impulse response coefficient, and a convolution product obtained from the output of the first delay memory circuit and the output of the second delay memory circuit. a multiplication/addition circuit; a subtraction circuit that subtracts the output of the multiplication/addition circuit from the transmission input to output a transmission output signal; and a coefficient correction for obtaining a coefficient correction value from the output of the first delay storage circuit and the output of the subtraction circuit. a value calculation circuit, a maximum/minimum value limiting circuit for limiting the maximum value/minimum value to the output of the coefficient correction value calculating circuit, and an output of the maximum/minimum value limiting circuit to the output of the second delay storage circuit. In addition,
A maximum correction amount limited type echo canceller comprising: an addition circuit that inputs input to a second delay storage circuit.