JPS6326753A - Memory bus control method - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory bus control method for electronic computers, and is particularly suitable for systems that have a restriction on the number of bus signal lines and that use dynamic random access memory. This paper relates to a memory bus control method.

[Conventional technology]

Electronic computers are generally used in the second category, except for some special purpose computers.
Take the configuration shown in the figure. That is, the main memory 102 is connected to the main processing unit 101 via the memory bus 111 .

On the other hand, the input/output control mechanism 103 via the input/output bus 112
is connected to the main processing unit 101 and the input/output control mechanism 10.
3, the input/output device 104 operates. Depending on the system configuration of some computers, the memory bus 111 and the input/output bus 112 may be used together.

In such a computer system, the main memory 102 and the input/output control mechanism 103 are modularized in order to make the main memory capacity variable depending on the purpose of the system or to change the configuration of input/output equipment depending on the purpose of the system. , the module is configured to be removable from the memory bus 111 or the input/output bus 112. For example, in a system that requires a small storage capacity but at a low price, only one main memory module is installed, whereas in a system that requires a large storage capacity, the maximum number of main memory modules that can be installed is installed. Memory is implemented.

In order to miniaturize such a system, it is necessary to reduce the size of the module. To achieve this, the circuit configuration within each module must be minimized. On the other hand, the bus signal lines that connect the modules must be arranged in a two-dimensional configuration (
For example, if each module corresponds to one printed wiring board, one side of the module is occupied. Therefore, when the module is miniaturized, the number of bus signal lines is subject to restrictions. Similar restrictions apply when configuring a bus using empty pins in a system in which the number of input/output buses and the dimensions of modules are fixed.

When there are such constraints, the number of signal lines necessary for performance may not be sufficient, and the conventional method to deal with this is to use the address signal lines of Intel's microprocessors 8085 and 8086, etc. There is one that has multiplexed data signal lines. This conventional method is described in Chapter 2, pages 10 to 25 of the product catalog "Microprocessor and Peripheral Handbook (1983)" published by Intel Corporation in the United States.
sorand Peripheral Handboo
(1983) Pages 2-10 to 2-25), an outline of the address/data multiplexing of the processor 8085 will be explained below.

Processor 8085 is the company's microprocessor 8080
The number of signal lines has been increased according to the enhancement of 1 function, but it is the same package as 8080 (4
Since a 0-pin dual inline package was used, the address/data signal lines were multiplexed. FIG. 3 schematically shows the data transfer signals and peripheral circuits of the 8o85. 8085 microprocessor 2
01 has eight address buses 211.8 address/data multiplexed buses 212. Access to the memory and peripheral circuits is performed through signal lines for an address latch enable signal 213, a read access timing signal 214, a write access timing signal 215, and an access ready signal 216.

In devices such as static memory, it is necessary to hold the corresponding address while accessing it, but on the other hand, 8 bits out of the 16 bits of the address are output from the address/data multiplexed bus 212, and this address is not used during data transfer. Since address output cannot be performed, it is necessary to provide an address latch circuit 202 externally to hold the address.

4 and 5 show 8 including the address latch circuit 202.
4 shows the access timing of the 085 microprocessor 201, and FIG. 4 shows the case of reading, and FIG. 5 shows the case of writing. In the Kowara diagram, when an address is output from the address/data multiplexed bus 212 at the beginning of an access cycle, the address latch enable signal 213 turns on almost simultaneously with this address output, and this signal 213 becomes an address output. Return to off state inside. As a result, the address from the bus 212 is held in the address latch circuit 202, the held address 217 and the address 2 held in the microprocessor 201 itself.
11 constitutes an address bus 221. After the address latch enable signal 213 turns off, the address/data multiplexed bus 2
The address output from 12 is completed, and this bus 212 becomes a data bus 222, and the access timing signal 214
．． (Reading, Figure 4) 215 (Writing, Figure 5)
Data transfer is performed according to the timing.

When address/data multiplexing is performed in this way,
By adding an address latch enable signal and providing an external latch circuit, the number of signal lines can be reduced. The 8085 is an 8-bit microprocessor, but the 8086 uses 16-bit address/data multiplexing to house a 16-bit microprocessor in a 40-pin dual in-line package.

As described above, by address/data multiplexing, it is possible to increase the number of data signal lines without increasing the number of signal lines. However, if similar address/data multiplexing were to be performed on the memory bus of a system configured as shown in FIG. 2, each memory module would have to be provided with an address latch.

-The memory element for the sumo wrestler memory 102 is an inexpensive and large-capacity dynamic random access memory (DRAM).
is commonly used.

When accessing a DRAM, it is necessary to divide the address into a row address and a column address and provide a row address strobe signal and a column address strobe signal. D.R.
The AM access timing is detailed in the product catalog "Hitachi IC Memory Data Book" (Catalog No. 746U) published by Hitachi, so 80
If the signal line 85 is used as it is for the memory bus of a computer system as shown in Figure 2, and if a DRAM is used as the storage element of the main memory, the row address strobe signal and the read access timing signal or the write access timing signal are used. It is necessary to provide a circuit for generating a column address strobe signal for each main memory module.

Furthermore, DRAM has the property that once written content evaporates over time. Therefore, it is necessary to rewrite the contents periodically. This rewriting is called refresh, and a typical refresh method is refresh using a row address strobe signal. FIG. 6 shows the timing of refresh using the row address strobe signal (RAS). That is, when a row address is added to the address input of the DRAM and the row address strobe signal is turned on, the contents of the memory cells in the row specified by the row address are rewritten. In this way, in order to perform refresh, set the row address to D.
A refresh counter for sequentially specifying the number of rows of RAM, a refresh timer and a row address strobe signal generation circuit for periodic refresh are required, but the 8085 does not take DRAM refresh into consideration. , a circuit for performing the above-mentioned refreshing is required on each main memory module side.

[Problem to be solved by the invention 3 As stated above, in the prior art, DRAM is used,
No consideration has been given to the case where it is used as a memory bus in a computer equipped with a modularized main memory, and each main memory module must be provided with a DRAM access timing signal generation circuit and a refresh control circuit. There was a problem that the amount of wear increases.

Further, in the conventional technique, since the address is determined and the access timing signal is turned on after the address is latched, there is a problem that the start of access is delayed.

An object of the present invention is to provide an address/data multiplexed bus and a DR
To provide a memory bus control method that can reduce the hardware of a main memory module and the entire computer system in a system using AM, and can also access DRAM at high speed.

[Means for solving problems]

The above purpose is to provide a first timing signal that is an address latch enable signal and a row address strobe signal, a second timing signal that is a data transfer timing signal and a column address strobe signal, and a data transfer direction of an access cycle. and a signal indicating whether it is read or write.

This is achieved by providing a circuit for outputting a DRAM refresh address and a refresh start timing signal in the memory bus control section of the main processing unit.

[Effect]

When accessing the main memory, the first timing signal is turned on while the address is being output from the main processing unit onto the address/data multiplexed bus, and thereby the address register provided in the main memory module is The address on the bus is latched and the row address stroke signal is turned on with the row address added to the address input of the DRAM. Next, the second timing signal is turned on, the address/data multiplex bus is switched to the data bus, and the column address strobe signal is turned on with the column address added to the address input of the DRAM. This operation activates the DRAM data transfer pin, allowing data to be transferred.
Data transfer can be performed without providing an access timing circuit in each main memory module. In addition, data access can be performed immediately using the second timing signal.

Delays in starting access can be reduced.

Also, when refreshing the DRAM, when a refresh address is output to the address/data multiplexed bus and the first signal is turned on, the row address strobe signal is output with the refresh address added to the address input of the DRAM. Because it will be turned on,
A refresh cycle can be executed using a row address strobe signal, and there is no need to provide a circuit for refresh control in each main memory module.

〔Example〕

The present invention will be explained below with reference to Examples. FIG. 1 shows an embodiment of the method of the present invention, in which the main processing bag ff1lo1
consists of a basic processing unit 11 that processes data according to instructions and other bus control units. The bus control unit includes tristate buffers 197, 198, 199 .
Refresh address counter 195. A tri-state buffer 196 that outputs the contents of the refresh address counter 195 to the memory bus 111, and a control circuit 131 that controls the tri-state buffer and counter 7 and controls the timing on the memory bus 111.
It consists of

Memory bus 111 is address/data multiplexed bus 1.
2. Memory address strobe signal, which is an address latch enable signal and a DRAM row address strobe signal. Data transfer timing signal for DRAM
Memory data strobe signal 3, which is a column address strobe signal for the main memory; Memory write signal 4, which is on when the access to the main memory is a write access; and off when it is a read access. It consists of a memory acknowledge signal 5 which is an access response signal from the main memory.

The main memory 102 uses a dynamic operation type random access memory 151 as a storage element, and peripheral circuits are classified into three types: address system, data system, and control system.

As an address system, the row address buffer 174. Column address register 153 for launching column addresses by memory address strobe signal 2. A multiplexer 152 . which outputs a row address when the memory address strobe signal 2 is off, and a column address after a slight delay after the memory address strobe signal 2 is turned on, to the DRAMI 51 . Address setting switch 156 assigned to the main memory module. Address on memory bus 111 and switch 1
a comparator 155 for comparing the contents of 56, and a register 15 for holding the match output of the comparator 155;
There are 4. As a data system, write data buffer 1
73, there is a tri-state buffer 171 for read data.

FIG. 7 shows an example of the internal configuration of the control circuit 131, in which a shift register 41 for generating read/write timing. Shift register 42 for generating refresh timing. Refresh timer 51゜Refresh request register 5
It consists of 2 and several gates.

In the embodiment described above, the operation when the main processing device 101 performs read access to the main memory 102 will be described. FIG. 8 is a timing chart of the operation at this time. First, when the read/write discrimination signal 144 of the basic processing unit 11 in FIG. 1 indicates read, the access request signal 1 is
43 is turned on. In response to this, the control timing circuit 131 in FIG. 7 turns off the memory write signal 4.

Address buffer control signal 187 is turned on. This causes address tri-state buffer 197 to output the contents of internal address bus 141 to address/data multiplexing path 1. When the address is determined on the address/data multiplexed bus 1 (FIG. 8, tn) - the bit corresponding to the row address of the DRAMI 51 out of all addresses is input to the multiplexer 152 through the address buffer 174. At this time, the memory address strobe signal 2 is in the off state (note that 2 is shown as an inverted value in FIG. 8; the same applies to the others), so the row address from the buffer 174 is output from the multiplexer 152. In this state, when the output QA of the shift register 41 in FIG. 7 is turned on and the memory address strobe signal 2 is turned on (FIG. 8, z).

When the row address strobe signal RAS of the DRAMI 51 is turned on, the column address register 153 and the register 154 that holds information as to whether the address exists in the main memory module are put into a hold state, and the delay gate 158° is turned on. 159, the output of the address multiplexer 152 changes from the row address to the column address from the register 153 (t8 in Figure 8).Next, the output QB of the shift register 41 in Figure 7 is turned on, and the memory data strobe signal 3 is turned on. At the same time, the address buffer control signal 187 is turned off and the data bus span control signal 189 is turned on (t4 in FIG. 8).
), then the address buffer 197 becomes a high impedance state, the data bus buffer 199 becomes a low impedance state, and the contents of the address/data multiplexed bus 1 can be output onto the internal data bus 142. - When the memory data strobe signal 3 turns on,
The output of the AND gate 161 in the main memory 102 is turned on when an access address exists in the main memory module, and the output of the AND gate 161 in the main memory 102 is turned on when the access address exists in the main memory module.
turns on (tδ in FIG. 8), and as the output of gate 161 turns on, the output of AND gate 163 also turns on, and data buffer 171. Access response signal buffer 172 enters a low impedance state. Also and gate 16
The output of 1 is input to the shift register 157, and the DRAM
151 is delayed by the time necessary to confirm the data output.

When the data output of the DRAM 151 is determined (t8 in Figure 8)
), the data is output to the address/data multiplexing path 1 via the data bus buffer 171, which is sent to the internal data bus 142 via the data bus buffer 199 of the main processing unit 101, and the read data is finalized 6- When the shift register 157 in the sumo wrestler memory 102 has elapsed a predetermined time, its output is turned on, and this is output as the memory acknowledge signal 5 via the buffer gate 172 (FIG. 8, t, 7).

Then, the timing circuit 131 turns on the access response signal 145 to the basic processing unit 11, and thereby the basic processing group! ! 11 takes in the data on the internal data bus 142 and turns off the access request signal 143. When signal 143 turns off, memory address strobe signal 2. Both memory data strobe signals 3 are in the off state (t8 in FIG. 8), and the data bus buffer 199 is in a high impedance state. Also, the DR in the main memory 102
The row address strobe and column address strobe of the AMI 51 are both turned off (FIG. 8te), the memory acknowledge signal 5 is turned off, and the tristate buffers 171 and 172 are placed in a high impedance state. With this, data reading from the main memory 102 is completed.

FIG. 9 is an operation time chart during write access to the main memory 102 from the main processing bag Cl0L. In this case, the read/write discrimination signal 144 of the basic processing unit 11
The access request signal 143 is turned on in a state in which the access request signal 143 indicates write. In response to this, the control timing circuit 131 turns on the memory write signal 4, turns on the address buffer control signal 187, and turns on the address buffer 197.
outputs the address to the address/data multiplexed bus 1 (t1 in Figure 9), after which the memory data strobe signal 3
The process until the switch turns on (t4 in FIG. 9) is the same as read access. When writing to the DRAM 151, the data input must be confirmed at the time the write enable signal WE turns on, and the data input must be confirmed at the time the memory data strobe signal 3 turns on (t4). Therefore, the output of the AND gate 161 is delayed by the shift register 157. When the output QA of the shift register 157 turns on, the output of the AND gate 162, that is, the write enable signal WE
turns on (txo in Figure 9), and DRAM 1
Data is written to 51, and thereafter all accesses for write data are completed in the same procedure as for read access.

FIG. 10 is an operation time chart during refresh. At this time, the refresh timer 51 (FIG. 7) inside the timing circuit v&131 times out, and when refresh is required, the register 52 is set in the timing circuit 131 and the refresh address buffer control signal 186 is set to the output QA of the shift register 42. is output in the on state, and the address/
The contents of the refresh address counter 195 are output onto the data multiplexing bus 1 (t1 in FIG. 10).

Subsequently, the memory address strobe signal 2 is output in the on state from the output QB of the shift register 42 (tz in FIG. 10), and when the row address strobe signal RAS of the DRAMI 51 is turned on, the memory address strobe signal 2 is output as shown in the contents of the refresh address counter. The memory cells inside the DRAM 1 51 are rewritten. When the time required for rewriting has elapsed, the output QC of the shift register 42 is turned on to reset the register 52, and as a result, the output of the shift register 42 itself is turned off. As a result, the memory address strobe signal 2 and the refresh address buffer control signal 186 are turned off (see tzt in FIG. 10).
), the counter update signal 185 is output at the same time, and the contents of the refresh address counter 195 are updated.

〔Effect of the invention〕

As is clear from the above embodiments, according to the present invention, the timing generation circuit for dynamic operation type random access memory access and the refresh control circuit can be integrated into the main processing unit, so that processing when multiple main memory modules ζ are implemented is possible. This has the effect of reducing the total amount of hardware in the device system. Furthermore, according to the present invention, since the row address strobe is applied at the address latch timing on the address/data multiplexed bus, the bit width of the address latch can be halved, and the start of access can be made faster. This has the effect of increasing speed and speed of access.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a general processing device system, FIG. 3 is a diagram showing the bus configuration of a conventional 8085 microprocessor, and FIG. 4 and 5 are timing charts for reading and writing of the microprocessor in FIG. 3, FIG. 6 is an operation timing chart for the dynamic random access memory, and FIG. 7 is an example of the timing circuit. 8 to 10 are timing charts of read operation, write operation, and refresh operation in the embodiment of FIG. 1. 1...Address/data multiplexed bus, 2...Memory address strobe signal, 3...Memory data strobe signal, 4...Memory read signal, 5...
Memory-7 knowledge signal, 101... Main processing unit, 102... Main memory module, 131... Memory bus control timing circuit, 11... Basic processing unit,
151...Dynamic operation type random access memory, 51...Refresh timer, 195...Refresh counter.

Claims (1)

[Scope of Claims] 1. In a memory bus control method when a main processing device accesses a main memory module connected to the device via a memory bus and whose storage element is a dynamic RAM, the main processing The device is provided with a memory control means, and when an access request and an access address are output from the main processing unit, the memory control means outputs a first timing signal to control the access on the internal address bus within the main processing unit. The address is output onto the memory bus, and when the main memory module receives the first timing signal, it inputs the row address within the access address output onto the memory bus to the address input of the dynamic RAM within its own module. and turns on the row address strobe signal, further sets the column address in the access address to the column address register, and then the memory control means outputs a second timing signal to control the internal memory in the main memory. The data bus is connected to the memory bus instead of the internal address bus, and when the main memory module receives the second timing signal, the column address strobe signal is also turned on following the row address strobe signal of the dynamic RAM in the own module. and applying the column address set in the column address register to the address input of the dynamic RAM, thereby performing data transfer between the main processing unit and the main memory module. 2. The memory control means is provided with a refresh timer and a refresh counter, and when the refresh timer outputs a refresh timing signal when the main memory module is not being accessed, the memory control means controls the refresh counter. The content is output as a refresh address to the memory bus, and the first timing signal is output to the main memory module, and the main memory module uses the address on the memory bus as a refresh address in the dynamic RA in its own module.
Claim 1, wherein the dynamic RAM is refreshed by applying the row address strobe signal to the address input of M and further turning on the row address strobe signal using the first timing signal. memory bus control method.