JPS63252014A - Phase synchronization method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a phase synchronization method that follows the frequency and phase of an input signal.

(Conventional technology and its problems) Conventionally, phase-locked circuits based on the PLL (phase-locked loop) method have been used as carrier wave regeneration circuits to create reference signals necessary for demodulating phase modulated waves, or as It is widely used in frequency tracking circuits and other applications. The frequency and phase pull-in characteristics of the phase-locked circuit using this PLL system depend on the equivalent noise bandwidth (loop bandwidth) determined by the loop gain, the characteristics of the loop filter, and the characteristics of the phase comparator. The wider the loop bandwidth, the faster the pull-in, and the narrower the loop bandwidth, the slower. However, when the loop bandwidth is wide, the output phase jitter in steady state is large, and when the loop bandwidth is narrow, it is small.

Generally, a phase synchronized circuit is required to have fast pull-in characteristics and to have small phase jitter in steady state, but these two requirements are contradictory problems as described above.

An example of a conventional technique that solves this problem is used in a part of a carrier wave regeneration circuit of a TDMA communication system. Here, T
Since a DMA signal consists of a plurality of mutually asynchronous burst signals, in order to demodulate this signal, it is necessary to perform the demodulation operation while creating a reference signal for each burst. It must be possible to establish synchronization within a very short time.

Furthermore, since TDMA signals generally have a high transmission speed, phase jitter in a steady state is required to be extremely small. To meet this requirement, the carrier wave regeneration circuit is controlled to increase the loop gain and widen the loop band during pull-in to speed up pull-in, and to lower the loop gain and narrow the loop band during steady-state operation to reduce phase jitter. There is.

FIG. 1 shows an example of the configuration of the above-mentioned prior art.
In (a), 101 is a signal input terminal, 102 is a phase comparator, 103 is a VCO (voltage controlled oscillator), 104
is an amplifier, 105 is a loop filter, 106 is a timing signal input terminal, and 107 is an output terminal.

Furthermore, FIG. 1(b) shows the phase comparison characteristics of the phase comparator 102, where the horizontal axis represents the phase difference θ between the input signal and the output signal of the V C0103, and the vertical axis represents the output voltage. .

The conventional example shown in FIG. 1 operates as follows. Phase comparator 10
2 outputs the phase difference between the input signal and the output signal of VC0103 as a voltage. This voltage is applied to amplifier 104.
Passes through the loop filter 105, joins the VCO 103,
The frequency and phase of the oscillation signal of V C0103 are controlled to approach the frequency and phase of the input signal. here,
As described above, the amplifier 104 adjusts the loop gain to change the loop bandwidth depending on whether it is in the pull-in or steady state, and its amplification is controlled by a timing signal that is detected separately and supplied to the terminal 106. be done.

A drawback of this method is that in order to change the loop band, timing information is required regarding when to start pulling in and when to reach a steady state. This requires a circuit for detecting timing and creating timing information, leading to increased complexity of the device.

On the other hand, this PLL type phase synchronization circuit also suffers from a phenomenon called a hang-up phenomenon in which the phase locking characteristic deteriorates, making it difficult to apply it to a place where phase synchronization must be established in a short period of time.

As can be seen from the phase comparison characteristics in FIG. 1(b), the hang-up phenomenon refers to the V
When the phase difference between the output signal of C0103 and the output signal of C0103 is π, the output of the phase comparator 102 becomes zero, the oscillation phase of the VCO 103 does not change, and the phase difference remains stable at π, resulting in a state in which synchronization cannot be established. say.

Furthermore, when the phase difference is not exactly π but extremely close to π, a phenomenon that can be regarded as a hang-up occurs, and the output of the phase comparator 102 becomes a value close to zero, and it takes a long time to establish synchronization. There were drawbacks.

A method for relieving this hang-up phenomenon and improving the synchronization pull-in characteristic is presented in the paper titled "Study of carrier wave regeneration circuit used for synchronization demodulation of rTDMA signals" (Confucian Society Journal Transactions vol.
, 54-B, Na41971, P160-1
67). This method is called the kick-off method, and measures the phase difference at the start of synchronization, and when the phase difference is close to π, the phase is forced to shift by π from the hang amplifier region (near π) to the stable region (near 0). It is a method. This method has the disadvantage that it cannot operate unless the synchronization start point is known, similar to the method described above in which the loop gain is changed between the pull-in state and the steady state. Additionally, if the input signal contains noise, it may not be possible to detect a hang-up phenomenon even though it is occurring, or it may be determined that a hang-up phenomenon is occurring even though it is not.
There are problems with so-called non-detection and false detection, and the hang-up phenomenon has not yet been completely eliminated.

(Object of the Invention) The present invention has been made in order to solve the drawbacks of the conventional phase synchronization method described above. It is an object of the present invention to provide a phase synchronization method that can establish synchronization in an extremely short time even for burst signals with frequency deviations.

(Structure and Features of the Invention) A feature of the present invention is that the baseband signal obtained by detecting the directly received signal with two orthogonal reference signals without using a phase comparator that causes a hang-up phenomenon. Digital calculation is performed to estimate the frequency difference 9 phase difference between the received signal and the reference signal using an optimization method, and phase synchronization is performed using these.

In addition, in order to establish high-speed and highly stable synchronization, there is a memory in the loop. By using this memory, it is possible to determine whether it is in the pull-in or steady state, and when the pull-in is in, high-speed phase synchronization is possible. This enables highly stable phase synchronization with low phase jitter during steady state.

According to the present invention, there is no hang-up phenomenon, and it is possible to pull in TDMA signals with large frequency deviations at high speed and with high stability.Furthermore, since the present invention is realized by digital arithmetic processing, analog Unlike the case of a circuit, it is possible to easily change the settings of its characteristics, and it is easy to set the optimum accuracy required for phase synchronization as a system, taking into consideration the transmission path condition.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 2 is a first embodiment of the present invention, which is a diagram showing a feedback type case. 1 is a human power signal terminal, 2.
3 is a multiplier, 4.5 is a low pass filter (LPF)
, 6.7 is an analog/digital converter (A/D), 8
9 is a digital arithmetic unit, 9 is a π/2 phase shifter, 10 is a variable phase shifter, 11 is a VCO (voltage controlled oscillator), and 12 is a reproduced signal output terminal. Here, if one input signal is modulated, the signal after the modulation component is removed is assumed to be input. The received signal S (t) is generally expressed by the following equation, assuming that it is an unmodulated signal.

S (t) −JHA cos θ(t) +n (
t) --------------------------- (1) In formula (1), A
denotes the amplitude level of the received signal, θ(t).

n (t) represents the phase component and noise component of the received signal, respectively, and are expressed by the following equations.

θ (shi) = ω. t +Δω(+θ −・−−−−・−
・−・−・・−・−１−−・・(2) However, ω. indicates the reference angular frequency of the received signal, Δω is the angular frequency deviation amount from the reference signal, and θ is the initial phase.

n (t) = a n , (t)cosθ(1)+
a n z (t) sin θ (t) ・------
-=- (3) However, n 1 (t) and n z (t) are Gaussian noise components with an average value of 0 that are orthogonal to each other. The circuit of FIG. 2 aims to accurately estimate θ(1) from the noisy received signal S (t) and reproduce a signal synchronized with the received signal.

The basic operation of this circuit will be explained below, and then the case for an asynchronous burst signal such as a TDMA signal will be explained. The received signal s (t) is multiplied by the orthogonal 91.101 signals by multipliers 2 and 3, respectively. The signals 101 and 91 are respectively expressed by the following equations.

e + (t) = a cosθ+(t) --
−−−−−−−−−−−−−−−−−−−(4) ez(
t)=v'N5inθ, (t) --------
−−−−−−−−−−−=−−−15) However, θ1(t
) is the oscillation angular frequency ω of VC○11. °〔=ω. +Ω.

] and the phase shift amount T0 controlled by the phase shifter 10, and is expressed by the following equation.

θ, (1)−ω. t+ε. t-+-70・---1-
−・−・・−−−−−−−・−・(6) However, Ω. and T indicate the frequency difference and phase difference estimated by the digital arithmetic unit 8, but in the following explanation, it is assumed that these two values start from the initial state, that is, zero.

The output signals 21 and 31 of the multipliers 2 and 3 are respectively LPF4.
.

)' 1(t) = 77 (t)cos ξ(t)
−−−−−−=−−−−−−−−−−−−−17)
yz(t)=η(t)s in ξ(1) ・-
・−・・−・−・・−・・−・・−・・−(8) However, ξ(t)=θ(1)−θ1(t)−ψ(t)−・−−1−・−・0■ The signals expressed by equations (7) and (8) are sampled at a timing period T and sent to the A/D converter 6.7.
It is converted into a digital signal. The output signals 71 and 61 of the A/D converters 7 and 6 in the first sample are respectively expressed by the following equations.

XI=77! CO5ξi −−−−−−−−−−
−−−−−−−−−−−02) Y, = η6 sin
ξ, −・・−・・−・−・−−−１−・・・・−・−
・−・− side However, ξ1 = θ (t,) − θI (tz) − ψ (triti
-tz-t ='r The digital arithmetic unit 8 performs the following calculation using X, , Y, and estimates θ(1).

First, x,,y for each input sample point.

Using 2Q4), perform the operation shown in (1) and
Find 1゜ξ.

ξ, denoted by 20ω, can only be found at the upper value of the range −π≦ξ, ≦π.

Therefore, the net angular rotation A at each sample point is determined by the operation shown below.

Here, the relationship shown in the following equation holds between A and ξ.

A5 (mod2tt) = ξ, ------------
---By using the relationship of a'n formula 07), 202
), 03) are as follows.

Xmu=ηmucosA! ...-Song/song times--
-Song...0 ■Y 6 = ηis in A,
−−−−−−−−−−−−−・−−−・−−−−−−−
−09) Next, 2〇8), by using θ field, Δω
A method for estimating θ and θ is shown below.

Here, the estimated Δω and θ are respectively ε1゜′
i''.

Transform equation (1B) and G9) into the following equation using ε, and f+.

Xal=77i cos(At Glt+'Fl
)...-(2eYet=77 MU5in(At G
+t=? l) --- [211 Next, consider the following operation for N samples from t to tN-1.

If YaN takes the maximum value, as is clear from the relationship of equation as, +21, or? . If 8 takes the minimum value,
This means that Δω and θ were estimated most correctly with Ω1 and '7''1.

Therefore, the problem of estimating Δω and θ comes down to finding ε1 and f + when 7.14 is the maximum (or when 7.M is the minimum).

ε and T for maximizing ¥ can be determined as follows by using a partial division method, which is one of the optimization methods.

First, equation (2) is partially differentiated as a function of Ω1 and T.

Isshin+Lm '2r+)・-・・・・・・(company)-ε
+1m? υ−・・・・・・・・・Here, ε1 and 7′1 for ma to be maximum are:
Shiki (sha), c! This is the solution when 9 becomes O.

On the other hand, 60 ε1. If θfb is 71, the following relationship holds true.

sin(AmiQ+tmit) zAll−ε
1LII T+ −−−−−−−−−−−−−
.OMEGA. and 'i'1 can be obtained as follows by solving the simultaneous equations of Equation (sha) and (251) using the relationship .

Σ ηkA, Σ ηktk−Σ ηktkΣ ηkjk
Ak11116 - 0k-6 -0 In formula (2), t is a time considered for convenience as shown in formula (c), Ql). Therefore, consider here that tk=kT.

Substituting the above relationship into Nihan and @, G+, ? 't
are calculated as follows.

The calculation corresponding to the formula 0 is performed by the digital calculator 8 shown in FIG. An example of the configuration of the digital arithmetic unit 8 is shown in FIG.

In FIG. 3, Xt and Yi for each sample point are input to 71.61. 13 is a phase calculator, 14 is a net circumferential rotation amount calculator, 15 is a received signal amplitude level calculator, 16 is a multiplier, 17 is an adder, 18 is an estimator for ε, 'i'', 20
is a data sample number counter, and T and ε estimated by the estimator 18 are output at 81.82.

The operation of the digital calculator 8 in FIG. 3 is as follows: phase calculator 13 uses equation 0ω, rotation amount calculator 14 uses equation 0ω, amplitude level calculator 15 substitutes, multiplier 16 . The adder 17 uses the formula (
The estimator 18 uses the value of each element obtained from the output of the adder 17 to calculate the expression
Calculate. ε and T now obtained at the output terminals 82.81 control the VCO II and the phase shifter IO of FIG.

However, since the frequency of the VCOII is controlled by a voltage value, the output ε of the digital calculator 8 in FIG. 2 is the reference signal ω of the VCOII. It is assumed that the voltage value is converted into a voltage value for outputting a frequency shifted by ε from the current value, and this voltage value is inputted to the VCO II via the output terminal 82. Further, the phase shifter 11 can be realized, for example, by a delay line circuit according to the phase difference, and the delay of the delay line constituting the variable phase shifter 10 is determined according to the output T to the output terminal 81 of the digital arithmetic unit 8. Change the amount.

Through these operations, a signal whose phase is synchronized with the received signal 1 is outputted to the terminal 12.

The phase synchronized circuit of the feedback type has been described above. Next, a second embodiment of the present invention will be described. In the first embodiment, which shows a feedforward type embodiment in FIG. control,
It was a feedback type phase synchronization circuit that synchronized the phase of the received signal. On the other hand, in the feedforward type shown in FIG. 4, the output of the fixed oscillator 19 is directly used as the reference signal wave, and the reference signal wave always has a constant frequency value. The processing in the digital arithmetic unit 8 is the same as that described in the first embodiment, and the outputs 81 and 82 of the digital arithmetic unit 8 contain the phase difference of one frequency between the received signal and the fixed oscillator output signal. The variable phase shifters IQ and VCOII in FIG. 4 output the estimated values of the differences, respectively, and the phase differences are output to the output terminals 81 and 82, respectively.

Controlled by the frequency difference, a reproduced signal is obtained at the output terminal 12.

The operations described above are the basis of the present invention. Next, when applying this phase-locked circuit to TDMA communication in which multiple asynchronous signals are received in a burst form, or when the received signal fluctuates over time depending on the transmission path condition, this phase-locked circuit can be used. The case where it is applied will be explained.

Figure 5 shows the angular frequency deviation N estimated by the digital calculator 8.
An example of the temporal change of (Ω,) will be shown.

The operation of the phase locked circuit of the present invention shown in FIG. 2 will be explained using FIG. 5.

The frequency difference Ω and the phase difference 7'1 are estimated using N samples from time t0 to LH-1. At this time, the difference E between the estimated Ω1 and the vCO output frequency color from to to LH-1 is determined and compared with El and a predetermined threshold value E. At this time, for example, if E is larger than E, it is determined that the fluctuation of the received signal is large, and (
From t and l (corresponding to the pull-in time in a TDMA signal), the oscillation frequency of the VCO II is set to (ω, 10Ω,), and the phase of the phase shifter 10 is set to 71, as shown in equation (2).

Next, for N samples from tN to L2□1, εt + Tt is estimated in the same way as above, and the difference E! between Ω1 and ε2 is calculated. Find and compare with E.

In the example of FIG. 5, E2 also has a larger value than E, and VCo
A case is shown in which the oscillation frequency of ll is changed from t2.4 to (ω.1ε2). In Figure 4, further from tzN to t3N
Ω estimated using N samples up to −1.

The difference E between and ε2 is shown for the case where it is smaller than E3. In this case, it can be inferred that the state of the received signal is stable. (Steady state for TDMA signals) In this case, the oscillation frequency of VCOII from t2N is left as (ω.192), and then N samples from tffN are taken in, and 2N samples from tzN are used to calculate Δω. Estimate θ. Increasing the number of samples used for estimating Δω and θ in this manner corresponds to narrowing the loop band in the PLL system, and enables phase synchronization with small phase jitter.

However, in order to detect sudden fluctuations in the received signal during the period in which 2N samples are taken, as shown in FIG.
! ε11+ using N samples from N+1 to t3N
Also estimate 1r3+.Similarly, from tiN+□, t
. 4. Until, t! Also from Ml, 8. Using the data of N consecutive samples, such as up to t, Ω, 2. The estimation operation for ε1° is performed in parallel with the estimation operation using the 2N samples described above.

Here, ε is estimated sequentially using N consecutive samples.
31+ Difference E between island, t... and ε2, E,2.
Find each of them and compare them with E3.

FIG. 5 shows a case where Eji E3z, . . . E3+N-1 found between N samples from t3N to t4N-1 are all smaller than E. At time t4, 4, here IQ4 estimated using 2N samples from tzN to t4t, 't<1'' V C011
and controls the phase shifter 10.

If the system is stable from t4N, phase synchronization is performed every 2N samples by the operation described above.

Here, for example, if the received signal changes rapidly (corresponding to a change in the burst signal in a TDMA signal) when control is entered for every 2N samples, as shown in the example of FIG. a) At Inx, the difference E4 between ε4□ and 94 estimated using N samples! is E,
It is possible to detect it by becoming larger. In this case, at the time of 14N+ffi, the VCOII and the phase shifter 10 are controlled by ε4□ and 'F4□ estimated by N samples from t 3N+1 to t 4N+2, and even against sudden fluctuations in the received signal, Phase synchronization becomes possible.

As mentioned above, this phase-locked circuit can determine whether it is in the pull-in or steady state, and during the pull-in, high-speed pull-in is possible by taking a small number of samples used to estimate Δω and θ. In steady state, a large number of samples are used to enable high-quality phase synchronization.

On the other hand, the number of samples used as the unit for estimating Δω and θ (N in the above example), the number of samples used in steady state (2N in the above example), and the frequency difference threshold W E s is determined based on the state of the transmission path, the accuracy required of the phase locked circuit from the perspective of the entire system, and the like. These parameters can be easily changed because the estimation of the frequency difference and the phase difference is obtained by digital calculation.

(Effects of the Invention) As explained in detail above, according to the phase synchronization method according to the present invention, the frequency deviation amount and phase error amount between the received signal and the reproduced signal are estimated using a direct optimization method. It is possible to accurately obtain the frequency deviation and the phase error even when the phase error is large.

Furthermore, when estimating the frequency deviation and phase error using the optimization method, the number of sample data used can be set to any number depending on the state of the received signal (for example, when TDMA signal is pulled in or during steady state). It is. As a result, phase synchronization can be established at high speed using a small number of data samples during pull-in, and during steady state,
It becomes possible to take a large number of data samples and establish high-quality phase synchronization. Here, the determination of the pull-in state and the steady state state can be made by storing the history of the frequency deviation amount 9 phase error amount estimated in the past within the loop.

Further, parameters such as the number of data samples used for estimation can be easily changed from the outside according to the transmission path condition, and it is possible to provide an optimal phase synchronization method.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram showing a conventional PLL type phase-locked circuit, FIG. 1(b) is a characteristic diagram showing the phase comparison characteristics of the conventional phase-locked circuit, and FIG. 2 is a feedback-type phase-locked circuit according to the present invention. FIG. 3 is a block diagram showing an example of a digital arithmetic unit used in the present invention. FIG. 4 is a block diagram showing an example of a feedforward type phase-locked circuit of the present invention. FIG. FIG. 4 is a diagram showing a temporal change in the amount of frequency deviation estimated when the present phase synchronization circuit is applied to TDMA communication in which signals of 1 and 2 are received in a burst manner. 1... Input signal terminal, 2.3... Multiplier, 4.5
...Low pass filter, 6.7...Analog/digital converter, 8...Digital arithmetic unit, 9.
...π/2 phase shifter, 10...Variable phase shifter, 11...
・Voltage controlled oscillator, 12... Reproduction signal output terminal, 1
3... Phase calculator, 14... Angular rotation amount calculator, 1
5... Amplitude level calculator, 16... Multiplier, 17
... Adder, 18... Estimator, 19... Fixed oscillator, 20... Sample number counter.

Claims (4)

[Claims] (1) The received signal is phase-detected using a first reference signal controlled by a voltage-controlled oscillator and a phase shifter, and a second reference signal that is orthogonal to the first reference signal, and the two obtained The baseband output signal is sampled at a certain period, and further A/
D-convert it to digital values, calculate the phase and amplitude values for each sampling point from these orthogonal digital values, and calculate the received signal and the received signal using a plurality of phase data and amplitude value data obtained within a certain period of time. Estimating a frequency difference and a phase difference with the first and second reference signals using an optimization method, and controlling the voltage controlled oscillator and the phase shifter with the estimated values of the frequency difference and the phase difference. and a phase synchronization circuit configured to generate a reproduced signal phase-synchronized with the received signal. (2) Frequency difference estimated in the past during the above estimation. It has a circuit that stores the history of phase differences, compares these stored values with sequentially estimated values, infers the received signal state based on the comparison results of these two values, and uses these analogy results as the basis. The invention is characterized in that the number of data samples used to estimate the frequency difference and the phase difference is made variable so that optimal phase synchronization can be achieved depending on the received signal condition. The phase-locked circuit according to range 1. (3) The received signal is phase-detected using a first reference signal from a fixed oscillator and a second reference signal that is orthogonal to the first reference signal, and the two baseband output signals obtained are detected at a certain period. Then, A/D conversion is performed to obtain digital values, and the phase and amplitude values for each sampling point are determined from these orthogonal digital values, using multiple phase data and amplitude data obtained within a certain period of time. estimate the frequency difference and phase difference between the received signal and the first and second reference signals using an optimization method, and control the voltage controlled oscillator and the phase shifter using these estimated values. , A phase synchronization circuit configured to generate a reproduced signal that is phase-shift synchronized with the received signal. (4) It has a circuit that stores the history of frequency differences and phase differences estimated in the past during the above estimation, and compares these stored values with sequentially estimated values, and compares these two values. The received signal condition is estimated based on the results, and the number of data samples used to estimate the frequency difference and phase difference is made variable based on these analogy results, thereby achieving optimal phase synchronization according to the received signal condition. The phase synchronized circuit according to claim 3, characterized in that it is configured to realize the following.