JPS63200685A - playback device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital image recording and reproducing apparatus.

In conventional digital VTRs, effective samples of a video signal converted into sidigital data through sampling and quantization are divided into a plurality of blocks per horizontal scanning period, and each block is subjected to first error correction. It is encoded (this is called an outer code) and then written to a relatively large capacity memory. The written information words and check words are read out in a different order than when they were written (this is called shuffling), and then subjected to a second error correction encoding (
After applying an inner code (this is called an inner code), a synchronization signal and address information are added and recorded on the tape.

3. When reproducing recorded data, a synchronizing signal is detected from the serial data string obtained from the reproducing head, and serial/parallel conversion is performed.
Extracts address information, etc.

The parallel-converted data words are error-detected and corrected by the inner code, and are written to the reproduction memory together with error flags according to the extracted address information. Reading from the reproduction memory is performed in a different order from writing, and the information words, check words, and error flags of the outer code are read in the same order as they were written to the recording memory (this is called deshuffling).

Next, the outer code is decoded to correct any errors that may have occurred during the recording/playback process on the tape.

Reed-Solomon codes are generally used for the inner code and the outer code. Decoding a Reed-Solomon code consists of (1) finding the syndrome, (2) finding the error position and value based on the syndrome, and (3) finding the error position and value based on the syndrome.
) Correcting is performed in three stages: correction is made according to the position and size of the determined error.

Here, the block diagram shown in FIG. 5 shows the principle of the circuit for determining the syndrome. For explanation, R8(3
4, 32) Taking the code as an example, the data input from the input terminal 501 is a word string as shown in FIG. In the figure, 32 words a2 to a33 are information words,
It consists of the original data word before being encoded.

Also, aOj al is a check word added by error correction encoding. Such a word string is input to the circuit shown in FIG. In the figure, 502 is a D register that performs a one-word delay, 503 is an adder that performs mod 2 addition, and 504 is a Galois field element σ' (i = o, 1
), 501 is an input terminal, and 505 is an output terminal. Now, after clearing the D register 502,
A33. a32...al
When l”O is input according to the clock, the output terminal 505
are sequentially a331 a33α1 ten a32. a33σ2
10a32-10a31. ...... is obtained, and finally, syndrome 5 = a33α33i+, 32α''10...-+a1
αi tena.

is obtained.

When the above-mentioned outer code syndrome is determined using such a circuit, the data read from the reproduction memory is as shown in FIG. In the figure, aJ, ~ a3 deception is the information word f:s a4. in the jth outer code.
a and J are check words in the j-th outer code, and the numbers above the arrows indicate the number of words in each part (j=o, 1...11).

The check words a4 and &A are redundant words inserted when the outer code is encoded, and are no longer needed after the outer code is decoded. Therefore, in the above-mentioned configuration, 1. the check words aL-, and their time slots are removed from the data word string read from the reproduction memory, and converted into a digital video signal consisting only of the information words aλ3°, 4; In order to do this, a relatively small capacity buffer memory was used after error correction, and time axis processing was performed.

Problems to be Solved by the Invention In the above configuration, after error correction is performed on the word string deshuffled and read out from the playback memory, it is written again to the buffer memory and loaded into the buffer memory. Since the test word is then removed and only the valid samples are read, a buffer memory for about one line is required, and its control becomes complicated.

Means for Solving the Problem The present invention divides the effective samples of one horizontal scanning period of a digitized video signal into a plurality of blocks, and performs error correction for each of the blocks by using the effective samples as information words. In a device that encodes data and adds a check word to it, and then records and reproduces it on a recording medium via memory, the data is read from the memory during playback, and the information words are checked so that they are lined up for each error correction code during the valid sample period. The words are arranged for each error correction code during the invalid sample period, and a part of the syndrome calculation is performed for each error correction code on either the information word or the check word from the memory configured in this way. When the other of the information word and check word is input, the intermediate 7 Beno results corresponding to each error correction code are extracted from the above register, and the remaining part of the syndrome calculation is performed. This is a playback device that has a syndrome calculation circuit that performs.

In the present invention, effective samples of one horizontal scanning period of a digitized video signal are divided into a plurality of blocks, and for each block, the effective samples are error-corrected encoded as information words and a check word is added. In a recording and reproducing device that records data on a recording medium through The test words, which are redundant words, are read out in sequence, and the check words, which are redundant words, are read out during the invalid sample period. Syndrome calculations are performed for each block on the information word string and check word string read out from memory, and the results are temporarily stored in multiple registers. The process is performed twice by storing the data, and errors are determined according to the obtained syndrome, and error correction is performed.

Therefore, the data word string read from the memory and subjected to the decoding of the error correction code has the information word string corrected in the correct order in the valid sample period, and the check word string exists in the invalid sample period, so the buffer memory is There is no need to perform time axis processing via the digital video signal, and the digital video signal can be reproduced as it is.

Embodiment The second block diagram of the playback device in the embodiment of the present invention is shown below.
As shown in the figure. Further, an example of the outer decoding circuit in this embodiment is shown in FIG. As an example, in this embodiment, an NTSC video signal is sampled at four times the color subcarrier frequency, quantized to 8 bits, and divided into two channels. 384, and the number of invalid samples is 71. If this effective sample is divided into, for example, 12 blocks, and two check words are added to each block as information words using a Reed-Solomon code, the outer code is R8 (34°9beno32). becomes. After writing these information words and check words into memory and performing shuffling, a number of redundant words are added using an inner code, and a synchronization pattern and address information are added, and the data is recorded on the magnetic tape. do.

In FIG. 2, 201 is a playback head, 202 is a playback amplifier, and 203 is a playback head 2o1. playback amplifier 20
A synchronization circuit that reproduces the clock from the signal reproduced from 2, performs pit synchronization, extracts a synchronization pattern, completes word synchronization, and outputs address information and parallel word data.

204 is an inner decoder that decodes the inner code for the reproduced parallel word data.

205 is an address signal processing circuit for determining a write address to the memory according to the extracted address information;
6 is a relatively large-capacity memory that performs time axis operations such as deshuffling and transmission rate conversion, 207 is a decoder that decodes the outer code, and 21o is deshuffled and sent to the correct digital video signal in the same order as the 1/2 digital video signal. A playback word string in which information words are arranged and test words are inserted into the invalid sample period,
211 indicates a digital video signal corrected by an outer code.

Playback head 2o1. The reproduction signal obtained by the reproduction amplifier 202 is sent to the synchronization circuit 203, where it is synchronized and extracted with parallelized address information, and then error correction is performed on the parallel data by the inner decoder 204, and the address signal is Write to memory 206 according to the memory address obtained by processing circuit 205. Memo IJ 20
6, the deshuffled data 210 is sent to the outer decoder 207, and an error-corrected digital video signal 211 is obtained. In this embodiment, the deshuffled data 210 constitutes a digital video signal, and during the effective sampling period, only the information words of the actor code are divided into 12 blocks, each block consisting of 32 words, as in the case of sampling. Subsequently, during the invalid sample period, 12 blocks of check words of the outer code are inserted, 2 words per 1 block. This is shown in FIG. In the same figure, aj(i=o.

1,...,11; j=ot'+...
..., 33) indicates a data word, and a2~
a33 is the information word of the 0th block, a0+ a
l is the check word of the 0th block, a2 to a3
3 is the information word of the first block, “Oj a
1! represents the check word of the first block. Also, the numbers attached to the arrows in the figure indicate the number of words in each part.

As shown in the figure, 465 words in one horizontal scanning period include 384 information words in 12 blocks in the valid sample period and 2 check words in 12 blocks in the invalid sample period.
It consists of 4 words and 47 words of invalid data.

An outer decoder 2 that decodes an outer code for the digital video signal 210 configured as described above.
An example of 07 is shown in FIG. Further, a simple time chart showing the operation of this circuit is shown in FIG. In FIG. 1, 101 and 102 are mod 2 adders, 103 and 104
is a D register that performs a one-word delay, 105 and 106 are coefficient units that multiply the Galois field elements α0 and α, respectively, and 10
7.108 is a multiplexer that selects either the output of the shift register or the output of the D register according to the control signal, 1
09.110 is a shift register that temporarily stores the intermediate results of the calculation to obtain the syndrome, 111 is an error derivation circuit that obtains an error based on the obtained syndrome, and 112 is a 1-line delay circuit that delays data for 1 horizontal scanning period. , 113 is the delayed data and error derivation circuit 1
Adder 101.11 is an adder that adds the errors obtained by mod 2 and performs error correction. D register 1o
The 3° coefficient unit 105 constitutes the entire syndrome calculation circuit based on the same principle as that shown in FIG.

The operation of outer decoding in this embodiment will be explained below. Regarding the signal input to the outer decoding, as shown in FIG. 3, for one outer code, the information word is in a valid sample period, and the check word for it is located apart in an invalid sample period. Therefore, in this conventional example, 13 beno has syndrome 5=a3 deception α"10 a3 deception"10・----+aJa'
+ a, 4ti = 0, 1 j = 0, 1,...
...The part of 11 that can be calculated only using information words SL =a3), ct511 +aJ2ct301+
・・・・・ Find up to 4 and store this once in the shift register 1o9°11o. When the test word is input, read it from the shift registers 109 and 110 and calculate 5 from the test word aLa. =84. Syndrome S is determined as ct2i-4-aJcf'+aA.

This situation is shown in FIG. In the same figure, S positive is an intermediate result of syndrome calculation, S positive = (... (a3'3σ1 + a352')σ
・・・・・・+a run-ai, a(53-k)i+ sL
a (32-k)z +,,,,,,,+・bar. 1・
It can be expressed as 1+・positive. When all of the information words a3L to a4 of the j-th outer code have been input, the adder 10
The output of 1,102 is the intermediate result of syndrome calculation s4
is obtained. This is taken into shift registers 109 and 110 in accordance with a clock 1/14 shown in FIG. The shift registers 109 and 110 have a depth of 1
It is a 2-word shift register, so s4 is 12.
After shifting times, the output of the shift register is obtained. At this time, exactly =4 is input to the input terminal, and by selecting the outputs of shift registers 109 and 110 by multiplexers 107 and 108, 54 =
s, 4αi+a4 is determined, and in the next time slot, the syndrome 55=S4ct''−A is determined by switching the multiplexers 107 and 108.The determined syndrome is again stored in the shift register 109 as shown in FIG. . As shown in the figure, the error is determined in 32 clocks, and during the next 32 clocks, the 1-line delay circuit 112 outputs a 15-hour pattern corresponding to the information word "3'3~mother-in-law". However, the adder 113 performs correction.

As explained above, in this embodiment, the shift register 1
By using 09, 110 and the 1-line delay circuit 112, syndromes are determined from information words and check words that are temporally separated from each other, and error correction is performed. As a result, the data read from the memo IJ 206 can be in the form of a digital video signal in which information words are read out during the valid sample period and all test words are inserted into the invalid sample period, and time axis processing after error correction is not required. .

Effects of the Invention As explained above, according to the present invention, by reading data in the form of a digital video signal directly from the memory for shuffling, there is no need for a circuit to remove the check word and its time slot after error correction. Then,
As a result, the conventionally required buffer memory is replaced with a one-line delay circuit, and its control becomes much simpler and easier to implement.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an outer decoding circuit in an embodiment of the present invention, FIG. 2 is a block diagram of a playback device in an embodiment of the present invention, and FIG. 3 is a configuration of data read from memory in an embodiment of the present invention. FIG. 4 is a timing diagram showing the decoding operation of the outer code in the embodiment of the present invention, FIG. 5 is a block diagram showing the syndrome calculation circuit in the conventional example, and FIG. 6 is an example of the outer code. FIG. 7 is a block diagram showing the structure of data read from a memory in a conventional example. 101.102,113,503...mod2
adders, 103, 104, 502---...D
Vshi, Z, evening, 105, 106, 504--
Coefficient unit, 107, 108...Multiplexer,
109, 110...Shift register, 111.
...Error derivation circuit, 112...1 line delay circuit, 2o6...Memory, 207...
...Outer decoder.

Claims (1)

[Claims] The effective samples of one horizontal scanning period of the digitized video signal are divided into a plurality of blocks, and for each block, the effective samples are error-corrected encoded as information words, a check word is added, and the information is stored in a memory. In an apparatus for recording and reproducing data on a recording medium, when reading data from the memory, the information words are arranged for each of the plurality of error correction codes during the valid sample period, and the check words are arranged for the plurality of error correction codes during the invalid sample period. A part of the syndrome calculation is performed for each error correction code on either the information word or the check word from the memory configured in this way. A plurality of registers temporarily store intermediate results, and when the other of the information word and the check word is input, the intermediate result corresponding to each error correction code is extracted from the plurality of registers and the syndrome calculation is performed. A reproducing device having a syndrome calculation circuit that performs the remaining portion.