JPS63172469A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS63172469A JPS63172469A JP62004662A JP466287A JPS63172469A JP S63172469 A JPS63172469 A JP S63172469A JP 62004662 A JP62004662 A JP 62004662A JP 466287 A JP466287 A JP 466287A JP S63172469 A JPS63172469 A JP S63172469A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- tpt
- film transistor
- staggered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
Landscapes
- Thin Film Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
薄膜トランジスタのオフ電流の増加と電界効果易動度の
低下を防ぐ方法として透明導電膜とn゛非晶質シリコン
膜との間に・チタン或いはクローム金属薄膜を介在させ
た薄膜トランジスタ。[Detailed Description of the Invention] [Summary] As a method for preventing an increase in off-state current and a decrease in field effect mobility of a thin film transistor, a titanium or chromium metal thin film is placed between a transparent conductive film and an amorphous silicon film. Interposed thin film transistor.
本発明は電気的特性を向上した薄膜トランジスタの構成
に関する。The present invention relates to a structure of a thin film transistor with improved electrical characteristics.
薄膜トランジスタ(略称TPT)はプラズマ化学気相成
長法(略称P−CVD)や真空蒸着法などの薄膜形成技
術を用いてガラスなどの絶縁基板上に非晶質シリコン(
以下略してa−3i)からなる半導体膜や窒化珪素(S
iNx)、二酸化珪素(SiO□)などの絶縁膜や金属
膜を形成すると共に、これと写真蝕刻技術(フォトリソ
グラフィ)を組合わして微細パターンを層形成すること
により作られている。Thin film transistors (abbreviated as TPT) are made by depositing amorphous silicon (
A semiconductor film made of silicon nitride (S
It is made by forming an insulating film or a metal film such as silicon dioxide (SiO□) or silicon dioxide (SiO□), and combining this with photolithography to form a fine pattern in layers.
か−る技術を使用すると広い面積に亙ってトランジスタ
・アレイが形成できることからTPTはアクティブマト
リックス形の液晶表示パネルにおけるスイッチング素子
として使用されている。Since a transistor array can be formed over a wide area using this technique, TPT is used as a switching element in an active matrix type liquid crystal display panel.
かかる用途において、TPTはスイッチング速度が速く
、且つ電界効果易動度(以下略して易動度)が速いこと
が必要である。In such applications, TPT is required to have high switching speed and high field effect mobility (hereinafter simply referred to as mobility).
TPTにはソースおよびドレイン電極とゲート電極との
配置によりスタガード形と逆スタガード形とがある。There are two types of TPTs: a staggered type and an inverted staggered type, depending on the arrangement of source and drain electrodes and gate electrodes.
第3図は従来のスタガード形TPTの断面構成図であっ
て、ガラス基板lの上にスパッタ法などにより酸化錫(
Snow)と酸化インジウム(InzOa)の固溶体よ
りなり低抵抗の透明導電膜(以下通称のITO膜)2と
燐(P)をドープした非晶質シリコン膜(以下略してn
”a−5t膜)3を層形成した後、写真蝕刻技術を用い
て選択エツチングを行ってソース電極Sとドレイン電極
りとをパターン形成する。FIG. 3 is a cross-sectional diagram of a conventional staggered TPT, in which tin oxide (tin oxide) is deposited on a glass substrate l by sputtering or the like.
A low-resistance transparent conductive film (hereinafter commonly referred to as ITO film) made of a solid solution of indium oxide (InzOa) and amorphous silicon film doped with phosphorus (P) (hereinafter abbreviated as n)
After forming the "a-5t film) 3, selective etching is performed using photolithography to pattern the source electrode S and the drain electrode.
次に、この上に非晶質シリコン膜(以下略してa−Si
Djり 4を形成した後、この上に窒化シリコン膜(
5iN)、膜)、酸化シリコン膜(Stow膜)、酸窒
化シリコン膜(SiON膜)の何れからなるゲート絶縁
膜5とクローム(Cr)やニクロム(Ni−Cr)など
の金属からなる電極膜6を層形成した後、写真蝕刻技術
を用いて選択エツチングしてゲート電極Gをパターン形
成すると共に素子間分離を行ってスタガー丁形TPTが
形成されている。Next, an amorphous silicon film (hereinafter abbreviated as a-Si) is placed on top of this.
After forming Dj 4, a silicon nitride film (
A gate insulating film 5 made of any one of a silicon oxide film (Stow film), a silicon oxynitride film (SiON film), and an electrode film 6 made of a metal such as chromium (Cr) or nichrome (Ni-Cr). After forming a layer, a gate electrode G is patterned by selective etching using a photolithography technique, and elements are separated to form a staggered TPT.
一方、逆スタガード形TPTはガラス基板1の上にゲー
ト電極Gを設けた逆構成をとって形成されている。On the other hand, an inverted staggered TPT is formed with a reverse configuration in which a gate electrode G is provided on a glass substrate 1.
かかる構成をとるTPTは素子完成の後に電気的特性を
安定化するために200〜300℃の熱処理(アニール
)プロセスがあり、また液晶表示パネル形成に当たって
各種の熱処理を蒙るが、この工程においてソース電極S
およびドレイン電極りを構成するITO膜2のIn原子
およびSn原子がn″−a−5i膜3を通ってa−Si
膜4の中に拡散し、そのためにa−St膜4の欠陥が増
加してオフ電流の増加゛や易動度の低下を生ずると云う
問題があった。TPTs with such a configuration undergo a heat treatment (annealing) process at 200 to 300°C to stabilize the electrical characteristics after the element is completed, and are also subjected to various heat treatments when forming a liquid crystal display panel. S
In and Sn atoms of the ITO film 2 constituting the drain electrode pass through the n''-a-5i film 3 to the a-Si
There is a problem in that the a-St film 4 is diffused into the film 4, thereby increasing the number of defects in the a-St film 4, resulting in an increase in off-state current and a decrease in mobility.
液晶表示パネルの駆動に使用されるTPTのソース電極
Sとドレイン電極りは液晶素子の透明電極と同じ工程で
パターン形成されるためにITO膜2が使用されている
が、TPTの安定化処理を始としアクティブマトリック
ス形の液晶表示パネルの形成に伴う熱処理によりITO
膜を構成するIn原子とSn原子がオーミック接続を行
うために設けられているn”a−5i膜3を通ってa−
St膜4の中に拡散し、それによりa−St膜4の欠陥
が増加してオフ電流の増加や易動度の低下を生じている
ことが問題である。The ITO film 2 is used for the source electrode S and drain electrode of the TPT used to drive the liquid crystal display panel because they are patterned in the same process as the transparent electrode of the liquid crystal element. Initially, ITO is processed through heat treatment associated with the formation of active matrix type liquid crystal display panels
A-
The problem is that it diffuses into the St film 4, thereby increasing the number of defects in the a-St film 4, resulting in an increase in off-state current and a decrease in mobility.
上記の問題はTFTのソース電極およびドレイン電極を
形成する透明導電膜とn+非非晶質シリコ腹膜の間に金
属薄膜を介在させることにより解決することができる。The above problem can be solved by interposing a metal thin film between the transparent conductive film forming the source and drain electrodes of the TFT and the n+ amorphous silicon peritoneum.
本発明はソース電極Sとドレイン電極りを構成するIn
およびSn原子のa−3il14への拡散を防ぐ方法と
して、ITO膜2とオーミック接続をとるために設けら
れているn”a−5i膜3との間にチタン(Ti)やク
ローム(Cr)などの高融点金属膜を設けるものである
。In the present invention, In which constitutes the source electrode S and the drain electrode
As a method for preventing the diffusion of Sn atoms into the a-3il14, titanium (Ti) or chromium (Cr) is used between the ITO film 2 and the n''a-5i film 3 provided for making an ohmic connection. A high melting point metal film is provided.
第1図は本発明に係るスタガード形TPTの断面構成図
であって、金属膜7をソース電極Sとドレイン電極りを
形成するITO膜2とn” a−Si膜3との間に介在
させている。FIG. 1 is a cross-sectional diagram of a staggered TPT according to the present invention, in which a metal film 7 is interposed between an ITO film 2 and an n'' a-Si film 3 that form a source electrode S and a drain electrode. ing.
ここで、金属膜の必−条件は熱が加わっても拡散が起こ
りにくいことで、この点から融点が1600℃以上のT
iやCrなどが適している。Here, a necessary condition for the metal film is that it is difficult to diffuse even when heat is applied, and from this point on, T
i, Cr, etc. are suitable.
本発明はかかる金属膜を500人程度の厚さに設けるこ
とによりソース電極Sとドレイン電極りからのIn原子
とSn原子の拡散を阻止するものであるる。The present invention prevents the diffusion of In atoms and Sn atoms from the source electrode S and the drain electrode by providing such a metal film with a thickness of about 500 nm.
なおこの場合、ソース電極Sおよびドレイン電極りの呼
称はITO膜2と金属膜7の両者を含むが、金属膜7は
ITO膜2の透明性を損なわないためにa−5t膜4と
ほぼ等しい大きさに形成する必要がある。In this case, the names of the source electrode S and the drain electrode include both the ITO film 2 and the metal film 7, but the metal film 7 is almost the same as the a-5t film 4 in order not to impair the transparency of the ITO film 2. It needs to be shaped to size.
〔実施例〕
第4図は本発明に係るスタガード形TPTの製造工程を
示す断面図であって、実施例を示すと次ぎのようになる
。[Example] FIG. 4 is a sectional view showing the manufacturing process of a staggered TPT according to the present invention, and an example is shown as follows.
ガラス基板1の上にスパッタ法によりITO膜2を10
00人の厚さに形成した後、電子ビーム蒸着法によりT
iを500人の厚さに形成して金属膜7を作り、その上
にP−CVD法により300人の厚さにn0a−5i膜
3を形成した(以上同図A)。10 ITO films 2 are deposited on a glass substrate 1 by sputtering.
After forming the film to a thickness of 0.00 mm, T
A metal film 7 was formed by forming a metal film 7 with a thickness of 500 mm, and an n0a-5i film 3 was formed thereon with a thickness of 300 mm using the P-CVD method (see A in the same figure).
次に、反応性イオンエツチング(略称RIB)を行って
ソース電極Sとドレイン電極りを形成する。Next, reactive ion etching (abbreviated as RIB) is performed to form a source electrode S and a drain electrode.
ここで、反応ガスとしてn’a−5i膜のエツチングに
は四弗化炭素(CF4)と酸素(0□)の混合ガスを、
Tiのエツチングには四塩化炭素(CC14)と0!と
の混合ガスを、またITOのエツチングには二弗化塩化
炭素(CCj!zh)と0□との混合ガスを使用した(
以上同図B)。Here, a mixed gas of carbon tetrafluoride (CF4) and oxygen (0□) was used as a reactive gas for etching the n'a-5i film.
For Ti etching, carbon tetrachloride (CC14) and 0! A mixed gas of carbon difluorochloride (CCj!zh) and 0□ was used for etching ITO.
Figure B).
次に、かかる基板上にp−cvo法によりa−Si膜4
を2000人の厚さに、またSiNx膜を3000人の
厚さに形成してゲート絶縁膜5を形成した(以上同図C
)。Next, an a-Si film 4 is formed on the substrate by the p-cvo method.
The gate insulating film 5 was formed by forming a SiNx film to a thickness of 2,000 wafers and a SiNx film to a thickness of 3,000 ni.
).
次に、電子ビーム蒸着法によりNi Crを800人の
厚さに蒸着して電極膜6を形成した後に、化学エツチン
グしてゲート電極Gを形成した(以上同図D)。Next, NiCr was deposited to a thickness of 800 nm by electron beam evaporation to form an electrode film 6, and then chemically etched to form a gate electrode G (see D in the figure).
次に、RIBにより素子間分離を行ってスタガード形T
PTができ上がった(以上同図E)。Next, element isolation is performed using RIB, and staggered T
The PT has been completed (see E in the same figure).
第2図は本発明に係るスタガード形TPTのドレイン電
流(■。)−ゲート電圧(VG)特性図であって、破線
8で示す従来のTPTに較べ、本発明に係る実線9で示
すTPTはオフ電流は二桁程少なく、また立ち上がり特
性も優れている。FIG. 2 is a drain current (■.) vs. gate voltage (VG) characteristic diagram of the staggered TPT according to the present invention, and compared to the conventional TPT indicated by the broken line 8, the TPT according to the present invention indicated by the solid line 9 is The off-state current is about two orders of magnitude lower, and the start-up characteristics are also excellent.
なお、金属膜7としてTi0代わりにCrを用いた場合
も類似の結果を得ることができた。Note that similar results were obtained when Cr was used as the metal film 7 instead of Ti0.
以上記したように本発明の実施によりOFF電流の減少
と昌動度の増加が可能となり、これにより電気的特性が
向上する。As described above, by implementing the present invention, it is possible to reduce the OFF current and increase the degree of mobility, thereby improving the electrical characteristics.
第1図は本発明に係るスタガード形TPTの断面構成図
、
第2図は実施例のスタガード形TPTのIo −Vc特
性図、
第3図は従来のスタガード形TPTの断面構成図、第4
図(A)〜(E)は本発明に係るスタガード形TPTの
製造工程を示す断面図、
である。
図において、
1はガラス基板、 2はITO膜、3はn″a
−5i膜、 4はa−Si膜、5はゲート絶縁膜、
6は電極膜、7は金属膜、
である。
部 5 図FIG. 1 is a cross-sectional configuration diagram of a staggered TPT according to the present invention, FIG. 2 is an Io-Vc characteristic diagram of a staggered TPT according to an embodiment, FIG. 3 is a cross-sectional configuration diagram of a conventional staggered TPT, and FIG.
Figures (A) to (E) are cross-sectional views showing the manufacturing process of the staggered TPT according to the present invention. In the figure, 1 is a glass substrate, 2 is an ITO film, and 3 is n″a
-5i film, 4 is a-Si film, 5 is gate insulating film,
6 is an electrode film, and 7 is a metal film. Part 5 Figure
Claims (2)
極を形成する透明導電膜とn^+非晶質シリコン膜との
間に金属薄膜を介在させてなることを特徴とする薄膜ト
ランジスタ。(1) A thin film transistor characterized in that a metal thin film is interposed between a transparent conductive film and an n^+ amorphous silicon film forming a source electrode and a drain electrode of the thin film transistor.
を特徴とする特許請求の範囲第1項記載の薄膜トランジ
スタ。(2) The thin film transistor according to claim 1, wherein the metal thin film is titanium or chromium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62004662A JPS63172469A (en) | 1987-01-12 | 1987-01-12 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62004662A JPS63172469A (en) | 1987-01-12 | 1987-01-12 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63172469A true JPS63172469A (en) | 1988-07-16 |
Family
ID=11590140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62004662A Pending JPS63172469A (en) | 1987-01-12 | 1987-01-12 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63172469A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4994401A (en) * | 1987-01-16 | 1991-02-19 | Hosiden Electronics Co., Ltd. | Method of making a thin film transistor |
| US5061648A (en) * | 1985-10-04 | 1991-10-29 | Hosiden Electronics Co., Ltd. | Method of fabricating a thin-film transistor |
| WO1994021102A3 (en) * | 1993-03-16 | 1994-11-10 | Thomson Lcd | Direct multilevel thin-film transistor production method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61182266A (en) * | 1985-02-08 | 1986-08-14 | Seiko Instr & Electronics Ltd | Method for manufacturing thin film transistor device |
| JPS61183622A (en) * | 1985-02-08 | 1986-08-16 | Seiko Instr & Electronics Ltd | Thin film transistor device and its manufacture |
| JPS61184881A (en) * | 1985-02-12 | 1986-08-18 | Seiko Instr & Electronics Ltd | Manufacturing method of thin film transistor |
-
1987
- 1987-01-12 JP JP62004662A patent/JPS63172469A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61182266A (en) * | 1985-02-08 | 1986-08-14 | Seiko Instr & Electronics Ltd | Method for manufacturing thin film transistor device |
| JPS61183622A (en) * | 1985-02-08 | 1986-08-16 | Seiko Instr & Electronics Ltd | Thin film transistor device and its manufacture |
| JPS61184881A (en) * | 1985-02-12 | 1986-08-18 | Seiko Instr & Electronics Ltd | Manufacturing method of thin film transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5061648A (en) * | 1985-10-04 | 1991-10-29 | Hosiden Electronics Co., Ltd. | Method of fabricating a thin-film transistor |
| US4994401A (en) * | 1987-01-16 | 1991-02-19 | Hosiden Electronics Co., Ltd. | Method of making a thin film transistor |
| WO1994021102A3 (en) * | 1993-03-16 | 1994-11-10 | Thomson Lcd | Direct multilevel thin-film transistor production method |
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