JPS63163518A - Reference voltage generating circuit - Google Patents

Abstract

PURPOSE:To reduce the area of the chip of a reference voltage generating circuit part by using the channel resistance of a MOS transistor TR. CONSTITUTION:This circuit part includes two bipolar TRs Q1 and Q2 different in emitter size in 1:n, an operational amplifier A1, and N (or P) MOS TRs M3-M5 which have gates connected to a positive power source in case of N channel (connected to a negative power source in case of P channel) but does not include resistances. An output reference voltage is obtained from the connection point between the first constant current circuit M1 and the first MOS resistance M3. That is, potential differences between drains and sources of MOS TRs M3-M5 are approximately equal for the variance of supply voltage or the like. Consequently, they are approximately equal with respect to channel resistances also for the variance of supply voltage or the like, and a reference voltage generating circuit having a constant output voltage is realized. Thus, the chip area is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit in which MOS transistors and bipolar transistors are mixed.

[Conventional technology]

In recent years, with the development of integration technology, miniaturization, reduction in chip area, and lower power consumption have progressed.In order to achieve many of these advantages in the MOS process, MOS transistors are also being used in the analog field. Circuits made up of In the MOS process, a bipolar transistor whose collector is a substrate can be parasitically created, and bandgap reference voltage generation circuits using this bipolar transistor are often used. Conventionally, this type of reference voltage generating circuit has a circuit configuration as shown in FIG. 7. .

Consisting of Shinko. ivI! 7 斥斥弥弘昭性、Paiborado 2nd Jisu
A bipolar transistor Q2 with an emitter size n times larger than Ql, three resistors R1, R2, R3 (R2=R3), and two MOS transistors with the same gate length and gate width W. Consists of Ml; M2 and one operational amplifier A1. MOS transistors M1 and M2 each constitute a constant current circuit.

Assuming that the base-emitter voltage of Ql is VBEI, the base-emitter voltage of Q2 is Vntz, and a bias voltage VB is applied to Ql and Q2, the output terminal OUT
voltage V. UT becomes. Here, by fixing VB and keeping it constant with respect to temperature, it is possible to make VOUT almost constant with respect to temperature. Also, since the power supply voltage term is not included in the equation, it is relatively stable against fluctuations in the source voltage.

[Problem that the invention seeks to solve]

However, the conventional reference voltage generation circuit described above requires a fairly large layout area because it uses a resistor, which is a passive element. In particular, in order to increase the speed of integrated circuits, the sheet resistance of polysilicon and diffused resistors used as resistors is currently being reduced, and in order to obtain the required resistance value, the area becomes large. There were drawbacks.

In order to further reduce power consumption, it is necessary to increase I (, 1 to 3), which has the disadvantage that the chip area increases in inverse proportion to the reduction in power. The reference voltage generation circuit of the present invention includes two bipolar transistors with different emitter sizes of 1:n, an operational amplifier and two MOS transistors of the same size for a constant current circuit, and an N-channel gate. In case of positive power supply,
In the case of P channel, MOS connected to the negative power supply side)? It has a characteristic that the chip area can be reduced compared to the resistor.

The reference voltage generation circuit of the present invention includes a first bipolar transistor whose collector is connected to a first potential, and a collector and a base of which are connected to the collector and base of the first bipolar transistor, respectively, and whose collector is connected to the first potential. a second piezoelectric transistor connected to the first pieborad 2 transistor and having an emitter size substantially larger than the emitter size of the first pieborad transistor;
a first constant current circuit composed of a bipolar transistor and a MOS transistor, one end of which is connected to a second potential;
a second constant current circuit composed of a MOS transistor and having one end connected to the second potential; and a second constant current circuit composed of a MOS transistor between the emitter of the first bipolar transistor and the other end of the first constant current circuit. The first MOS connected to
a second M configured with a resistor and a MOS transistor and having one end connected to the emitter of the second bipolar transistor;
The second M is composed of an OS resistor and a MOS transistor.
A third MOS resistor connected between the other end of the OS resistor and the other end of the second constant current circuit, and a connection point between the first MOS resistor and the first constant current circuit are input in positive phase. The connection point between the first MOS resistor and the third MOS resistor is used as an inverse phase input, and the output is the output from the first MOS resistor. an operational amplifier serving as a control input of the second constant current circuit, the first constant current circuit and the first M
It is characterized in that the output reference voltage is obtained from the connection point with the OS resistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1+a+ is a circuit diagram showing an embodiment of the present invention.

Two NPN bipolar transistors Q1 and Q2, whose bases are commonly connected and to which a bias voltage VB is applied, are:
The emitter sizes of Ql and Q2 are in a relationship of 〇 (n>1), the collectors of Ql and Q2 are commonly connected and a positive power supply VDD is applied, and the emitters of Ql and Q2 are each connected to an N-channel MOS transistor M5. ．． Connect to the drain of M4.

MS, M40ance is N channel MOS transistor M
1 and the drain of MS, and the source of MS is connected to M2
The drains of Ml and M2 are connected to the negative power supply (GND). The sizes of M1 and M2 are the same. The positive phase input of operational amplifier A1 is connected to the source of MS, the negative phase input is connected to the source of M4, and the operational amplifier output is fed back to a portion where the gates of M1 and M2 are commonly connected. M.S., M.S.
4. All MS gates are connected to the positive power supply VDD. M
The OS transistors M1 and M2 each constitute a constant current circuit. M4. Among the MSs, M4 and MS have the same gate length Ll and gate width W1, and the gate length of MS is L2.
Let the r gate width be W2. The channel resistance of a MOS transistor has a relationship between gate length and gate width W as shown in the following equation.

R=W ・・・・・・・・・・・・・・・・・・・・・・・・
(2) When the voltage at the OUT terminal is calculated in consideration of the Janel resistance, the relationship obtained by substituting it into (1) is obtained. In this circuit configuration, MS, M4゜MS
The potential difference between the drain and the source remains almost constant even with variations in the power supply voltage. Therefore, the channel resistance “A r
``H'' is almost constant against power supply voltage fluctuations, etc., and a reference voltage generation circuit with a constant output voltage can be realized.In terms of chip area, the configuration using the resistor shown in Figure 3 requires =R3=5Ω.

To achieve R1=650Ω, the sheet resistance value is set to 30
Ω, the resistance width is 6 μm for accuracy, and the interval between the resistors is 3 μm on one side, the total area occupied by the resistors is about 25,600 μfF12.

-Gal 2. R3 and R1 are each MOS)? , J dista M4. M5. If replaced with M3, M4 and M5o W
/L30 /Jfn/ 4 /JfFl, MS
With W/L=230 μm/4μ groove, the same characteristics as #1 can be obtained, and the area at that time is about 7350 μm2, which can be reduced to about one-fourth of the area when using a resistor. The power supply voltage fluctuation characteristics at this time are shown in FIG. 1(b). Power supply voltage 2
The fluctuation is 1/50th of the fluctuation in (2) and is stable.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. When integrated into a circuit, if a P-type substrate is used, a PNP bipolar transistor with a common collector can be easily realized using a MOS process. Ql is diode-connected and the base of Q3 is connected to the emitter of Ql. Further, Q2 is a diode-connected bipolar transistor with the emitter size of Ql multiplied by n (n>1), and Q4 is also a bipolar transistor with the emitter size of Ql multiplied by n, and the emitter of Q2 and the base of Ql are connected. The positive phase input of operational amplifier A1 is connected to the emitter of Q3, and the negative phase input of operational amplifier A1 is connected to the drain of MS whose source is connected to the emitter of Q3. By connecting the pievora transistors in series like Ql and Q3, the voltages of the positive-phase and negative-phase inputs of the operational amplifier can be set high, increasing the gain of the operational amplifier itself and operating more stably. P-channel MOS transistors M1, M2 . M6. M7 is a bipolar transistor Q
l, Q2. Q3. For constant current drive of Q4, Pcha 4
hM08t:Yinji, xYM8. M9. MIO, Mll
.

Ml2. Ml3 and N-channel MOS transistor M14
is a startup circuit when the power is turned on. M
S and M4. 9. MS has a P-channel MOS transistor as a channel resistance; The voltage at the output terminal from the source side of MS can be set by the ratio of the channel resistances of MS and M4.

The transistor sizes of M4 and MS are the same, and Ml and M
2. If the sizes of MS and M7 are the same, the voltage between Ql and Q3 is VBKI, and the voltage between the base and emitter of Q2 and Q4 is VRE2, then (VRE: VBEI - VsE2RA: M
The channel resistance of S is kLB2 the channel resistance of M4, and a band cap reference voltage generation circuit can be constructed.

If MS, M4. If a resistor, which is a normal passive element, is used for the MS, the total resistance will be about 472 ohms9, which will require a huge area. If we estimate the resistance of Ω for 4Z7 with a sheet resistance of 30Ω, a resistance width of 6μ, and a resistance interval of 3μ, the opening size will be approximately 320μm. On the other hand, MS, M4. M.S.
By using the channel resistance of the MOS transistor, the MS
W/L=60μm/4 μm, W/L of M4=M5:
10μfF115/! If jff1 is about 45μ, it can be realized in 10, and the area will be about 1/7th.

〔Effect of the invention〕

As explained above, the present invention is applicable to MS, M4. MS MO
By using the channel resistance of the S transistor,
The chip area of the reference voltage generation circuit section can be reduced, and the larger the resistance value used, the more the chip area can be reduced.

[Brief explanation of the drawing]

Figure 1 (aJ is a circuit diagram showing one embodiment of the present invention, Figure 1 (bJ is a characteristic diagram of the power supply voltage of Figure 1), Figure 2 is a circuit diagram showing another embodiment of the present invention. , FIG. 3 is a circuit diagram showing a conventionally used reference voltage generation circuit. Ql, Q3...bipolar transistors, Q2, Q4
...Emitter size of Ql and Q3 n times (n>1)
Bipolar transistor, MS, M4, MS...
MOS transistor, Ml, M2. M6~M14...
MOS transistor, AI... operational amplifier% VDD
...Power supply voltage, OUT...Output terminal. Gi 2 Menka 3 Diagram

Claims (1)

[Claims] 1. A first bipolar transistor having a collector connected to a first potential; a collector and a base connected to the collector and base of the first bipolar transistor, respectively, and a collector connected to the first potential; a second bipolar transistor connected and having an emitter size substantially larger than the emitter size of the first bipolar transistor, and a first constant current circuit configured with a MOS transistor and having one end connected to a second potential; a second constant current circuit made up of a MOS transistor and having one end connected to the second potential; and a second constant current circuit made up of a MOS transistor between the emitter of the first bipolar transistor and the other end of the first constant current circuit. a first MOS resistor connected to the emitter of the second bipolar transistor; a second MOS resistor composed of a MOS transistor and having one end connected to the emitter of the second bipolar transistor; Said second
A third MOS resistor connected between the other end of the constant current circuit and a connection point between the first MOS resistor and the first constant current circuit are used as positive phase inputs. 3 MOS
an operational amplifier whose output is a control input of the first and second constant current circuits, the connection point of the resistor being a negative phase input, and the operational amplifier having a connection point of the first constant current circuit and the first MOS resistor; A reference voltage generation circuit characterized in that an output reference voltage is obtained. 2. MOS that constitutes at least two or more constant current circuits
transistor and at least two different emitter sizes
It is equipped with two or more bipolar transistors, one operational amplifier, and three MOS transistors configured with MOS resistors. A MOS transistor configured as a series-connected MOS resistor is connected, and a MOS transistor configured as a single MOS resistor with a bias voltage applied to the emitter and gate of a bipolar transistor with a small emitter size is connected. A reference voltage generation circuit characterized in that each of the connected MOS transistors and one MOS transistor are connected to a MOS transistor forming a constant current circuit.