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JPS63151019A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63151019A
JPS63151019A JP61297709A JP29770986A JPS63151019A JP S63151019 A JPS63151019 A JP S63151019A JP 61297709 A JP61297709 A JP 61297709A JP 29770986 A JP29770986 A JP 29770986A JP S63151019 A JPS63151019 A JP S63151019A
Authority
JP
Japan
Prior art keywords
film
active region
pattern
exposure mask
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61297709A
Other languages
Japanese (ja)
Inventor
Kouki Mutou
耕喜 武藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP61297709A priority Critical patent/JPS63151019A/en
Publication of JPS63151019A publication Critical patent/JPS63151019A/en
Pending legal-status Critical Current

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

PURPOSE:To obtain an accurate active region as designed, by providing a protruding part at each outer corner part, using an exposure mask having an active region pattern, in which each inner corner part has a slant side, and patterning an oxidation mask layer. CONSTITUTION:On a semiconductor substrate 31, a pad SiO2 film 32 and an Si3N4 film 33 are laminated and formed. This part is patterned by photolithography using an exposure mask 41. Only an active region forming area is made to remain. The exposure mask 41 is formed so that protruding parts 43 are formed at the outer corner parts of an active-region forming pattern 42 and the inner corner parts become slant sides 44. Therefore, Si3N4 film patterns 33a are formed in an L shape or a T shape, which has the protruding parts 34 and slant sides 35. With the Si3N4 film patterns 33a as masks, the device is oxidized in a steam atmosphere. Thus a field oxide film 36, in which right angles are maintained at the corners of the Si3N4 film patterns 33a, is formed.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は半導体装置の製造方法に関し、特に、半導体
基板面をLOGO8(Local 0xidation
 ofSilicon )  法にてフィールド領域と
アクティブ領域に分離する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular, the present invention relates to a method for manufacturing a semiconductor device.
The present invention relates to a method of separating a field region and an active region using a method (ofSilicon).

(従来の技術) 従来の上記分離方法を第3図を参照して説明する。ただ
し、第3図では、左側に断面図、右側に平面図を示す。
(Prior Art) The conventional separation method described above will be explained with reference to FIG. However, in FIG. 3, a sectional view is shown on the left side, and a plan view is shown on the right side.

まず、第3図(a)に示すように、半導体基板1上にパ
ッドS10.膜2とSi3N4膜3を重ねて形成する。
First, as shown in FIG. 3(a), pads S10. The film 2 and the Si3N4 film 3 are formed in an overlapping manner.

次に、その55N4膜3とパッドSin、膜2を、−例
として第4図に示す露光用マスク11を用いたホトリソ
グラフィ忙よシ第3図(b)に示すようにパターン化し
、アクティグ領域形成予定領域にのみ残す。ここで、第
4図の露光用マスク11においては、L形およびT形に
アクティグ領域/4ターン12が形成されており、この
アクティグ領域/9ターン12と同一形状にSi3N4
膜3およびノ々ツドSin。
Next, the 55N4 film 3, pad Sin, and film 2 are patterned by photolithography using the exposure mask 11 shown in FIG. 4 as an example, as shown in FIG. 3(b). Leave it only in the area where it will be formed. Here, in the exposure mask 11 shown in FIG. 4, L-shaped and T-shaped active regions/4 turns 12 are formed, and Si3N4 is formed in the same shape as the active regions/9 turns 12.
Membrane 3 and nodes Sin.

膜2が残る。Membrane 2 remains.

次に、残存5isN4膜3をマスクとして半導体基板l
を1000℃、水蒸気雰囲気中で2〜3時間酸化するこ
とにより、第3図(c)に示すように、半導体基板1の
Si3N4膜3が存在しない部分に厚いフィールド酸化
膜4を形成する。
Next, using the remaining 5isN4 film 3 as a mask, the semiconductor substrate l is
By oxidizing it at 1000 DEG C. in a steam atmosphere for 2 to 3 hours, a thick field oxide film 4 is formed in the portion of the semiconductor substrate 1 where the Si3N4 film 3 is not present, as shown in FIG. 3(c).

その後、Si、N、膜3を170℃程度のリン酸で、ま
た、その下のパッドSi0g膜2をHF系の液で除去す
ることによ)、それらで覆われていた基板面を第3図(
d)に示すように露出させる。この基板面が露出した部
分がアクティブ領域5、周辺のフィールド酸化膜4で覆
われている部分がフィールド領域6である。アクティブ
領域5は、ここでは、第4図の露光用マスク11のアク
ティグ領域パターン12および第3図(b) + ((
りの811N4膜3パターンと同様にL形およびT形に
得られる。
After that, by removing the Si, N, and film 3 with phosphoric acid at about 170°C and the pad Si0g film 2 underneath with an HF-based solution, the substrate surface covered with them is removed with a third layer. figure(
Expose as shown in d). The exposed portion of the substrate surface is the active region 5, and the peripheral portion covered with the field oxide film 4 is the field region 6. The active region 5 is here formed by the active region pattern 12 of the exposure mask 11 in FIG. 4 and FIG. 3(b) + ((
Similar to the three 811N4 film patterns, L-shape and T-shape are obtained.

(発明が解決しようとする問題点) しかしながら、上記のような従来の方法では、フィール
ド酸化flll!4の酸化形成工程において、5iaN
4膜3/#ターンの角へのストレスの集中によシ、該S
i、N、膜3パターンの外角が丸まったり(第3図(e
)の右側平面図内の内部分)、内角に切れ込み21が生
じたシした。そして、その結果、アクティブ領域50角
部においては、第3図(d)の右側平面図の円内で示す
ようにフィールド酸化膜4がアクティブ領域5内に入シ
込み、アクティグ領域5の面積の減少が生じた。また、
甚しい場合は、アクティブ領域5内に内角部で喰い込ん
だフィールド酸化膜4により該アクティブ領域5が切断
されてしまった。
(Problems to be Solved by the Invention) However, in the conventional method as described above, field oxidation is full! In the oxidation formation step of step 4, 5iaN
4 Film 3/# Due to the concentration of stress on the corner of the turn, the S
i, N, the outer corners of the 3 film patterns are rounded (Figure 3 (e)
), a notch 21 was formed at the inner corner. As a result, at the corner of the active region 50, the field oxide film 4 intrudes into the active region 5 as shown by the circle in the right plan view of FIG. A decrease occurred. Also,
In a severe case, the active region 5 is cut off by the field oxide film 4 which has dug into the active region 5 at an inner corner.

この発明は上記の点に鑑みなされたもので、その目的は
、LOGO8工程において、耐酸化マスク層パターンの
角の丸ま9や切れ込みによるアクティブ領域の面積の減
少や切断を防止し、設計通りの正確なアクティブ領域を
得ることのできる半導体装置の製造方法を提供すること
にある。
This invention was made in view of the above points, and its purpose is to prevent the area of the active region from being reduced or cut due to rounded corners 9 or cuts in the oxidation-resistant mask layer pattern in the LOGO8 process, and to prevent the area of the active region from being cut as designed. An object of the present invention is to provide a method for manufacturing a semiconductor device that can obtain an accurate active area.

(問題点を解決するための手段) この発明は、LOCO8工程において、ホ) IJング
ラフイによる耐酸化マスク層の74ターン化を次のよう
な露光用マスクを用いて行う。その露光用マスクは、外
側の角部に突出し部を有するとともに、内側の角部を斜
辺としたアクティブ領域パターンを有する。
(Means for Solving the Problems) In the present invention, in the LOCO8 process, e) 74 turns of the oxidation-resistant mask layer by IJ graphing are performed using the following exposure mask. The exposure mask has a protrusion at the outer corner and an active region pattern with the inner corner as the hypotenuse.

(作用) 上記のようなアクティグ領域ノ々ターンを有する露光用
マスクを用いて耐酸化マスク層のノ9ターン化を行うと
、得られる耐酸化マスク層ノJ?ターンは、上記露光用
マスクのアクティブ領域パターンと同様に、例えば第2
図(b)の右側の平面図に示すように、外側の角部に突
出し部を有するとともに、内側の角部が斜辺となったノ
々ターンとなる。し九がって、次に、その耐酸化マスク
層/4ターンをマスクとしてフィールド酸化を行った時
、該耐酸化マスク層パターンの角にストレスの集中が生
じるが、該ストレスの集中によシ生じる症状は、前記突
出しと斜辺によシ、角の丸iシや切り込みの発生に至ら
ず、第2図(C)右側の平面図に示すように角が直角に
なるに留lる。そもそも、耐酸化マスク層Aターンの角
は直角を維持したいのである。上記のようなこの発明に
おいては、フィールド酸化時のストレスの集中による変
形により、耐酸化マスク層パターンの角は、直角という
所望の形状となるのであシ、その結果、フィールド酸化
膜の入り込みのない角が直角の所望形状の設計通りのア
クティグ領域が得られるようになる。
(Function) When the oxidation-resistant mask layer is made into 9-turns using the exposure mask having the above-mentioned active area turns, the resulting oxidation-resistant mask layer No.J? The turn is similar to the active area pattern of the exposure mask, for example, the second
As shown in the plan view on the right side of Figure (b), the outer corner has a protruding portion and the inner corner is the oblique side, forming a notch turn. Then, when field oxidation is performed using the oxidation-resistant mask layer/4 turns as a mask, stress concentration occurs at the corners of the oxidation-resistant mask layer pattern; The symptoms that occur are due to the above-mentioned protrusion and oblique side, and the corners do not become rounded or notched, but only the corners become right angles, as shown in the plan view on the right side of FIG. 2(C). In the first place, it is desired to maintain the angle of the oxidation-resistant mask layer A turn at a right angle. In this invention as described above, the corners of the oxidation-resistant mask layer pattern have the desired shape of right angles due to deformation due to concentration of stress during field oxidation, and as a result, there is no intrusion of the field oxide film. It becomes possible to obtain an active area having a desired shape with right-angled corners as designed.

(実施例) 以下この発明の一実施例を図面を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to the drawings.

第2図(a)ないしくd)はこの発明の一実施例を工程
順に示し、左側は断面図、右側は平面図である。
FIGS. 2(a) to 2d) show an embodiment of the present invention in the order of steps, with the left side being a sectional view and the right side being a plan view.

この第2図の(a)に示すように、まず、半導体基板3
1上にパッド5i01膜32とSi、N、膜33を重ね
て形成する。
As shown in FIG. 2(a), first, the semiconductor substrate 3
A pad 5i01 film 32 and a Si, N, film 33 are formed on top of each other.

次に、その813N4膜33とパッドsio、膜32を
第1図に示す露光用マスク41を用いたホトリングラフ
ィによシ第2図(b)に示すように・ぐターン化し、ア
クティブ領域形成予定領域にのみ残す。ここで、第1図
の露光用マスク41においてFiL形およびT形にアク
ティブ領域パターン42が形成されるが、更に該アクテ
ィブ領域・ぐターン42は、外側の角部に突出し部43
を有するとともに、内側の角部が斜辺44となるように
形成される。したがって、このような露光用マスク41
を用いて5isN+膜33とパッド5i01膜32のホ
トリングラフイ(・々ターン化)を行うと、得られるS
t、N4膜パターン33aは、上記露光用マスク41の
アクティブ領域ノ々ターン42と同様に、第2図(b)
の右側の平面図に示すように、外側の角部に突出し部3
4を有するとともに、内側の角部が斜辺35となったL
形あるいはT形に形成される。ただし、突出し部34と
斜辺35は若干丸まる。また、この5isNa膜パター
ン33aと同一形状に、その下のパッドSin、膜パタ
ーン32aも得られる。なお、このSi、N、膜33と
ノ9ツドSiO鵞膜32のパターン化(フォトリソグラ
フィ)をポジ型レジストを用いて行うとすると、前記露
光用マスク41のアクティブ領域パターン42は、Cr
によシネ透明部として形成される。
Next, the 813N4 film 33, the pad sio, and the film 32 are patterned by photolithography using the exposure mask 41 shown in FIG. 1 to form an active region as shown in FIG. 2(b). Leave it only in the scheduled area. Here, an active area pattern 42 is formed in a FiL shape and a T shape in the exposure mask 41 shown in FIG.
and is formed so that the inner corner portion becomes the oblique side 44. Therefore, such an exposure mask 41
When the 5isN+ film 33 and the pad 5i01 film 32 are photolithographically formed using
The N4 film pattern 33a is similar to the active area no-turns 42 of the exposure mask 41 as shown in FIG. 2(b).
As shown in the right side plan view, there is a protrusion 3 on the outer corner.
4, and the inner corner is the hypotenuse 35.
It is formed into a T-shape or T-shape. However, the protruding portion 34 and the oblique side 35 are slightly rounded. Further, the pad Sin and the film pattern 32a below the 5isNa film pattern 33a are also obtained in the same shape as the 5isNa film pattern 33a. Note that if the patterning (photolithography) of the Si, N, film 33 and the 9-SiO film 32 is carried out using a positive resist, the active area pattern 42 of the exposure mask 41 is made of Cr.
It is formed as a transparent part.

しかる後、818N4膜パターン33aをマスクとして
半導体基板31を1000℃、水蒸気雰囲気中で2時間
酸化することにより、第2図(c)に示すように、半導
体基板31のSi3N4膜パターン33aが存在しない
部分に厚いフィールド酸化膜36を形成する。
Thereafter, the semiconductor substrate 31 is oxidized at 1000° C. for 2 hours in a steam atmosphere using the 818N4 film pattern 33a as a mask, so that the Si3N4 film pattern 33a on the semiconductor substrate 31 is no longer present, as shown in FIG. 2(c). A thick field oxide film 36 is formed in the portion.

この時、 5IJN4膜パターン33aの角にストレス
の集中が生じ、従来は外側の角が丸まったり、内側の角
に切り込みが生じたが、上記St、N4膜ノ9ターン3
3aでは、外側の角部に突出し部34を有するとともに
、内側の角部が斜辺35となっていることによシ、角の
丸まシや切シ込みの発生には至らず、第2図(c)の右
側の平面図に示すように角が直角になる忙留まる。換言
すれば、所望の形状である直角が5ilN、膜パターン
33aの角に維持されたことになる。
At this time, stress concentration occurs at the corners of the 5IJN4 film pattern 33a, and conventionally the outer corners were rounded and the inner corners were notched, but in the above-mentioned St, N4 film pattern 9 turn 3
3a has a protrusion 34 on the outside corner and the hypotenuse 35 on the inside corner, so no rounded corners or notches occur, and as shown in FIG. As shown in the plan view on the right side of (c), the corners are at right angles. In other words, the desired shape of the right angle is maintained at the corner of the film pattern 33a by 5ilN.

しかる後、  St、N、膜パターン33&とその下の
パッドS10.膜パターン32mをリン酸とHF系の液
で除去することにより、それらで覆われていた基板面を
第2図(d)に示すように露出させ、該基板露出部分で
あるアクティブ領域37を得る。このアクティブ領域3
7は、前記フィールド酸化時、5isN4膜ノリーン3
3aの角が直角に維持されたことにより、対応して角は
直角となり、フィールド酸化膜36の入り込みはなく、
設計通りの形状および面積で得られる。
After that, St, N, film pattern 33& and the pad S10 . By removing the film pattern 32m with phosphoric acid and HF-based liquid, the substrate surface covered with them is exposed as shown in FIG. 2(d), and an active region 37, which is the exposed portion of the substrate, is obtained. . This active area 3
7 is the 5isN4 film Noreen 3 during the field oxidation.
Since the corner of 3a is maintained at a right angle, the corner becomes a corresponding right angle, and the field oxide film 36 does not enter.
Obtained in the designed shape and area.

(発明の効果) 以上詳述したように、この発明によれば、外側の角部に
突出し部を有するとともに、内側の角部を斜辺゛とした
アクティブ領域・々ターンを有する露光用マスクを用い
て耐酸化マスク層パターンを形成するようにしたので、
フィールド酸化時、該マスク層ツクターンの外角の丸ま
シや内角での切り込みの発生を防止し、角を直角に維持
でき、その結果、角部におけるアクティグ領域へのフィ
ールド酸化膜の入や込みを防止できるので、アクティブ
領域の面積の減少や切断を防止でき、設計通りの正確な
アクティブ領域を得ることができる。この発明の方法は
、特に微細なアクティブ領域ノぞターンを形成する場合
に有利である。
(Effects of the Invention) As described in detail above, according to the present invention, an exposure mask is used which has a protrusion at the outer corner and has an active area/turn with the inner corner as the hypotenuse. Since the oxidation-resistant mask layer pattern was formed using
During field oxidation, it is possible to prevent rounding of the outer corners of the mask layer and notches at the inner corners, and to maintain the corners at right angles.As a result, the field oxide film is prevented from penetrating into the active area at the corners. Since this can be prevented, reduction in the area of the active region or cutting can be prevented, and an accurate active region as designed can be obtained. The method of the present invention is particularly advantageous when forming fine active region nozzles.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はこの発明の半導体装置の製造方法
の一実施例を示し、第1図は露光用マスクの平面図、第
2図は製造方法を工程順に示す断面図および平面図、第
3図は従来の方法を工程順に示す断面図および平面図、
第4図は従来の方法で使用される露光用マスクの平面図
である。 31・・・半導体基板、32・・・ノ(ラド5i02膜
、32a−−−IllllラドSi0パターン、33 
・5t8N4膜、33a・・・SimN+膜・々ターン
、34・・・突出し部、35・・・斜辺、36・・・フ
ィールド酸化膜、37・・・アクティブ領域、41・・
・露光用マスク、42・・・アクティブ領域パターン、
43・・・突出し部、44・・・斜辺。 本全1デー¥施イ列τのf番y用マスク第1図
1 and 2 show an embodiment of the method for manufacturing a semiconductor device of the present invention, FIG. 1 is a plan view of an exposure mask, FIG. 2 is a sectional view and a plan view showing the manufacturing method in order of steps, FIG. 3 is a sectional view and a plan view showing the conventional method in the order of steps;
FIG. 4 is a plan view of an exposure mask used in the conventional method. 31... Semiconductor substrate, 32... (RAD 5i02 film, 32a---Illll Rad Si0 pattern, 33
- 5t8N4 film, 33a...SimN+ film/turn, 34...Protrusion, 35...Octenuse, 36...Field oxide film, 37...Active region, 41...
- Exposure mask, 42... active area pattern,
43... Protruding part, 44... Hypotenuse. Figure 1: Mask for number f and y of the entire book 1 day ¥ application column τ

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に耐酸化マスク層を形成し、この耐酸化マ
スク層をフォトリソグラフィによりパターン化し、アク
テイブ領域形成予定領域にのみ残し、その耐酸化マスク
層パターンをマスクとして前記半導体基板を酸化するこ
とにより半導体基板面をフィールド領域とアクティブ領
域に分離するようにした半導体装置の製造方法において
、外側の角部に突出し部を有するとともに、内側の角部
を斜辺としたアクテイブ領域パターンを有する露光用マ
スクにて前記耐酸化マスク層のフォトリソグラフィを行
うことを特徴とする半導体装置の製造方法。
By forming an oxidation-resistant mask layer on a semiconductor substrate, patterning this oxidation-resistant mask layer by photolithography, leaving it only in the area where the active region is to be formed, and oxidizing the semiconductor substrate using the oxidation-resistant mask layer pattern as a mask. In a method of manufacturing a semiconductor device in which a semiconductor substrate surface is separated into a field region and an active region, an exposure mask having a protrusion at an outer corner and an active region pattern with an inner corner as a hypotenuse is provided. A method of manufacturing a semiconductor device, comprising performing photolithography on the oxidation-resistant mask layer.
JP61297709A 1986-12-16 1986-12-16 Manufacture of semiconductor device Pending JPS63151019A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61297709A JPS63151019A (en) 1986-12-16 1986-12-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61297709A JPS63151019A (en) 1986-12-16 1986-12-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63151019A true JPS63151019A (en) 1988-06-23

Family

ID=17850147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61297709A Pending JPS63151019A (en) 1986-12-16 1986-12-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63151019A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63186450A (en) * 1987-01-29 1988-08-02 Sony Corp Selective thermal oxidation
JPH08213314A (en) * 1995-11-21 1996-08-20 Hitachi Ltd Method of manufacturing integrated circuit device
US5830606A (en) * 1988-11-22 1998-11-03 Hitachi, Ltd. Mask for manufacturing semiconductor device and method of manufacture thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63186450A (en) * 1987-01-29 1988-08-02 Sony Corp Selective thermal oxidation
US5830606A (en) * 1988-11-22 1998-11-03 Hitachi, Ltd. Mask for manufacturing semiconductor device and method of manufacture thereof
US5948574A (en) * 1988-11-22 1999-09-07 Hitachi, Ltd. Mask for manufacturing semiconductor device and method of manufacture thereof
US6106981A (en) * 1988-11-22 2000-08-22 Hitachi, Ltd. Mask for manufacturing semiconductor device and method of manufacture thereof
US6420075B1 (en) 1988-11-22 2002-07-16 Hitachi, Ltd. Mask for manufacturing semiconductor device and method of manufacture thereof
US6458497B2 (en) 1988-11-22 2002-10-01 Hitachi, Ltd. Mask for manufacturing semiconductor device and method of manufacture thereof
US6548213B2 (en) 1988-11-22 2003-04-15 Hitachi, Ltd. Mask for manufacturing semiconductor device and method of manufacture thereof
US6733933B2 (en) 1988-11-22 2004-05-11 Renesas Technology Corporation Mask for manufacturing semiconductor device and method of manufacture thereof
US7008736B2 (en) 1988-11-22 2006-03-07 Renesas Technology Corp. Semiconductor integrated circuit device fabrication method using a mask having a phase shifting film covering region and an opening region
JPH08213314A (en) * 1995-11-21 1996-08-20 Hitachi Ltd Method of manufacturing integrated circuit device

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