JPS63155188A - Display timing generation system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] When displaying image data using a control method in which a plurality of lamps, etc. provided on a plane perform gradation in a time-division manner, it is necessary to use a time-division control method corresponding to luminance data. An oscillation circuit was required to generate a display timing signal for lighting the lamp. The present invention separates a data signal and a clock signal from a modulation signal, determines the period of the clock signal, and generates a display timing signal. oscillation circuit becomes unnecessary.

[Industrial application field]

The present invention relates to a display device, and more particularly to a display timing generation method for a device that performs time-division gradation control.

[Traditional technique]

2. Description of the Related Art Display devices that use lamps such as FL tubes and perform gradation display by controlling the driving time of the lamps are often used as large-sized display devices.

The driving time of the lamp described above corresponds to the luminance data. For example, by turning on the lamps all at once and turning them off after a display timing signal indicating the number of brightness data, the brightness corresponding to the brightness data, that is, the gradation of the lamps, etc., is obtained.

Large display devices are rarely used indoors and are generally used outdoors. In this case, the luminance data, or image data, may be transferred from a device installed in another remote room with good environmental conditions, and a modulation signal modulated by a modulator is added, for example.

The large display device demodulates this modulation signal and stores it in a memory etc., generates the display timing signal mentioned above, and
The lamp is controlled by a gradation control section to turn on the lamp in accordance with the data stored in the memory, that is, the luminance data.

[Problem that the invention sought to solve]

As mentioned above, large display devices are often used outdoors, where the environmental conditions are poor and changes in temperature and the like are particularly noticeable. Generally, the gradation control section mentioned above is equipped with an oscillator to generate a display timing signal, which requires a large-scale circuit to ensure stable operation even under the above-mentioned environmental conditions. . Furthermore, synchronization with data obtained from the demodulator is also required, resulting in an even more complex circuit.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the conventional art, it is an object of the present invention to provide a display timing generation method that does not require an oscillator or the like for generating display timing signals and generates display timing signals using an idle circuit.

[Means for solving problems]

FIG. 1 is a block diagram of the present invention. 1 is a demodulation circuit that detects a clock signal and a data signal from a modulation signal that is intermittently applied in specific data units, and outputs it; 2 is a demodulation circuit that determines the period of the clock that is applied from the demodulation circuit 1, and displays it when the period exceeds a specific time. A delay circuit 3 generates a clock as a timing and outputs it as a display timing signal, and 3 is a display device that is synchronized with the display timing signal and drives a plurality of display elements in relation to the display data.

[For production]

The modulated signal applied to the demodulation circuit 1 has data intermittently, and the demodulation circuit 1 demodulates the modulated signal that intermittently has data. This demodulation circuit obtains a data signal and a clock signal. Since the modulation signal has data intermittently, the data signal and clock signal obtained from the demodulation circuit 1 are also intermittently. The clock signal is applied to a delay circuit 2, and the delay circuit 2 determines the point in time when data is interrupted from the period of the clock signal, and outputs it to the display device as a display timing signal. The display device has a display element such as a lamp, and drives the lamp in synchronization with a display timing signal in response to the data signal described above. In this system, the display timing signal is generated from the intermittent lock signal of the demodulation circuit 1, so that the clock signal used to capture the data signal and the display timing signal are always in synchronization.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention. In FIG. 2, it consists of an image data processing section 4, an optical communication path 5, and a gradation control section 6. The image data processing section 4 is a circuit that divides image data applied from an image data generation circuit (not shown) into blocks, modulates the data, and sends the data to the gradation control section 6 via the optical communication path 5.

The oscillation circuit 9 included in the image data processing section 4 has a crystal resonator 8, and the resonant frequency (
It oscillates at 50MHz). Then, the oscillation output, that is, the 50 MHz clock is applied to the F2F modulation circuit 7 and the blanking timing generation section 10. The blanking timing generation unit 10 is a circuit that generates timing for transmitting data in units of blocks in synchronization with the clock applied from the oscillation circuit 9. For example, the present invention is 200X
The data is divided into blocks of 8 bits (1,600 kbit), and the blanking timing creation section 10 determines the blocks and provides a specific blanking period between the blocks. The display elements of the display device 11, which will be described later, are horizontal 112, vertical 152, and have three colors: red, green, and blue.
Furthermore, when driving each display element (for example, a lamp) at 256 levels and 371 (8 bits) with a display of 60 fields per second, ll2XI52 X 3 X60X per second
8-bit (24,51456 Mbit) data is transferred. In other words, the F2F modulation circuit 7 receives 24 pulses per second.
．． 51,456 Mbit of data is added and output to the optical transmitter 13 as a modulated signal.

Since the F2F modulation circuit in the embodiment of the present invention transmits data using 50 MHz clock F2F modulation, the maximum data that can be transmitted is 25 Mbit/sec.

The data to be sent in 1 second is 24.51456.
Mbit, so in the embodiment of the present invention 200X8b
A blanking period in which no data is transferred is provided between each book consisting of .IT.

FIG. 3 is a timing chart showing the blocks 81 to 8256 and the blanking time. Block 8
Blocks 1 to B255 are composed of 200 x 8 bit data, and block 8256 is composed of 72 x 8 bit data. After each block B1-8255, there is a blanking period of time td. This period is approximately 1.1 μ5 ec (=td). After block 8256, there is a blanking period of time tL. This period LL is approximately 42 μsec. Each block 8
The total time of 1 to B255 and the subsequent blanking period is 40 nsec x 8 x 200 + 1.1 μse
c': 65.1 μsec. Also block 825
The total time of G and the subsequent blanking period is 40 ns.
ec x 8 X72+42μ5ec-65,1. That is, the total time of each block 81 to 8256 and the subsequent blanking period is 65.1 u sec.
It becomes. The total focus of each block is image 1
Matches the number of data that makes up the field. Each field is exactly 1/60 second.

A circuit (not shown) that generates an image signal and an F2F modulation circuit 7
For example, the F2F modulation circuit performs handshaking to send and receive data, and when a blanking signal is applied from the blanking timing generation section 10, the F2F modulation circuit stops transmitting that data, and also sends an image signal to the circuit that generates the image signal. The handshake is also stopped. As a result, modulated signals consisting of blocks and blanking periods are sequentially applied to the optical transmitter 13.

The optical transmitter 13 is a circuit that converts an electrical signal into light, and the above-mentioned data and optical data corresponding to the blanking period are transmitted via the optical communication path 5 to the optical receiver (R
) join 12.

The optical receiver 12 is a circuit that converts an optical signal into an electrical signal, and this circuit applies a signal similar to the signal applied to the optical transmitter from the F2F modulation circuit 7 to the F2F demodulation circuit 14. The F2F demodulation circuit 14 outputs the data applied to the F2F modulation circuit as serial data. In addition to the received serial data, the F2F demodulation circuit I4 also outputs a clock for loading this serial data into a memory or the like.

In addition to the display element, the display device 11 includes a circuit that stores image data to be displayed on the display element, a drive circuit that drives the display element with luminance data included in the image data, and the like.

The display element is, for example, an FL tube, and the drive circuit controls the driving time of the FL tube in accordance with the luminance data. Conventionally, the drive time of the FL tube is controlled using a timing signal generated by a clock oscillator, but in the present invention, the gradation control section does not have this clock oscillator. A delay circuit 15 generates a timing signal similar to that of this clock oscillator. In addition, the timing signal is 2 between the fields for controlling the brightness mentioned above.
It consists of a display timing signal that generates 56 pulses and a field synchronization signal that indicates the beginning of the field.

FIG. 4 is a block diagram of a delay circuit according to an embodiment of the present invention. F2 Fy! , the clock outputted from the subcircuit 14 is applied to the retriggerable one-shot multivibrator Al, the D-type flip-flop A2, the retriggerable one-shot multivibrator B1, and the D-type flip-flop B2 of the delay circuit 15.

The retriggerable one-shot multi-by-break A1 is
It is a one-shot multivibrator that keeps the output (Q) at L level for 0.5 μsec from the falling edge of the pulse, and is retriggerable. That is, when the clock is stopped for 0.5 μsec, the output d becomes L level.

On the other hand, when image data is not included in the transfer data, that is, the signal applied to the F2F demodulation circuit 14, the clock is not generated and remains at the L level.

Therefore, no trigger is applied to the retriggerable one-shot multivibrator A1, and its output (Q) becomes H level 0.5 μsec & after the fall of the last input pulse. The input of the D-type flip-flop A2 is a retriggerable one-shot multi-by-break At.
The output (Q) of this output (Q) is taken in at the rising edge of the clock and output as a display timing signal. That is, 0.5 μsec after the last falling edge of the clock, the D type flip-flop A2
A high level is added to the clock, and the high level is taken in and output at the first rising edge of the clock thereafter.

Retriggerable one-shot multi-vibration Bl and D
The configuration of the type flip-flop B2 is also the same as that of the retriggerable one-shot multi-by-break AI and D type flip-flop A2 described above. However, the time constant of the retriggerable one-shot multivibrator B1 is set to 20 μsec, and only this time constant is different.

The data contained in the modulated signal output from the modulation circuit is in blocks 81 to 8256 as shown in FIG.
Periods that do not include data are the period td after blocks 81 to B255 and the period tL after block B256.
That is. At this time, since no clock is output from the F2F demodulation circuit, the retriggerable one-shot multi-high breaks Al and Bl output H level corresponding to this period. Period td is 1.1 μsec Period tA is 42 t
t sec, the retriggerable one-shot multivibrator A1 is at the H level during both periods, and the retriggerable one-shot multivibrator B1 is at the H level during the period ti0. The output (Q) of the retriggerable one-shot multi-by-break B1 is a frame synchronization signal and becomes H level at the end of one frame shown in FIG. 3, or in other words, at the beginning of one frame.

Also retriggerable one shot multi high break A1
Since the output (Q) becomes H level in each period td and tJL, 256 pulses are outputted as a display timing signal between frames.

As described above, although a retriggerable one-shot multi-byte break is used in the embodiment of the present invention, it is also possible to use a programmable counter having a similar function. Further, the display timing signal and frame synchronization signal are set at H level for one clock cycle, but the present invention is not limited to this. For example, the output of each D type flip-flop is added to an AND gate, and the clock signal is added to the other input. This makes it possible to output a pulse with the same time width as the clock signal.

〔Effect of the invention〕

As described above, in the present invention, the gradation control unit 6 determines the clock cycle and generates the display timing signal, so according to the present invention, an oscillator or the like for generating the display timing signal is It is possible to obtain a display timing generation method that generates a display timing signal with a simple circuit without the need for the display timing signal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a timing chart of an embodiment of the present invention, Fig. 4 is a block diagram of a delay circuit, and Fig. 5 is a block diagram of a delay circuit. 5 is a timing chart of a delay circuit. 1... Demodulation circuit, 2... Delay circuit, 3... Display device. Flowchart of the patent applicant Fujitsu Machinery Co., Ltd., Fig. 1 De-4-ray circuit arc-IJ] Fig. 4

Claims (1)

[Claims] 1) A demodulation circuit (1) to which a modulation signal (S) is applied and outputs a clock signal and a data signal; It consists of a delay circuit (2) that outputs, and a display device (3) that captures the data signal output from the demodulation circuit (1) using the clock signal and displays the data in synchronization with the display timing signal. A display timing generation method characterized by: 2) The data signal is luminance data, and the display means corresponds to the luminance data and lights up the display elements in time division in synchronization with a display timing signal. Display timing generation method.